1 This file is a partial list of people who have contributed to the LLVM
2 project. If you have contributed a patch or made some other contribution to
3 LLVM, please submit a patch to this file to add yourself, and it will be
6 The list is sorted by surname and formatted to allow easy grepping and
7 beautification by scripts. The fields are: name (N), email (E), web-address
8 (W), PGP key ID and fingerprint (P), description (D), snail-mail address
9 (S), and (I) IRC handle.
14 W: http://www.cs.uiuc.edu/~vadve/
15 D: The Sparc64 backend, provider of much wisdom, and motivator for LLVM
19 D: LCSSA pass and related LoopUnswitch work
20 D: GVNPRE pass, TargetData refactoring, random improvements
23 D: MingW Win32 API portability layer
26 E: aaron@aaronballman.com
27 D: __declspec attributes, Windows support, general bug fixing
30 E: natebegeman@mac.com
31 D: PowerPC backend developer
32 D: Target-independent code generator and analysis improvements
35 E: dberlin@dberlin.org
36 D: ET-Forest implementation.
41 D: General bug fixing/fit & finish, mostly in Clang
44 E: neil@daikokuya.co.uk
45 D: APFloat implementation.
48 E: brukman+llvm@uiuc.edu
49 W: http://misha.brukman.net
50 D: Portions of X86 and Sparc JIT compilers, PowerPC backend
51 D: Incremental bitcode loader
55 D: The `mem2reg' pass - promotes values stored in memory to registers
58 E: bcahoon@codeaurora.org
59 D: Loop unrolling with run-time trip counts.
62 E: chandlerc@gmail.com
63 D: Hashing algorithms and interfaces
64 D: Inline cost analysis
65 D: Machine block placement pass
69 D: Fixes to the Reassociation pass, various improvement patches
72 E: evan.cheng@apple.com
73 D: ARM and X86 backends
74 D: Instruction scheduler improvements
75 D: Register allocator improvements
76 D: Loop optimizer improvements
77 D: Target-independent code generator improvements
79 N: Dan Villiom Podlaski Christiansen
83 D: LLVM Makefile improvements
84 D: Clang diagnostic & driver tweaks
88 E: jeffc@jolt-lang.org
89 W: http://jolt-lang.org
90 D: Native Win32 API portability layer
94 D: Original Autoconf support, documentation improvements, bug fixes
97 E: adasgupt@codeaurora.org
98 D: Deterministic finite automaton based infrastructure for VLIW packetization
101 E: stefanus.dutoit@rapidmind.com
102 D: Bug fixes and minor improvements
104 N: Rafael Avila de Espindola
105 E: rafael.espindola@gmail.com
109 E: alkis@evlogimenos.com
110 D: Linear scan register allocator, many codegen improvements, Java frontend
114 D: Basic-block autovectorization, PowerPC backend improvements
117 E: pizza@parseerror.com
118 D: Miscellaneous bug fixes
122 W: http://www.students.uiuc.edu/~gaeke/
123 D: Portions of X86 static and JIT compilers; initial SparcV8 backend
124 D: Dynamic trace optimizer
125 D: FreeBSD/X86 compatibility fixes, the llvm-nm tool
128 E: nicolas.geoffray@lip6.fr
129 W: http://www-src.lip6.fr/homepages/Nicolas.Geoffray/
130 D: PPC backend fixes for Linux
133 D: Portions of the PowerPC backend
136 E: saemghani@gmail.com
137 D: Callgraph class cleanups
139 N: Mikhail Glushenkov
140 E: foldr@codedgers.com
145 D: Miscellaneous bug fixes
148 E: david@goodwinz.net
149 D: Thumb-2 code generator
152 E: greened@obbligato.org
153 D: Miscellaneous bug fixes
154 D: Register allocation refactoring
158 D: Improvements for space efficiency
161 E: grosbach@apple.com
162 D: SjLj exception handling support
163 D: General fixes and improvements for the ARM back-end
165 D: ARM integrated assembler and assembly parser
169 D: PBQP-based register allocator
172 E: gordonhenriksen@mac.com
173 D: Pluggable GC support
177 N: Raul Fernandes Herbster
178 E: raul@dsc.ufcg.edu.br
179 D: JIT support for ARM
182 E: arathorn@fastwebnet.it
183 D: Visual C++ compatibility fixes
186 E: patjenk@wam.umd.edu
191 D: ARM constant islands improvements
192 D: Tail merging improvements
193 D: Rewrite X87 back end
194 D: Use APFloat for floating point constants widely throughout compiler
195 D: Implement X87 long double
198 E: kungfoomaster@nondot.org
199 D: Support for packed types
203 D: Author of LLVM Ada bindings
206 W: http://randomhacks.net/
207 D: llvm-config script
209 N: Anton Korobeynikov
211 D: Mingw32 fixes, cross-compiling support, stdcall/fastcall calling conv.
212 D: x86/linux PIC codegen, aliases, regparm/visibility attributes
213 D: Switch lowering refactoring
217 D: Author of the original C backend
220 E: benny.kra@gmail.com
221 D: Miscellaneous bug fixes
224 E: sundeepk@codeaurora.org
225 D: Implemented DFA-based target independent VLIW packetizer
228 E: christopher.lamb@gmail.com
229 D: aligned load/store support, parts of noalias and restrict support
230 D: vreg subreg infrastructure, X86 codegen improvements based on subregs
235 D: Improvements to the PPC backend, instruction scheduling
236 D: Debug and Dwarf implementation
237 D: Auto upgrade mangler
238 D: llvm-gcc4 svn wrangler
242 W: http://nondot.org/~sabre/
243 D: Primary architect of LLVM
245 N: Tanya Lattner (Tanya Brethour)
247 W: http://nondot.org/~tonic/
248 D: The initial llvm-ar tool, converted regression testsuite to dejagnu
249 D: Modulo scheduling in the SparcV9 backend
250 D: Release manager (1.7+)
253 E: alenhar2@cs.uiuc.edu
254 W: http://www.lenharth.org/~andrewl/
256 D: Sampling based profiling
260 D: PredicateSimplifier pass
262 N: Tony Linthicum, et. al.
263 E: tlinth@codeaurora.org
264 D: Backend for Qualcomm's Hexagon VLIW processor.
266 N: Bruno Cardoso Lopes
267 E: bruno.cardoso@gmail.com
268 W: http://www.brunocardoso.org
272 E: duraid@octopus.com.au
273 W: http://kinoko.c.u-tokyo.ac.jp/~duraid/
274 D: IA64 backend, BigBlock register allocator
277 E: rjmccall@apple.com
278 D: Clang semantic analysis and IR generation
281 E: michael.mccracken@gmail.com
282 D: Line number support for llvmgcc
284 N: Vladimir Merzliakov
286 D: Test suite fixes for FreeBSD
290 D: Added STI Cell SPU backend.
294 D: Support for implicit TLS model used with MS VC runtime
297 E: geek4civic@gmail.com
298 E: chapuni@hf.rim.or.jp
299 D: Cygwin and MinGW support.
303 N: Edward O'Callaghan
304 E: eocallaghan@auroraux.org
305 W: http://www.auroraux.org
306 D: Add Clang support with various other improvements to utils/NewNightlyTest.pl
307 D: Fix and maintain Solaris & AuroraUX support for llvm, various build warnings
308 D: and error clean ups.
312 D: Visual C++ compatibility fixes
314 N: Jakob Stoklund Olesen
316 D: Machine code verifier
318 D: Fast register allocator
319 D: Greedy register allocator
327 D: LTO tool, PassManager rewrite, Loop Pass Manager, Loop Rotate
328 D: GCC PCH Integration (llvm-gcc), llvm-gcc improvements
329 D: Optimizer improvements, Loop Index Split
332 E: peckw@wesleypeck.com
333 W: http://wesleypeck.com/
334 D: MicroBlaze backend
337 E: pichet2000@gmail.com
341 W: http://vladimir_prus.blogspot.com
343 D: Made inst_iterator behave like a proper iterator, LowerConstantExprs pass
346 E: kalle.rasikila@nokia.com
347 D: Some bugfixes to CellSPU
351 D: Cmake dependency chain and various bug fixes
354 E: alexr@leftfield.org
356 D: ARM calling conventions rewrite, hard float support
359 E: mcrosier@apple.com
360 D: ARM fast-isel improvements
361 D: Performance monitoring
364 E: nadav.rotem@intel.com
365 D: Vector code generation improvements.
368 E: roman@codedgers.com
373 D: Ada support in llvm-gcc
375 D: Exception handling improvements
376 D: Type legalizer rewrite
380 D: Graph coloring register allocator for the Sparc64 backend
382 N: Arnold Schwaighofer
383 E: arnold.schwaighofer@gmail.com
384 D: Tail call optimization for the x86 backend
388 D: Miscellaneous bug fixes
391 E: ashukla@cs.uiuc.edu
394 N: Michael J. Spencer
395 E: bigcheesegs@gmail.com
396 D: Shepherding Windows COFF support into MC.
397 D: Lots of Windows stuff.
400 E: rspencer@reidspencer.com
401 W: http://reidspencer.com/
402 D: Lots of stuff, see: http://wiki.llvm.org/index.php/User:Reid
405 E: edwintorok@gmail.com
406 D: Miscellaneous bug fixes
410 D: C++ bugs filed, and C++ front-end bug fixes.
412 N: Lauro Ramos Venancio
413 E: lauro.venancio@indt.org.br
414 D: ARM backend improvements
415 D: Thread Local Storage implementation
418 E: wendling@apple.com
419 D: Exception handling
423 E: bob.wilson@acm.org
424 D: Advanced SIMD (NEON) support in the ARM backend