4 Author: Will Deacon <will.deacon@arm.com>
5 Date : 07 September 2012
7 This document is based on the ARM booting document by Russell King and
8 is relevant to all public releases of the AArch64 Linux kernel.
10 The AArch64 exception model is made up of a number of exception levels
11 (EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
12 counterpart. EL2 is the hypervisor level and exists only in non-secure
13 mode. EL3 is the highest priority level and exists only in secure mode.
15 For the purposes of this document, we will use the term `boot loader'
16 simply to define all software that executes on the CPU(s) before control
17 is passed to the Linux kernel. This may include secure monitor and
18 hypervisor code, or it may just be a handful of instructions for
19 preparing a minimal boot environment.
21 Essentially, the boot loader should provide (as a minimum) the
24 1. Setup and initialise the RAM
25 2. Setup the device tree
26 3. Decompress the kernel image
27 4. Call the kernel image
30 1. Setup and initialise RAM
31 ---------------------------
33 Requirement: MANDATORY
35 The boot loader is expected to find and initialise all RAM that the
36 kernel will use for volatile data storage in the system. It performs
37 this in a machine dependent manner. (It may use internal algorithms
38 to automatically locate and size all RAM, or it may use knowledge of
39 the RAM in the machine, or any other method the boot loader designer
43 2. Setup the device tree
44 -------------------------
46 Requirement: MANDATORY
48 The device tree blob (dtb) must be no bigger than 2 megabytes in size
49 and placed at a 2-megabyte boundary within the first 512 megabytes from
50 the start of the kernel image. This is to allow the kernel to map the
51 blob using a single section mapping in the initial page tables.
54 3. Decompress the kernel image
55 ------------------------------
59 The AArch64 kernel does not currently provide a decompressor and
60 therefore requires decompression (gzip etc.) to be performed by the boot
61 loader if a compressed Image target (e.g. Image.gz) is used. For
62 bootloaders that do not implement this requirement, the uncompressed
63 Image target is available instead.
66 4. Call the kernel image
67 ------------------------
69 Requirement: MANDATORY
71 The decompressed kernel image contains a 64-byte header as follows:
73 u32 code0; /* Executable code */
74 u32 code1; /* Executable code */
75 u64 text_offset; /* Image load offset */
76 u64 res0 = 0; /* reserved */
77 u64 res1 = 0; /* reserved */
78 u64 res2 = 0; /* reserved */
79 u64 res3 = 0; /* reserved */
80 u64 res4 = 0; /* reserved */
81 u32 magic = 0x644d5241; /* Magic number, little endian, "ARM\x64" */
82 u32 res5 = 0; /* reserved */
87 - code0/code1 are responsible for branching to stext.
89 The image must be placed at the specified offset (currently 0x80000)
90 from the start of the system RAM and called there. The start of the
91 system RAM must be aligned to 2MB.
93 Before jumping into the kernel, the following conditions must be met:
95 - Quiesce all DMA capable devices so that memory does not get
96 corrupted by bogus network packets or disk data. This will save
97 you many hours of debug.
99 - Primary CPU general-purpose register settings
100 x0 = physical address of device tree blob (dtb) in system RAM.
101 x1 = 0 (reserved for future use)
102 x2 = 0 (reserved for future use)
103 x3 = 0 (reserved for future use)
106 All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
108 The CPU must be in either EL2 (RECOMMENDED in order to have access to
109 the virtualisation extensions) or non-secure EL1.
113 Instruction cache may be on or off.
114 The address range corresponding to the loaded kernel image must be
115 cleaned to the PoC. In the presence of a system cache or other
116 coherent masters with caches enabled, this will typically require
117 cache maintenance by VA rather than set/way operations.
118 System caches which respect the architected cache maintenance by VA
119 operations must be configured and may be enabled.
120 System caches which do not respect architected cache maintenance by VA
121 operations (not recommended) must be configured and disabled.
124 CNTFRQ must be programmed with the timer frequency.
125 If entering the kernel at EL1, CNTHCTL_EL2 must have EL1PCTEN (bit 0)
129 All CPUs to be booted by the kernel must be part of the same coherency
130 domain on entry to the kernel. This may require IMPLEMENTATION DEFINED
131 initialisation to enable the receiving of maintenance operations on
135 All writable architected system registers at the exception level where
136 the kernel image will be entered must be initialised by software at a
137 higher exception level to prevent execution in an UNKNOWN state.
139 The boot loader is expected to enter the kernel on each CPU in the
142 - The primary CPU must jump directly to the first instruction of the
143 kernel image. The device tree blob passed by this CPU must contain
146 1. An 'enable-method' property. Currently, the only supported value
147 for this field is the string "spin-table".
149 2. A 'cpu-release-addr' property identifying a 64-bit,
150 zero-initialised memory location.
152 It is expected that the bootloader will generate these device tree
153 properties and insert them into the blob prior to kernel entry.
155 - Any secondary CPUs must spin outside of the kernel in a reserved area
156 of memory (communicated to the kernel by a /memreserve/ region in the
157 device tree) polling their cpu-release-addr location, which must be
158 contained in the reserved region. A wfe instruction may be inserted
159 to reduce the overhead of the busy-loop and a sev will be issued by
160 the primary CPU. When a read of the location pointed to by the
161 cpu-release-addr returns a non-zero value, the CPU must jump directly
164 - Secondary CPU general-purpose register settings
165 x0 = 0 (reserved for future use)
166 x1 = 0 (reserved for future use)
167 x2 = 0 (reserved for future use)
168 x3 = 0 (reserved for future use)