Documentation/devicetree/bindings/arm/idle-states.txt

   1 ==========================================
   2 ARM idle states binding description
   3 ==========================================
   4
   5 ==========================================
   6 1 - Introduction
   7 ==========================================
   8
   9 ARM systems contain HW capable of managing power consumption dynamically,
  10 where cores can be put in different low-power states (ranging from simple
  11 wfi to power gating) according to OS PM policies. The CPU states representing
  12 the range of dynamic idle states that a processor can enter at run-time, can be
  13 specified through device tree bindings representing the parameters required
  14 to enter/exit specific idle states on a given processor.
  15
  16 According to the Server Base System Architecture document (SBSA, [3]), the
  17 power states an ARM CPU can be put into are identified by the following list:
  18
  19 - Running
  20 - Idle_standby
  21 - Idle_retention
  22 - Sleep
  23 - Off
  24
  25 The power states described in the SBSA document define the basic CPU states on
  26 top of which ARM platforms implement power management schemes that allow an OS
  27 PM implementation to put the processor in different idle states (which include
  28 states listed above; "off" state is not an idle state since it does not have
  29 wake-up capabilities, hence it is not considered in this document).
  30
  31 Idle state parameters (eg entry latency) are platform specific and need to be
  32 characterized with bindings that provide the required information to OS PM
  33 code so that it can build the required tables and use them at runtime.
  34
  35 The device tree binding definition for ARM idle states is the subject of this
  36 document.
  37
  38 ===========================================
  39 2 - idle-states definitions
  40 ===========================================
  41
  42 Idle states are characterized for a specific system through a set of
  43 timing and energy related properties, that underline the HW behaviour
  44 triggered upon idle states entry and exit.
  45
  46 The following diagram depicts the CPU execution phases and related timing
  47 properties required to enter and exit an idle state:
  48
  49 ..__[EXEC]__|__[PREP]__|__[ENTRY]__|__[IDLE]__|__[EXIT]__|__[EXEC]__..
  50             |          |           |          |          |
  51
  52             |<------ entry ------->|
  53             |       latency        |
  54                                               |<- exit ->|
  55                                               |  latency |
  56             |<-------- min-residency -------->|
  57                        |<-------  wakeup-latency ------->|
  58
  59                 Diagram 1: CPU idle state execution phases
  60
  61 EXEC:   Normal CPU execution.
  62
  63 PREP:   Preparation phase before committing the hardware to idle mode
  64         like cache flushing. This is abortable on pending wake-up
  65         event conditions. The abort latency is assumed to be negligible
  66         (i.e. less than the ENTRY + EXIT duration). If aborted, CPU
  67         goes back to EXEC. This phase is optional. If not abortable,
  68         this should be included in the ENTRY phase instead.
  69
  70 ENTRY:  The hardware is committed to idle mode. This period must run
  71         to completion up to IDLE before anything else can happen.
  72
  73 IDLE:   This is the actual energy-saving idle period. This may last
  74         between 0 and infinite time, until a wake-up event occurs.
  75
  76 EXIT:   Period during which the CPU is brought back to operational
  77         mode (EXEC).
  78
  79 entry-latency: Worst case latency required to enter the idle state. The
  80 exit-latency may be guaranteed only after entry-latency has passed.
  81
  82 min-residency: Minimum period, including preparation and entry, for a given
  83 idle state to be worthwhile energywise.
  84
  85 wakeup-latency: Maximum delay between the signaling of a wake-up event and the
  86 CPU being able to execute normal code again. If not specified, this is assumed
  87 to be entry-latency + exit-latency.
  88
  89 These timing parameters can be used by an OS in different circumstances.
  90
  91 An idle CPU requires the expected min-residency time to select the most
  92 appropriate idle state based on the expected expiry time of the next IRQ
  93 (ie wake-up) that causes the CPU to return to the EXEC phase.
  94
  95 An operating system scheduler may need to compute the shortest wake-up delay
  96 for CPUs in the system by detecting how long will it take to get a CPU out
  97 of an idle state, eg:
  98
  99 wakeup-delay = exit-latency + max(entry-latency - (now - entry-timestamp), 0)
 100
 101 In other words, the scheduler can make its scheduling decision by selecting
 102 (eg waking-up) the CPU with the shortest wake-up latency.
 103 The wake-up latency must take into account the entry latency if that period
 104 has not expired. The abortable nature of the PREP period can be ignored
 105 if it cannot be relied upon (e.g. the PREP deadline may occur much sooner than
 106 the worst case since it depends on the CPU operating conditions, ie caches
 107 state).
 108
 109 An OS has to reliably probe the wakeup-latency since some devices can enforce
 110 latency constraints guarantees to work properly, so the OS has to detect the
 111 worst case wake-up latency it can incur if a CPU is allowed to enter an
 112 idle state, and possibly to prevent that to guarantee reliable device
 113 functioning.
 114
 115 The min-residency time parameter deserves further explanation since it is
 116 expressed in time units but must factor in energy consumption coefficients.
 117
 118 The energy consumption of a cpu when it enters a power state can be roughly
 119 characterised by the following graph:
 120
 121                |
 122                |
 123                |
 124            e   |
 125            n   |                                      /---
 126            e   |                               /------
 127            r   |                        /------
 128            g   |                  /-----
 129            y   |           /------
 130                |       ----
 131                |      /|
 132                |     / |
 133                |    /  |
 134                |   /   |
 135                |  /    |
 136                | /     |
 137                |/      |
 138           -----|-------+----------------------------------
 139               0|       1                              time(ms)
 140
 141                 Graph 1: Energy vs time example
 142
 143 The graph is split in two parts delimited by time 1ms on the X-axis.
 144 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
 145 and denotes the energy costs incurred whilst entering and leaving the idle
 146 state.
 147 The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
 148 shallower slope and essentially represents the energy consumption of the idle
 149 state.
 150
 151 min-residency is defined for a given idle state as the minimum expected
 152 residency time for a state (inclusive of preparation and entry) after
 153 which choosing that state become the most energy efficient option. A good
 154 way to visualise this, is by taking the same graph above and comparing some
 155 states energy consumptions plots.
 156
 157 For sake of simplicity, let's consider a system with two idle states IDLE1,
 158 and IDLE2:
 159
 160           |
 161           |
 162           |
 163           |                                                  /-- IDLE1
 164        e  |                                              /---
 165        n  |                                         /----
 166        e  |                                     /---
 167        r  |                                /-----/--------- IDLE2
 168        g  |                    /-------/---------
 169        y  |        ------------    /---|
 170           |       /           /----    |
 171           |      /        /---         |
 172           |     /    /----             |
 173           |    / /---                  |
 174           |   ---                      |
 175           |  /                         |
 176           | /                          |
 177           |/                           |                  time
 178        ---/----------------------------+------------------------
 179           |IDLE1-energy < IDLE2-energy | IDLE2-energy < IDLE1-energy
 180                                        |
 181                                 IDLE2-min-residency
 182
 183                 Graph 2: idle states min-residency example
 184
 185 In graph 2 above, that takes into account idle states entry/exit energy
 186 costs, it is clear that if the idle state residency time (ie time till next
 187 wake-up IRQ) is less than IDLE2-min-residency, IDLE1 is the better idle state
 188 choice energywise.
 189
 190 This is mainly down to the fact that IDLE1 entry/exit energy costs are lower
 191 than IDLE2.
 192
 193 However, the lower power consumption (ie shallower energy curve slope) of idle
 194 state IDLE2 implies that after a suitable time, IDLE2 becomes more energy
 195 efficient.
 196
 197 The time at which IDLE2 becomes more energy efficient than IDLE1 (and other
 198 shallower states in a system with multiple idle states) is defined
 199 IDLE2-min-residency and corresponds to the time when energy consumption of
 200 IDLE1 and IDLE2 states breaks even.
 201
 202 The definitions provided in this section underpin the idle states
 203 properties specification that is the subject of the following sections.
 204
 205 ===========================================
 206 3 - idle-states node
 207 ===========================================
 208
 209 ARM processor idle states are defined within the idle-states node, which is
 210 a direct child of the cpus node [1] and provides a container where the
 211 processor idle states, defined as device tree nodes, are listed.
 212
 213 - idle-states node
 214
 215         Usage: Optional - On ARM systems, it is a container of processor idle
 216                           states nodes. If the system does not provide CPU
 217                           power management capabilities or the processor just
 218                           supports idle_standby an idle-states node is not
 219                           required.
 220
 221         Description: idle-states node is a container node, where its
 222                      subnodes describe the CPU idle states.
 223
 224         Node name must be "idle-states".
 225
 226         The idle-states node's parent node must be the cpus node.
 227
 228         The idle-states node's child nodes can be:
 229
 230         - one or more state nodes
 231
 232         Any other configuration is considered invalid.
 233
 234         An idle-states node defines the following properties:
 235
 236         - entry-method
 237                 Value type: <stringlist>
 238                 Usage and definition depend on ARM architecture version.
 239                         # On ARM v8 64-bit this property is required and must
 240                           be one of:
 241                            - "psci" (see bindings in [2])
 242                         # On ARM 32-bit systems this property is optional
 243
 244 The nodes describing the idle states (state) can only be defined within the
 245 idle-states node, any other configuration is considered invalid and therefore
 246 must be ignored.
 247
 248 ===========================================
 249 4 - state node
 250 ===========================================
 251
 252 A state node represents an idle state description and must be defined as
 253 follows:
 254
 255 - state node
 256
 257         Description: must be child of the idle-states node
 258
 259         The state node name shall follow standard device tree naming
 260         rules ([5], 2.2.1 "Node names"), in particular state nodes which
 261         are siblings within a single common parent must be given a unique name.
 262
 263         The idle state entered by executing the wfi instruction (idle_standby
 264         SBSA,[3][4]) is considered standard on all ARM platforms and therefore
 265         must not be listed.
 266
 267         With the definitions provided above, the following list represents
 268         the valid properties for a state node:
 269
 270         - compatible
 271                 Usage: Required
 272                 Value type: <stringlist>
 273                 Definition: Must be "arm,idle-state".
 274
 275         - local-timer-stop
 276                 Usage: See definition
 277                 Value type: <none>
 278                 Definition: if present the CPU local timer control logic is
 279                             lost on state entry, otherwise it is retained.
 280
 281         - entry-latency-us
 282                 Usage: Required
 283                 Value type: <prop-encoded-array>
 284                 Definition: u32 value representing worst case latency in
 285                             microseconds required to enter the idle state.
 286                             The exit-latency-us duration may be guaranteed
 287                             only after entry-latency-us has passed.
 288
 289         - exit-latency-us
 290                 Usage: Required
 291                 Value type: <prop-encoded-array>
 292                 Definition: u32 value representing worst case latency
 293                             in microseconds required to exit the idle state.
 294
 295         - min-residency-us
 296                 Usage: Required
 297                 Value type: <prop-encoded-array>
 298                 Definition: u32 value representing minimum residency duration
 299                             in microseconds, inclusive of preparation and
 300                             entry, for this idle state to be considered
 301                             worthwhile energy wise (refer to section 2 of
 302                             this document for a complete description).
 303
 304         - wakeup-latency-us:
 305                 Usage: Optional
 306                 Value type: <prop-encoded-array>
 307                 Definition: u32 value representing maximum delay between the
 308                             signaling of a wake-up event and the CPU being
 309                             able to execute normal code again. If omitted,
 310                             this is assumed to be equal to:
 311
 312                                 entry-latency-us + exit-latency-us
 313
 314                             It is important to supply this value on systems
 315                             where the duration of PREP phase (see diagram 1,
 316                             section 2) is non-neglibigle.
 317                             In such systems entry-latency-us + exit-latency-us
 318                             will exceed wakeup-latency-us by this duration.
 319
 320         - status:
 321                 Usage: Optional
 322                 Value type: <string>
 323                 Definition: A standard device tree property [5] that indicates
 324                             the operational status of an idle-state.
 325                             If present, it shall be:
 326                             "okay": to indicate that the idle state is
 327                                     operational.
 328                             "disabled": to indicate that the idle state has
 329                                         been disabled in firmware so it is not
 330                                         operational.
 331                             If the property is not present the idle-state must
 332                             be considered operational.
 333
 334         In addition to the properties listed above, a state node may require
 335         additional properties specifics to the entry-method defined in the
 336         idle-states node, please refer to the entry-method bindings
 337         documentation for properties definitions.
 338
 339 ===========================================
 340 4 - Examples
 341 ===========================================
 342
 343 Example 1 (ARM 64-bit, 16-cpu system, PSCI enable-method):
 344
 345 cpus {
 346         #size-cells = <0>;
 347         #address-cells = <2>;
 348
 349         CPU0: cpu@0 {
 350                 device_type = "cpu";
 351                 compatible = "arm,cortex-a57";
 352                 reg = <0x0 0x0>;
 353                 enable-method = "psci";
 354                 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
 355                                    &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
 356         };
 357
 358         CPU1: cpu@1 {
 359                 device_type = "cpu";
 360                 compatible = "arm,cortex-a57";
 361                 reg = <0x0 0x1>;
 362                 enable-method = "psci";
 363                 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
 364                                    &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
 365         };
 366
 367         CPU2: cpu@100 {
 368                 device_type = "cpu";
 369                 compatible = "arm,cortex-a57";
 370                 reg = <0x0 0x100>;
 371                 enable-method = "psci";
 372                 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
 373                                    &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
 374         };
 375
 376         CPU3: cpu@101 {
 377                 device_type = "cpu";
 378                 compatible = "arm,cortex-a57";
 379                 reg = <0x0 0x101>;
 380                 enable-method = "psci";
 381                 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
 382                                    &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
 383         };
 384
 385         CPU4: cpu@10000 {
 386                 device_type = "cpu";
 387                 compatible = "arm,cortex-a57";
 388                 reg = <0x0 0x10000>;
 389                 enable-method = "psci";
 390                 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
 391                                    &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
 392         };
 393
 394         CPU5: cpu@10001 {
 395                 device_type = "cpu";
 396                 compatible = "arm,cortex-a57";
 397                 reg = <0x0 0x10001>;
 398                 enable-method = "psci";
 399                 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
 400                                    &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
 401         };
 402
 403         CPU6: cpu@10100 {
 404                 device_type = "cpu";
 405                 compatible = "arm,cortex-a57";
 406                 reg = <0x0 0x10100>;
 407                 enable-method = "psci";
 408                 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
 409                                    &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
 410         };
 411
 412         CPU7: cpu@10101 {
 413                 device_type = "cpu";
 414                 compatible = "arm,cortex-a57";
 415                 reg = <0x0 0x10101>;
 416                 enable-method = "psci";
 417                 cpu-idle-states = <&CPU_RETENTION_0_0 &CPU_SLEEP_0_0
 418                                    &CLUSTER_RETENTION_0 &CLUSTER_SLEEP_0>;
 419         };
 420
 421         CPU8: cpu@100000000 {
 422                 device_type = "cpu";
 423                 compatible = "arm,cortex-a53";
 424                 reg = <0x1 0x0>;
 425                 enable-method = "psci";
 426                 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
 427                                    &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
 428         };
 429
 430         CPU9: cpu@100000001 {
 431                 device_type = "cpu";
 432                 compatible = "arm,cortex-a53";
 433                 reg = <0x1 0x1>;
 434                 enable-method = "psci";
 435                 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
 436                                    &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
 437         };
 438
 439         CPU10: cpu@100000100 {
 440                 device_type = "cpu";
 441                 compatible = "arm,cortex-a53";
 442                 reg = <0x1 0x100>;
 443                 enable-method = "psci";
 444                 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
 445                                    &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
 446         };
 447
 448         CPU11: cpu@100000101 {
 449                 device_type = "cpu";
 450                 compatible = "arm,cortex-a53";
 451                 reg = <0x1 0x101>;
 452                 enable-method = "psci";
 453                 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
 454                                    &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
 455         };
 456
 457         CPU12: cpu@100010000 {
 458                 device_type = "cpu";
 459                 compatible = "arm,cortex-a53";
 460                 reg = <0x1 0x10000>;
 461                 enable-method = "psci";
 462                 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
 463                                    &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
 464         };
 465
 466         CPU13: cpu@100010001 {
 467                 device_type = "cpu";
 468                 compatible = "arm,cortex-a53";
 469                 reg = <0x1 0x10001>;
 470                 enable-method = "psci";
 471                 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
 472                                    &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
 473         };
 474
 475         CPU14: cpu@100010100 {
 476                 device_type = "cpu";
 477                 compatible = "arm,cortex-a53";
 478                 reg = <0x1 0x10100>;
 479                 enable-method = "psci";
 480                 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
 481                                    &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
 482         };
 483
 484         CPU15: cpu@100010101 {
 485                 device_type = "cpu";
 486                 compatible = "arm,cortex-a53";
 487                 reg = <0x1 0x10101>;
 488                 enable-method = "psci";
 489                 cpu-idle-states = <&CPU_RETENTION_1_0 &CPU_SLEEP_1_0
 490                                    &CLUSTER_RETENTION_1 &CLUSTER_SLEEP_1>;
 491         };
 492
 493         idle-states {
 494                 entry-method = "arm,psci";
 495
 496                 CPU_RETENTION_0_0: cpu-retention-0-0 {
 497                         compatible = "arm,idle-state";
 498                         arm,psci-suspend-param = <0x0010000>;
 499                         entry-latency-us = <20>;
 500                         exit-latency-us = <40>;
 501                         min-residency-us = <80>;
 502                 };
 503
 504                 CLUSTER_RETENTION_0: cluster-retention-0 {
 505                         compatible = "arm,idle-state";
 506                         local-timer-stop;
 507                         arm,psci-suspend-param = <0x1010000>;
 508                         entry-latency-us = <50>;
 509                         exit-latency-us = <100>;
 510                         min-residency-us = <250>;
 511                         wakeup-latency-us = <130>;
 512                 };
 513
 514                 CPU_SLEEP_0_0: cpu-sleep-0-0 {
 515                         compatible = "arm,idle-state";
 516                         local-timer-stop;
 517                         arm,psci-suspend-param = <0x0010000>;
 518                         entry-latency-us = <250>;
 519                         exit-latency-us = <500>;
 520                         min-residency-us = <950>;
 521                 };
 522
 523                 CLUSTER_SLEEP_0: cluster-sleep-0 {
 524                         compatible = "arm,idle-state";
 525                         local-timer-stop;
 526                         arm,psci-suspend-param = <0x1010000>;
 527                         entry-latency-us = <600>;
 528                         exit-latency-us = <1100>;
 529                         min-residency-us = <2700>;
 530                         wakeup-latency-us = <1500>;
 531                 };
 532
 533                 CPU_RETENTION_1_0: cpu-retention-1-0 {
 534                         compatible = "arm,idle-state";
 535                         arm,psci-suspend-param = <0x0010000>;
 536                         entry-latency-us = <20>;
 537                         exit-latency-us = <40>;
 538                         min-residency-us = <90>;
 539                 };
 540
 541                 CLUSTER_RETENTION_1: cluster-retention-1 {
 542                         compatible = "arm,idle-state";
 543                         local-timer-stop;
 544                         arm,psci-suspend-param = <0x1010000>;
 545                         entry-latency-us = <50>;
 546                         exit-latency-us = <100>;
 547                         min-residency-us = <270>;
 548                         wakeup-latency-us = <100>;
 549                 };
 550
 551                 CPU_SLEEP_1_0: cpu-sleep-1-0 {
 552                         compatible = "arm,idle-state";
 553                         local-timer-stop;
 554                         arm,psci-suspend-param = <0x0010000>;
 555                         entry-latency-us = <70>;
 556                         exit-latency-us = <100>;
 557                         min-residency-us = <300>;
 558                         wakeup-latency-us = <150>;
 559                 };
 560
 561                 CLUSTER_SLEEP_1: cluster-sleep-1 {
 562                         compatible = "arm,idle-state";
 563                         local-timer-stop;
 564                         arm,psci-suspend-param = <0x1010000>;
 565                         entry-latency-us = <500>;
 566                         exit-latency-us = <1200>;
 567                         min-residency-us = <3500>;
 568                         wakeup-latency-us = <1300>;
 569                 };
 570         };
 571
 572 };
 573
 574 Example 2 (ARM 32-bit, 8-cpu system, two clusters):
 575
 576 cpus {
 577         #size-cells = <0>;
 578         #address-cells = <1>;
 579
 580         CPU0: cpu@0 {
 581                 device_type = "cpu";
 582                 compatible = "arm,cortex-a15";
 583                 reg = <0x0>;
 584                 cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
 585         };
 586
 587         CPU1: cpu@1 {
 588                 device_type = "cpu";
 589                 compatible = "arm,cortex-a15";
 590                 reg = <0x1>;
 591                 cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
 592         };
 593
 594         CPU2: cpu@2 {
 595                 device_type = "cpu";
 596                 compatible = "arm,cortex-a15";
 597                 reg = <0x2>;
 598                 cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
 599         };
 600
 601         CPU3: cpu@3 {
 602                 device_type = "cpu";
 603                 compatible = "arm,cortex-a15";
 604                 reg = <0x3>;
 605                 cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
 606         };
 607
 608         CPU4: cpu@100 {
 609                 device_type = "cpu";
 610                 compatible = "arm,cortex-a7";
 611                 reg = <0x100>;
 612                 cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
 613         };
 614
 615         CPU5: cpu@101 {
 616                 device_type = "cpu";
 617                 compatible = "arm,cortex-a7";
 618                 reg = <0x101>;
 619                 cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
 620         };
 621
 622         CPU6: cpu@102 {
 623                 device_type = "cpu";
 624                 compatible = "arm,cortex-a7";
 625                 reg = <0x102>;
 626                 cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
 627         };
 628
 629         CPU7: cpu@103 {
 630                 device_type = "cpu";
 631                 compatible = "arm,cortex-a7";
 632                 reg = <0x103>;
 633                 cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
 634         };
 635
 636         idle-states {
 637                 CPU_SLEEP_0_0: cpu-sleep-0-0 {
 638                         compatible = "arm,idle-state";
 639                         local-timer-stop;
 640                         entry-latency-us = <200>;
 641                         exit-latency-us = <100>;
 642                         min-residency-us = <400>;
 643                         wakeup-latency-us = <250>;
 644                 };
 645
 646                 CLUSTER_SLEEP_0: cluster-sleep-0 {
 647                         compatible = "arm,idle-state";
 648                         local-timer-stop;
 649                         entry-latency-us = <500>;
 650                         exit-latency-us = <1500>;
 651                         min-residency-us = <2500>;
 652                         wakeup-latency-us = <1700>;
 653                 };
 654
 655                 CPU_SLEEP_1_0: cpu-sleep-1-0 {
 656                         compatible = "arm,idle-state";
 657                         local-timer-stop;
 658                         entry-latency-us = <300>;
 659                         exit-latency-us = <500>;
 660                         min-residency-us = <900>;
 661                         wakeup-latency-us = <600>;
 662                 };
 663
 664                 CLUSTER_SLEEP_1: cluster-sleep-1 {
 665                         compatible = "arm,idle-state";
 666                         local-timer-stop;
 667                         entry-latency-us = <800>;
 668                         exit-latency-us = <2000>;
 669                         min-residency-us = <6500>;
 670                         wakeup-latency-us = <2300>;
 671                 };
 672         };
 673
 674 };
 675
 676 ===========================================
 677 5 - References
 678 ===========================================
 679
 680 [1] ARM Linux Kernel documentation - CPUs bindings
 681     Documentation/devicetree/bindings/arm/cpus.txt
 682
 683 [2] ARM Linux Kernel documentation - PSCI bindings
 684     Documentation/devicetree/bindings/arm/psci.txt
 685
 686 [3] ARM Server Base System Architecture (SBSA)
 687     http://infocenter.arm.com/help/index.jsp
 688
 689 [4] ARM Architecture Reference Manuals
 690     http://infocenter.arm.com/help/index.jsp
 691
 692 [5] ePAPR standard
 693     https://www.power.org/documentation/epapr-version-1-1/