Documentation/devicetree/bindings/clock/exynos5433-clock.txt

   1 * Samsung Exynos5433 CMU (Clock Management Units)
   2
   3 The Exynos5433 clock controller generates and supplies clock to various
   4 controllers within the Exynos5433 SoC.
   5
   6 Required Properties:
   7
   8 - compatible: should be one of the following.
   9   - "samsung,exynos5433-cmu-top"   - clock controller compatible for CMU_TOP
  10     which generates clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
  11     domains and bus clocks.
  12   - "samsung,exynos5433-cmu-cpif"  - clock controller compatible for CMU_CPIF
  13     which generates clocks for LLI (Low Latency Interface) IP.
  14   - "samsung,exynos5433-cmu-mif"   - clock controller compatible for CMU_MIF
  15     which generates clocks for DRAM Memory Controller domain.
  16   - "samsung,exynos5433-cmu-peric" - clock controller compatible for CMU_PERIC
  17     which generates clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs.
  18   - "samsung,exynos5433-cmu-peris" - clock controller compatible for CMU_PERIS
  19     which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs.
  20   - "samsung,exynos5433-cmu-fsys"  - clock controller compatible for CMU_FSYS
  21     which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs.
  22   - "samsung,exynos5433-cmu-g2d"   - clock controller compatible for CMU_G2D
  23     which generates clocks for G2D/MDMA IPs.
  24   - "samsung,exynos5433-cmu-disp"  - clock controller compatible for CMU_DISP
  25     which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs.
  26   - "samsung,exynos5433-cmu-aud"   - clock controller compatible for CMU_AUD
  27     which generates clocks for Cortex-A5/BUS/AUDIO clocks.
  28   - "samsung,exynos5433-cmu-bus0", "samsung,exynos5433-cmu-bus1"
  29     and "samsung,exynos5433-cmu-bus2" - clock controller compatible for CMU_BUS
  30     which generates global data buses clock and global peripheral buses clock.
  31   - "samsung,exynos5433-cmu-g3d"  - clock controller compatible for CMU_G3D
  32     which generates clocks for 3D Graphics Engine IP.
  33   - "samsung,exynos5433-cmu-gscl"  - clock controller compatible for CMU_GSCL
  34     which generates clocks for GSCALER IPs.
  35   - "samsung,exynos5433-cmu-apollo"- clock controller compatible for CMU_APOLLO
  36     which generates clocks for Cortex-A53 Quad-core processor.
  37   - "samsung,exynos5433-cmu-atlas" - clock controller compatible for CMU_ATLAS
  38     which generates clocks for Cortex-A57 Quad-core processor, CoreSight and
  39     L2 cache controller.
  40   - "samsung,exynos5433-cmu-mscl" - clock controller compatible for CMU_MSCL
  41     which generates clocks for M2M (Memory to Memory) scaler and JPEG IPs.
  42   - "samsung,exynos5433-cmu-mfc"  - clock controller compatible for CMU_MFC
  43     which generates clocks for MFC(Multi-Format Codec) IP.
  44   - "samsung,exynos5433-cmu-hevc" - clock controller compatible for CMU_HEVC
  45     which generates clocks for HEVC(High Efficiency Video Codec) decoder IP.
  46   - "samsung,exynos5433-cmu-isp" - clock controller compatible for CMU_ISP
  47     which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
  48   - "samsung,exynos5433-cmu-cam0" - clock controller compatible for CMU_CAM0
  49     which generates clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1}
  50     IPs.
  51
  52 - reg: physical base address of the controller and length of memory mapped
  53   region.
  54
  55 - #clock-cells: should be 1.
  56
  57 - clocks: list of the clock controller input clock identifiers,
  58         from common clock bindings. Please refer the next section
  59         to find the input clocks for a given controller.
  60
  61 - clock-names: list of the clock controller input clock names,
  62         as described in clock-bindings.txt.
  63
  64         Input clocks for top clock controller:
  65                 - oscclk
  66                 - sclk_mphy_pll
  67                 - sclk_mfc_pll
  68                 - sclk_bus_pll
  69
  70         Input clocks for cpif clock controller:
  71                 - oscclk
  72
  73         Input clocks for mif clock controller:
  74                 - oscclk
  75                 - sclk_mphy_pll
  76
  77         Input clocks for fsys clock controller:
  78                 - oscclk
  79                 - sclk_ufs_mphy
  80                 - div_aclk_fsys_200
  81                 - sclk_pcie_100_fsys
  82                 - sclk_ufsunipro_fsys
  83                 - sclk_mmc2_fsys
  84                 - sclk_mmc1_fsys
  85                 - sclk_mmc0_fsys
  86                 - sclk_usbhost30_fsys
  87                 - sclk_usbdrd30_fsys
  88
  89         Input clocks for g2d clock controller:
  90                 - oscclk
  91                 - aclk_g2d_266
  92                 - aclk_g2d_400
  93
  94         Input clocks for disp clock controller:
  95                 - oscclk
  96                 - sclk_dsim1_disp
  97                 - sclk_dsim0_disp
  98                 - sclk_dsd_disp
  99                 - sclk_decon_tv_eclk_disp
 100                 - sclk_decon_vclk_disp
 101                 - sclk_decon_eclk_disp
 102                 - sclk_decon_tv_vclk_disp
 103                 - aclk_disp_333
 104
 105         Input clocks for bus0 clock controller:
 106                 - aclk_bus0_400
 107
 108         Input clocks for bus1 clock controller:
 109                 - aclk_bus1_400
 110
 111         Input clocks for bus2 clock controller:
 112                 - oscclk
 113                 - aclk_bus2_400
 114
 115         Input clocks for g3d clock controller:
 116                 - oscclk
 117                 - aclk_g3d_400
 118
 119         Input clocks for gscl clock controller:
 120                 - oscclk
 121                 - aclk_gscl_111
 122                 - aclk_gscl_333
 123
 124         Input clocks for apollo clock controller:
 125                 - oscclk
 126                 - sclk_bus_pll_apollo
 127
 128         Input clocks for atlas clock controller:
 129                 - oscclk
 130                 - sclk_bus_pll_atlas
 131
 132         Input clocks for mscl clock controller:
 133                 - oscclk
 134                 - sclk_jpeg_mscl
 135                 - aclk_mscl_400
 136
 137         Input clocks for mfc clock controller:
 138                 - oscclk
 139                 - aclk_mfc_400
 140
 141         Input clocks for hevc clock controller:
 142                 - oscclk
 143                 - aclk_hevc_400
 144
 145         Input clocks for isp clock controller:
 146                 - oscclk
 147                 - aclk_isp_dis_400
 148                 - aclk_isp_400
 149
 150         Input clocks for cam0 clock controller:
 151                 - oscclk
 152                 - aclk_cam0_333
 153                 - aclk_cam0_400
 154                 - aclk_cam0_552
 155
 156 Each clock is assigned an identifier and client nodes can use this identifier
 157 to specify the clock which they consume.
 158
 159 All available clocks are defined as preprocessor macros in
 160 dt-bindings/clock/exynos5433.h header and can be used in device
 161 tree sources.
 162
 163 Example 1: Examples of 'oscclk' source clock node are listed below.
 164
 165         xxti: xxti {
 166                 compatible = "fixed-clock";
 167                 clock-output-names = "oscclk";
 168                 #clock-cells = <0>;
 169         };
 170
 171 Example 2: Examples of clock controller nodes are listed below.
 172
 173         cmu_top: clock-controller@10030000 {
 174                 compatible = "samsung,exynos5433-cmu-top";
 175                 reg = <0x10030000 0x0c04>;
 176                 #clock-cells = <1>;
 177
 178                 clock-names = "oscclk",
 179                         "sclk_mphy_pll",
 180                         "sclk_mfc_pll",
 181                         "sclk_bus_pll";
 182                 clocks = <&xxti>,
 183                        <&cmu_cpif CLK_SCLK_MPHY_PLL>,
 184                        <&cmu_mif CLK_SCLK_MFC_PLL>,
 185                        <&cmu_mif CLK_SCLK_BUS_PLL>;
 186         };
 187
 188         cmu_cpif: clock-controller@10fc0000 {
 189                 compatible = "samsung,exynos5433-cmu-cpif";
 190                 reg = <0x10fc0000 0x0c04>;
 191                 #clock-cells = <1>;
 192
 193                 clock-names = "oscclk";
 194                 clocks = <&xxti>;
 195         };
 196
 197         cmu_mif: clock-controller@105b0000 {
 198                 compatible = "samsung,exynos5433-cmu-mif";
 199                 reg = <0x105b0000 0x100c>;
 200                 #clock-cells = <1>;
 201
 202                 clock-names = "oscclk",
 203                         "sclk_mphy_pll";
 204                 clocks = <&xxti>,
 205                        <&cmu_cpif CLK_SCLK_MPHY_PLL>;
 206         };
 207
 208         cmu_peric: clock-controller@14c80000 {
 209                 compatible = "samsung,exynos5433-cmu-peric";
 210                 reg = <0x14c80000 0x0b08>;
 211                 #clock-cells = <1>;
 212         };
 213
 214         cmu_peris: clock-controller@10040000 {
 215                 compatible = "samsung,exynos5433-cmu-peris";
 216                 reg = <0x10040000 0x0b20>;
 217                 #clock-cells = <1>;
 218         };
 219
 220         cmu_fsys: clock-controller@156e0000 {
 221                 compatible = "samsung,exynos5433-cmu-fsys";
 222                 reg = <0x156e0000 0x0b04>;
 223                 #clock-cells = <1>;
 224
 225                 clock-names = "oscclk",
 226                         "sclk_ufs_mphy",
 227                         "div_aclk_fsys_200",
 228                         "sclk_pcie_100_fsys",
 229                         "sclk_ufsunipro_fsys",
 230                         "sclk_mmc2_fsys",
 231                         "sclk_mmc1_fsys",
 232                         "sclk_mmc0_fsys",
 233                         "sclk_usbhost30_fsys",
 234                         "sclk_usbdrd30_fsys";
 235                 clocks = <&xxti>,
 236                        <&cmu_cpif CLK_SCLK_UFS_MPHY>,
 237                        <&cmu_top CLK_DIV_ACLK_FSYS_200>,
 238                        <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
 239                        <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
 240                        <&cmu_top CLK_SCLK_MMC2_FSYS>,
 241                        <&cmu_top CLK_SCLK_MMC1_FSYS>,
 242                        <&cmu_top CLK_SCLK_MMC0_FSYS>,
 243                        <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
 244                        <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
 245         };
 246
 247         cmu_g2d: clock-controller@12460000 {
 248                 compatible = "samsung,exynos5433-cmu-g2d";
 249                 reg = <0x12460000 0x0b08>;
 250                 #clock-cells = <1>;
 251
 252                 clock-names = "oscclk",
 253                         "aclk_g2d_266",
 254                         "aclk_g2d_400";
 255                 clocks = <&xxti>,
 256                        <&cmu_top CLK_ACLK_G2D_266>,
 257                        <&cmu_top CLK_ACLK_G2D_400>;
 258         };
 259
 260         cmu_disp: clock-controller@13b90000 {
 261                 compatible = "samsung,exynos5433-cmu-disp";
 262                 reg = <0x13b90000 0x0c04>;
 263                 #clock-cells = <1>;
 264
 265                 clock-names = "oscclk",
 266                         "sclk_dsim1_disp",
 267                         "sclk_dsim0_disp",
 268                         "sclk_dsd_disp",
 269                         "sclk_decon_tv_eclk_disp",
 270                         "sclk_decon_vclk_disp",
 271                         "sclk_decon_eclk_disp",
 272                         "sclk_decon_tv_vclk_disp",
 273                         "aclk_disp_333";
 274                 clocks = <&xxti>,
 275                        <&cmu_mif CLK_SCLK_DSIM1_DISP>,
 276                        <&cmu_mif CLK_SCLK_DSIM0_DISP>,
 277                        <&cmu_mif CLK_SCLK_DSD_DISP>,
 278                        <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
 279                        <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
 280                        <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
 281                        <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
 282                        <&cmu_mif CLK_ACLK_DISP_333>;
 283         };
 284
 285         cmu_aud: clock-controller@114c0000 {
 286                 compatible = "samsung,exynos5433-cmu-aud";
 287                 reg = <0x114c0000 0x0b04>;
 288                 #clock-cells = <1>;
 289         };
 290
 291         cmu_bus0: clock-controller@13600000 {
 292                 compatible = "samsung,exynos5433-cmu-bus0";
 293                 reg = <0x13600000 0x0b04>;
 294                 #clock-cells = <1>;
 295
 296                 clock-names = "aclk_bus0_400";
 297                 clocks = <&cmu_top CLK_ACLK_BUS0_400>;
 298         };
 299
 300         cmu_bus1: clock-controller@14800000 {
 301                 compatible = "samsung,exynos5433-cmu-bus1";
 302                 reg = <0x14800000 0x0b04>;
 303                 #clock-cells = <1>;
 304
 305                 clock-names = "aclk_bus1_400";
 306                 clocks = <&cmu_top CLK_ACLK_BUS1_400>;
 307         };
 308
 309         cmu_bus2: clock-controller@13400000 {
 310                 compatible = "samsung,exynos5433-cmu-bus2";
 311                 reg = <0x13400000 0x0b04>;
 312                 #clock-cells = <1>;
 313
 314                 clock-names = "oscclk", "aclk_bus2_400";
 315                 clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
 316         };
 317
 318         cmu_g3d: clock-controller@14aa0000 {
 319                 compatible = "samsung,exynos5433-cmu-g3d";
 320                 reg = <0x14aa0000 0x1000>;
 321                 #clock-cells = <1>;
 322
 323                 clock-names = "oscclk", "aclk_g3d_400";
 324                 clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
 325         };
 326
 327         cmu_gscl: clock-controller@13cf0000 {
 328                 compatible = "samsung,exynos5433-cmu-gscl";
 329                 reg = <0x13cf0000 0x0b10>;
 330                 #clock-cells = <1>;
 331
 332                 clock-names = "oscclk",
 333                         "aclk_gscl_111",
 334                         "aclk_gscl_333";
 335                 clocks = <&xxti>,
 336                         <&cmu_top CLK_ACLK_GSCL_111>,
 337                         <&cmu_top CLK_ACLK_GSCL_333>;
 338         };
 339
 340         cmu_apollo: clock-controller@11900000 {
 341                 compatible = "samsung,exynos5433-cmu-apollo";
 342                 reg = <0x11900000 0x1088>;
 343                 #clock-cells = <1>;
 344
 345                 clock-names = "oscclk", "sclk_bus_pll_apollo";
 346                 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
 347         };
 348
 349         cmu_atlas: clock-controller@11800000 {
 350                 compatible = "samsung,exynos5433-cmu-atlas";
 351                 reg = <0x11800000 0x1088>;
 352                 #clock-cells = <1>;
 353
 354                 clock-names = "oscclk", "sclk_bus_pll_atlas";
 355                 clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
 356         };
 357
 358         cmu_mscl: clock-controller@105d0000 {
 359                 compatible = "samsung,exynos5433-cmu-mscl";
 360                 reg = <0x105d0000 0x0b10>;
 361                 #clock-cells = <1>;
 362
 363                 clock-names = "oscclk",
 364                         "sclk_jpeg_mscl",
 365                         "aclk_mscl_400";
 366                 clocks = <&xxti>,
 367                        <&cmu_top CLK_SCLK_JPEG_MSCL>,
 368                        <&cmu_top CLK_ACLK_MSCL_400>;
 369         };
 370
 371         cmu_mfc: clock-controller@15280000 {
 372                 compatible = "samsung,exynos5433-cmu-mfc";
 373                 reg = <0x15280000 0x0b08>;
 374                 #clock-cells = <1>;
 375
 376                 clock-names = "oscclk", "aclk_mfc_400";
 377                 clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
 378         };
 379
 380         cmu_hevc: clock-controller@14f80000 {
 381                 compatible = "samsung,exynos5433-cmu-hevc";
 382                 reg = <0x14f80000 0x0b08>;
 383                 #clock-cells = <1>;
 384
 385                 clock-names = "oscclk", "aclk_hevc_400";
 386                 clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
 387         };
 388
 389         cmu_isp: clock-controller@146d0000 {
 390                 compatible = "samsung,exynos5433-cmu-isp";
 391                 reg = <0x146d0000 0x0b0c>;
 392                 #clock-cells = <1>;
 393
 394                 clock-names = "oscclk",
 395                         "aclk_isp_dis_400",
 396                         "aclk_isp_400";
 397                 clocks = <&xxti>,
 398                        <&cmu_top CLK_ACLK_ISP_DIS_400>,
 399                        <&cmu_top CLK_ACLK_ISP_400>;
 400         };
 401
 402         cmu_cam0: clock-controller@120d0000 {
 403                 compatible = "samsung,exynos5433-cmu-cam0";
 404                 reg = <0x120d0000 0x0b0c>;
 405                 #clock-cells = <1>;
 406
 407                 clock-names = "oscclk",
 408                         "aclk_cam0_333",
 409                         "aclk_cam0_400",
 410                         "aclk_cam0_552";
 411                 clocks = <&xxti>,
 412                        <&cmu_top CLK_ACLK_CAM0_333>,
 413                        <&cmu_top CLK_ACLK_CAM0_400>,
 414                        <&cmu_top CLK_ACLK_CAM0_552>;
 415         };
 416
 417 Example 3: UART controller node that consumes the clock generated by the clock
 418            controller.
 419
 420         serial_0: serial@14C10000 {
 421                 compatible = "samsung,exynos5433-uart";
 422                 reg = <0x14C10000 0x100>;
 423                 interrupts = <0 421 0>;
 424                 clocks = <&cmu_peric CLK_PCLK_UART0>,
 425                          <&cmu_peric CLK_SCLK_UART0>;
 426                 clock-names = "uart", "clk_uart_baud0";
 427                 pinctrl-names = "default";
 428                 pinctrl-0 = <&uart0_bus>;
 429                 status = "disabled";
 430         };