1 * Rockchip rk3399 DMC(Dynamic Memory Controller) device
4 - compatible: Must be "rockchip,rk3399-dmc".
5 - devfreq-events: Node to get DDR loading, Refer to
6 Documentation/devicetree/bindings/devfreq/rockchip-dfi.txt
7 - interrupts: The interrupt number to the CPU. The interrupt specifier format
8 depends on the interrupt controller. It should be DCF interrupts,
9 when DDR dvfs finish, it will happen.
10 - clocks: Phandles for clock specified in "clock-names" property
11 - clock-names : The name of clock used by the DFI, must be "pclk_ddr_mon";
12 - operating-points-v2: Refer to Documentation/devicetree/bindings/power/opp.txt
14 - center-supply: DMC supply node.
15 - status: Marks the node enabled/disabled.
18 - ddr_timing: DDR timing need to pass to arm trust firmware
19 - upthreshold: The upthreshold to simpleondeamnd policy
20 - downdifferential: The downdifferential to simpleondeamnd policy
24 ddr_timing: ddr_timing {
25 compatible = "rockchip,ddr-timing";
26 ddr3_speed_bin = <21>;
29 sr_mc_gate_idle = <0>;
32 dram_dll_dis_freq = <300>;
33 phy_dll_dis_freq = <125>;
35 ddr3_odt_dis_freq = <333>;
36 ddr3_drv = <DDR3_DS_40ohm>;
37 ddr3_odt = <DDR3_ODT_120ohm>;
38 phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
39 phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
40 phy_ddr3_odt = <PHY_DRV_ODT_240>;
42 lpddr3_odt_dis_freq = <333>;
43 lpddr3_drv = <LP3_DS_34ohm>;
44 lpddr3_odt = <LP3_ODT_240ohm>;
45 phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;
46 phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;
47 phy_lpddr3_odt = <PHY_DRV_ODT_240>;
49 lpddr4_odt_dis_freq = <333>;
50 lpddr4_drv = <LP4_PDDS_60ohm>;
51 lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
52 lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
53 phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
54 phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
55 phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
56 phy_lpddr4_odt = <PHY_DRV_ODT_60>;
59 dmc_opp_table: dmc_opp_table {
60 compatible = "operating-points-v2";
63 opp-hz = /bits/ 64 <300000000>;
64 opp-microvolt = <900000>;
67 opp-hz = /bits/ 64 <666000000>;
68 opp-microvolt = <900000>;
73 compatible = "rockchip,rk3399-dmc";
74 devfreq-events = <&dfi>;
75 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
76 clocks = <&cru SCLK_DDRCLK>;
77 clock-names = "dmc_clk";
78 ddr_timing = <&ddr_timing>;
79 operating-points-v2 = <&dmc_opp_table>;
80 center-supply = <&ppvar_centerlogic>;
82 downdifferential = <10>;