1 Rockchip specific extensions to the Synopsys Designware HDMI
2 ================================
5 - compatible: "rockchip,rk3288-dw-hdmi",
6 "rockchip,rk3399-dw-hdmi";
7 - reg: Physical base address and length of the controller's registers.
8 - clocks: phandle to hdmi iahb and isfr clocks.
9 - clock-names: should be "iahb" "isfr"
10 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
11 - interrupts: HDMI interrupt number
12 - ports: contain a port node with endpoint definitions as defined in
13 Documentation/devicetree/bindings/media/video-interfaces.txt. For
14 vopb,set the reg = <0> and set the reg = <1> for vopl.
15 - reg-io-width: the width of the reg:1,4, the value should be 4 on
19 - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing
20 - clocks, clock-names: phandle to the HDMI CEC clock, name should be "cec",
21 phandle to the VPLL clock, name should be "vpll".
25 compatible = "rockchip,rk3288-dw-hdmi";
26 reg = <0xff980000 0x20000>;
28 ddc-i2c-bus = <&i2c5>;
29 rockchip,grf = <&grf>;
30 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
31 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
32 clock-names = "iahb", "isfr";
38 hdmi_in_vopb: endpoint@0 {
40 remote-endpoint = <&vopb_out_hdmi>;
42 hdmi_in_vopl: endpoint@1 {
44 remote-endpoint = <&vopl_out_hdmi>;