Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt

   1 Rockchip specific extensions to the Synopsys Designware MIPI DSI
   2 ================================
   3
   4 Required properties:
   5 - compatible: must be one of:
   6         "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi".
   7         "rockchip,rk3366-mipi-dsi", "snps,dw-mipi-dsi".
   8         "rockchip,rk3368-mipi-dsi", "snps,dw-mipi-dsi".
   9         "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi".
  10 - reg: Represent the physical address range of the controller.
  11 - interrupts: Represent the controller's interrupt to the CPU(s).
  12 - clocks, clock-names: Phandles to the controller's APB clock(pclk) as
  13   described in [1].
  14 - rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
  15 - #address-cells: Should be <1>.
  16 - #size-cells: Should be <0>.
  17 - ports: contain a port node with endpoint definitions as defined in [2].
  18   For vopb,set the reg = <0> and set the reg = <1> for vopl.
  19
  20 Optional properties
  21 - clocks, clock-names:
  22   phandle to the SNPS-PHY config clock, name should be "phy_cfg".
  23   phandle to the SNPS-PHY PLL reference clock, name should be "ref".
  24   phandle to the Non-SNPS PHY high speed clock, name should be "hs_clk".
  25 - phys: phandle to Non-SNPS PHY node
  26 - phy-names: the string "mipi_dphy" when is found in a node, along with "phys"
  27   attribute, provides phandle to MIPI PHY node
  28 - resets : phandle to the reset of MIPI DSI APB Clock.
  29 - reset-names : should be "apb".
  30 - rockchip,dual-channel: for dual-channel panel, if not, don't configure
  31 - rockchip,lane-rate: manually configure lane-rate, not necessary.
  32
  33 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
  34 [2] Documentation/devicetree/bindings/media/video-interfaces.txt
  35 [3] Documentation/devicetree/bindings/reset/reset.txt
  36
  37 Example:
  38
  39 For Rockchip RK3288:
  40
  41         dsi0: dsi@ff960000 {
  42                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
  43                 reg = <0x0 0xff960000 0x0 0x4000>;
  44                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
  45                 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
  46                 clock-names = "ref", "pclk";
  47                 rockchip,grf = <&grf>;
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50
  51                 rockchip,dual-channel = <&dsi1>;
  52                 rockchip,lane-rate = <900>;
  53
  54                 status = "okay";
  55
  56                 ports {
  57                         #address-cells = <1>;
  58                         #size-cells = <0>;
  59                         reg = <1>;
  60
  61                         dsi0_in: port {
  62                                 #address-cells = <1>;
  63                                 #size-cells = <0>;
  64
  65                                 dsi0_in_vopb: endpoint@0 {
  66                                         reg = <0>;
  67                                         remote-endpoint = <&vopb_out_dsi0>;
  68                                 };
  69                                 dsi0_in_vopl: endpoint@1 {
  70                                         reg = <1>;
  71                                         remote-endpoint = <&vopl_out_dsi0>;
  72                                 };
  73                         };
  74                 };
  75
  76                 panel {
  77                         compatible ="boe,tv080wum-nl0";
  78                         reg = <0>;
  79
  80                         enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
  81                         pinctrl-names = "default";
  82                         pinctrl-0 = <&lcd_en>;
  83                         backlight = <&backlight>;
  84                         status = "okay";
  85                 };
  86         };
  87
  88         dsi1: dsi@ff964000 {
  89                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
  90                 reg = <0x0 0xff964000 0x0 0x4000>;
  91                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
  92                 clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI1>;
  93                 clock-names = "ref", "pclk";
  94                 rockchip,grf = <&grf>;
  95                 #address-cells = <1>;
  96                 #size-cells = <0>;
  97                 status = "okay";
  98
  99                 ports {
 100                         #address-cells = <1>;
 101                         #size-cells = <0>;
 102                         reg = <1>;
 103
 104                         dsi1_in: port {
 105                                 #address-cells = <1>;
 106                                 #size-cells = <0>;
 107
 108                                 dsi1_in_vopb: endpoint@0 {
 109                                         reg = <0>;
 110                                         remote-endpoint = <&vopb_out_dsi1>;
 111                                 };
 112                                 dsi1_in_vopl: endpoint@1 {
 113                                         reg = <1>;
 114                                         remote-endpoint = <&vopl_out_dsi1>;
 115                                 };
 116                         };
 117                 };
 118         };
 119
 120 For Rockchip RK3368:
 121
 122         dsi: dsi@ff960000 {
 123                 compatible = "rockchip,rk3368-mipi-dsi";
 124                 clocks = <&cru PCLK_MIPI_DSI0>, <&mipi_dphy>;
 125                 clock-names = "pclk", "hs_clk";
 126                 phys = <&mipi_dphy>;
 127                 phy-names = "mipi_dphy";
 128                 resets = <&cru SRST_MIPIDSI0>;
 129                 reset-names = "apb";
 130                 ...
 131
 132                 ports {
 133                         port {
 134                                 dsi_in_vop: endpoint {
 135                                         remote-endpoint = <&vop_out_dsi>;
 136                                 };
 137                         };
 138                 };
 139         };