1 * ARM Generic Interrupt Controller
3 ARM SMP cores are often associated with a GIC, providing per processor
4 interrupts (PPI), shared processor interrupts (SPI) and software
5 generated interrupts (SGI).
7 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
8 Secondary GICs are cascaded into the upward interrupt controller and do not
11 Main node required properties:
13 - compatible : should be one of:
14 "arm,arm1176jzf-devchip-gic"
24 - interrupt-controller : Identifies the node as an interrupt controller
25 - #interrupt-cells : Specifies the number of cells needed to encode an
26 interrupt source. The type shall be a <u32> and the value shall be 3.
28 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
31 The 2nd cell contains the interrupt number for the interrupt type.
32 SPI interrupts are in the range [0-987]. PPI interrupts are in the
35 The 3rd cell is the flags, encoded as follows:
36 bits[3:0] trigger type and level flags.
37 1 = low-to-high edge triggered
38 2 = high-to-low edge triggered (invalid for SPIs)
39 4 = active high level-sensitive
40 8 = active low level-sensitive (invalid for SPIs).
41 bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
42 the 8 possible cpus attached to the GIC. A bit set to '1' indicated
43 the interrupt is wired to that CPU. Only valid for PPI interrupts.
44 Also note that the configurability of PPI interrupts is IMPLEMENTATION
45 DEFINED and as such not guaranteed to be present (most SoC available
46 in 2014 seem to ignore the setting of this flag and use the hardware
49 - reg : Specifies base physical address(s) and size of the GIC registers. The
50 first region is the GIC distributor register base and size. The 2nd region is
51 the GIC cpu interface register base and size.
54 - interrupts : Interrupt source of the parent interrupt controller on
55 secondary GICs, or VGIC maintenance interrupt on primary GIC (see
58 - cpu-offset : per-cpu offset within the distributor and cpu interface
59 regions, used when the GIC doesn't have banked registers. The offset is
62 - clocks : List of phandle and clock-specific pairs, one for each entry
64 - clock-names : List of names for the GIC clock input(s). Valid clock names
65 depend on the GIC variant:
66 "ic_clk" (for "arm,arm11mp-gic")
67 "PERIPHCLKEN" (for "arm,cortex-a15-gic")
68 "PERIPHCLK", "PERIPHCLKEN" (for "arm,cortex-a9-gic")
69 "clk" (for "arm,gic-400")
70 "gclk" (for "arm,pl390")
72 - power-domains : A phandle and PM domain specifier as defined by bindings of
73 the power controller specified by phandle, used when the GIC
74 is part of a Power or Clock Domain.
79 intc: interrupt-controller@fff11000 {
80 compatible = "arm,cortex-a9-gic";
81 #interrupt-cells = <3>;
84 reg = <0xfff11000 0x1000>,
89 * GIC virtualization extensions (VGIC)
91 For ARM cores that support the virtualization extensions, additional
92 properties must be described (they only exist if the GIC is the
93 primary interrupt controller).
97 - reg : Additional regions specifying the base physical address and
98 size of the VGIC registers. The first additional region is the GIC
99 virtual interface control register base and size. The 2nd additional
100 region is the GIC virtual cpu interface register base and size.
102 - interrupts : VGIC maintenance interrupt.
106 interrupt-controller@2c001000 {
107 compatible = "arm,cortex-a15-gic";
108 #interrupt-cells = <3>;
109 interrupt-controller;
110 reg = <0x2c001000 0x1000>,
114 interrupts = <1 9 0xf04>;
118 * GICv2m extension for MSI/MSI-x support (Optional)
120 Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
121 This is enabled by specifying v2m sub-node(s).
125 - compatible : The value here should contain "arm,gic-v2m-frame".
127 - msi-controller : Identifies the node as an MSI controller.
129 - reg : GICv2m MSI interface register base and size
133 - arm,msi-base-spi : When the MSI_TYPER register contains an incorrect
134 value, this property should contain the SPI base of
135 the MSI frame, overriding the HW value.
137 - arm,msi-num-spis : When the MSI_TYPER register contains an incorrect
138 value, this property should contain the number of
139 SPIs assigned to the frame, overriding the HW value.
143 interrupt-controller@e1101000 {
144 compatible = "arm,gic-400";
145 #interrupt-cells = <3>;
146 #address-cells = <2>;
148 interrupt-controller;
149 interrupts = <1 8 0xf04>;
150 ranges = <0 0 0 0xe1100000 0 0x100000>;
151 reg = <0x0 0xe1110000 0 0x01000>,
152 <0x0 0xe112f000 0 0x02000>,
153 <0x0 0xe1140000 0 0x10000>,
154 <0x0 0xe1160000 0 0x10000>;
156 compatible = "arm,gic-v2m-frame";
158 reg = <0x0 0x80000 0 0x1000>;
164 compatible = "arm,gic-v2m-frame";
166 reg = <0x0 0x90000 0 0x1000>;