1 Device tree bindings for MVEBU Device Bus controllers
3 The Device Bus controller available in some Marvell's SoC allows to control
4 different types of standard memory and I/O devices such as NOR, NAND, and FPGA.
5 The actual devices are instantiated from the child nodes of a Device Bus node.
9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
12 Orion5x SoC are supported using the
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
16 This is the base address of a chip select within
17 the controller's register space.
18 (see the example below)
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
24 0 <physical address of mapping> <size>
26 Timing properties for child nodes:
30 - devbus,turn-off-ps: Defines the time during which the controller does not
31 drive the AD bus after the completion of a device read.
32 This prevents contentions on the Device Bus after a read
33 cycle from a slow device.
36 - devbus,bus-width: Defines the bus width, in bits (e.g. <16>).
39 - devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
40 to read data sample. This parameter is useful for
41 synchronous pipelined devices, where the address
42 precedes the read data by one or two cycles.
45 - devbus,acc-first-ps: Defines the time delay from the negation of
46 ALE[0] to the cycle that the first read data is sampled
50 - devbus,acc-next-ps: Defines the time delay between the cycle that
51 samples data N and the cycle that samples data N+1
55 - devbus,rd-setup-ps: Defines the time delay between DEV_CSn assertion to
56 DEV_OEn assertion. If set to 0 (default),
57 DEV_OEn and DEV_CSn are asserted at the same cycle.
58 This parameter has no affect on <acc-first-ps> parameter
59 (no affect on first data sample). Set <rd-setup-ps>
60 to a value smaller than <acc-first-ps>.
61 Mandatory for "marvell,mvebu-devbus"
62 compatible string, ignored otherwise.
64 - devbus,rd-hold-ps: Defines the time between the last data sample to the
65 de-assertion of DEV_CSn. If set to 0 (default),
66 DEV_OEn and DEV_CSn are de-asserted at the same cycle
67 (the cycle of the last data sample).
68 This parameter has no affect on DEV_OEn de-assertion.
69 DEV_OEn is always de-asserted the next cycle after
70 last data sampled. Also this parameter has no
71 affect on <turn-off-ps> parameter.
72 Set <rd-hold-ps> to a value smaller than <turn-off-ps>.
73 Mandatory for "marvell,mvebu-devbus"
74 compatible string, ignored otherwise.
78 - devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
79 to the DEV_WEn assertion.
82 - devbus,wr-low-ps: Defines the time during which DEV_WEn is active.
83 A[2:0] and Data are kept valid as long as DEV_WEn
84 is active. This parameter defines the setup time of
85 address and data to DEV_WEn rise.
88 - devbus,wr-high-ps: Defines the time during which DEV_WEn is kept
89 inactive (high) between data beats of a burst write.
90 DEV_A[2:0] and Data are kept valid (do not toggle) for
91 <wr-high-ps> - <tick> ps.
92 This parameter defines the hold time of address and
93 data after DEV_WEn rise.
96 - devbus,sync-enable: Synchronous device enable.
99 Mandatory for "marvell,mvebu-devbus" compatible
100 string, ignored otherwise.
102 An example for an Armada XP GP board, with a 16 MiB NOR device as child
103 is showed below. Note that the Device Bus driver is in charge of allocating
104 the mbus address decoding window for each of its child devices.
105 The window is created using the chip select specified in the child
106 device node together with the base address and size specified in the ranges
107 property. For instance, in the example below the allocated decoding window
108 will start at base address 0xf0000000, with a size 0x1000000 (16 MiB)
109 for chip select 0 (a.k.a DEV_BOOTCS).
111 This address window handling is done in this mvebu-devbus only as a temporary
112 solution. It will be removed when the support for mbus device tree binding is
115 The reg property implicitly specifies the chip select as this:
125 devbus-bootcs@d0010400 {
127 ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf0000000, size 0x1000000 */
128 #address-cells = <1>;
131 /* Device Bus parameters are required */
133 /* Read parameters */
134 devbus,bus-width = <8>;
135 devbus,turn-off-ps = <60000>;
136 devbus,badr-skew-ps = <0>;
137 devbus,acc-first-ps = <124000>;
138 devbus,acc-next-ps = <248000>;
139 devbus,rd-setup-ps = <0>;
140 devbus,rd-hold-ps = <0>;
142 /* Write parameters */
143 devbus,sync-enable = <0>;
144 devbus,wr-high-ps = <60000>;
145 devbus,wr-low-ps = <60000>;
146 devbus,ale-wr-ps = <60000>;
149 compatible = "cfi-flash";
154 #address-cells = <1>;
158 * We split the 16 MiB in two partitions,
159 * just as an example.
168 reg = <0x800000 0x800000>;