1 Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC)
3 The device node has following properties.
6 - compatible: Can be one of "rockchip,rk3228-gmac", "rockchip,rk3288-gmac",
7 "rockchip,rk3366-gmac", "rockchip,rk3368-gmac",
9 - reg: addresses and length of the register sets for the device.
10 - interrupts: Should contain the GMAC interrupts.
11 - interrupt-names: Should contain the interrupt names "macirq".
12 - rockchip,grf: phandle to the syscon grf used to control speed and mode.
13 - clocks: <&cru SCLK_MAC>: clock selector for main clock, from PLL or PHY.
14 <&cru SCLK_MAC_PLL>: PLL clock for SCLK_MAC
15 <&cru SCLK_MAC_RX>: clock gate for RX
16 <&cru SCLK_MAC_TX>: clock gate for TX
17 <&cru SCLK_MACREF>: clock gate for RMII referce clock
18 <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output
19 <&cru ACLK_GMAC>: AXI clock gate for GMAC
20 <&cru PCLK_GMAC>: APB clock gate for GMAC
21 - clock-names: One name for each entry in the clocks property.
22 - phy-mode: See ethernet.txt file in the same directory.
23 - pinctrl-names: Names corresponding to the numbered pinctrl states.
24 - pinctrl-0: pin-control mode. can be <&rgmii_pins> or <&rmii_pins>.
25 - clock_in_out: For RGMII, it must be "input", means main clock(125MHz)
26 is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means
27 PHY provides the reference clock(50MHz), "output" means GMAC provides the
29 - snps,reset-gpio gpio number for phy reset.
30 - snps,reset-active-low boolean flag to indicate if phy reset is active low.
31 - assigned-clocks: main clock, should be <&cru SCLK_MAC>;
32 - assigned-clock-parents = parent of main clock.
33 can be <&ext_gmac> or <&cru SCLK_MAC_PLL>.
36 - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
37 - rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.
38 - phy-supply: phandle to a regulator if the PHY needs one
42 gmac: ethernet@ff290000 {
43 compatible = "rockchip,rk3288-gmac";
44 reg = <0xff290000 0x10000>;
45 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
46 interrupt-names = "macirq";
47 rockchip,grf = <&grf>;
48 clocks = <&cru SCLK_MAC>,
49 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
50 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
51 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
52 clock-names = "stmmaceth",
53 "mac_clk_rx", "mac_clk_tx",
54 "clk_mac_ref", "clk_mac_refout",
55 "aclk_mac", "pclk_mac";
57 pinctrl-names = "default";
58 pinctrl-0 = <&rgmii_pins /*&rmii_pins*/>;
60 clock_in_out = "input";
61 snps,reset-gpio = <&gpio4 7 0>;
62 snps,reset-active-low;
64 assigned-clocks = <&cru SCLK_MAC>;
65 assigned-clock-parents = <&ext_gmac>;