1 * Rockchip AXI PCIe Root Port Bridge DT description
4 - #address-cells: Address representation for root ports, set to <3>
5 - #size-cells: Size representation for root ports, set to <2>
6 - #interrupt-cells: specifies the number of cells needed to encode an
7 interrupt source. The value must be 1.
8 - compatible: Should contain "rockchip,rk3399-pcie"
9 - reg: Two register ranges as listed in the reg-names property
10 - reg-names: The first entry must be "axi-base" for the core registers
11 The second entry must be "apb-base" for the client pcie registers
12 - clocks: Must contain an entry for each entry in clock-names.
13 See ../clocks/clock-bindings.txt for details.
14 - clock-names: Must include the following entries:
19 - interrupts: Three interrupt entries must be specified.
20 - interrupt-names: Must include the following names
24 - resets: Must contain five entries for each entry in reset-names.
25 See ../reset/reset.txt for details.
26 - reset-names: Must include the following names
32 - rockchip,grf: phandle to the syscon managing the "general register files"
33 - pcie-conf: offset of pcie client block for configuration
34 - pcie-status: offset of pcie client block for status
35 - pcie-laneoff: offset of pcie client block for lane
36 - msi-parent: Link to the hardware entity that serves as the Message
37 - pinctrl-names : The pin control state names
38 - pinctrl-0: The "default" pinctrl state
39 - interrupt-map-mask and interrupt-map: standard PCI properties
40 - interrupt-controller: identifies the node as an interrupt controller
43 - ep-gpios: contain the entry for pre-reset gpio
44 - num-lanes: number of lanes to use
45 - assigned-clocks, assigned-clock-parents and assigned-clock-rates: standard
46 clock bindings. See ../clock/clock-bindings.txt
50 pci_express: axi-pcie@f8000000 {
53 compatible = "rockchip,rk3399-pcie";
54 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
55 <&cru PCLK_PCIE>, <&cru SCLK_PCIEPHY_REF>;
56 clock-names = "aclk_pcie", "aclk_perf_pcie",
57 "hclk_pcie", "clk_pciephy_ref";
58 bus-range = <0x0 0x1>;
59 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
61 interrupt-names: "pcie-sys", "pcie-legacy", "pcie-client";
62 assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
63 assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
64 assigned-clock-rates = <100000000>;
65 ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
66 ranges = < 0x82000000 0 0xfa000000 0x0 0xfa000000 0 0x600000
67 0x81000000 0 0xfa600000 0x0 0xfa600000 0 0x100000 >;
69 reg = < 0x0 0xf8000000 0x0 0x2000000 >, < 0x0 0xfd000000 0x0 0x1000000 >;
70 reg-name = "axi-base", "apb-base";
71 resets = <&cru SRST_PCIEPHY>, <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
72 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>;
73 reset-names = "phy-rst", "core-rst", "mgmt-rst", "mgmt-sticky-rst", "pipe-rst";
74 rockchip,grf = <&grf>;
76 pcie-status = <0xe2a4>;
77 pcie-laneoff = <0xe214>;
78 pinctrl-names = "default";
79 pinctrl-0 = <&pcie_clkreq>;
81 #interrupt-cells = <1>;
82 interrupt-map-mask = <0 0 0 7>;
83 interrupt-map = <0 0 0 1 &pcie_0 1>,
87 pcie_0: interrupt-controller {
90 #interrupt-cells = <1>;