Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt

   1 Rockchip specific extensions to the Analogix Display Port PHY
   2 ------------------------------------
   3
   4 Required properties:
   5 - compatible : should be one of the following supported values:
   6          - "rockchip.rk3288-dp-phy"
   7          - "rockchip.rk3368-dp-phy"
   8 - clocks: from common clock binding: handle to dp clock.
   9         of memory mapped region.
  10 - clock-names: from common clock binding:
  11         Required elements: "24m"
  12 - #phy-cells : from the generic PHY bindings, must be 0;
  13
  14 Optional properties
  15  - resets : phandle to the reset of eDP 24m clock domain.
  16  - reset-names : should be "edp_24m".
  17
  18 Example:
  19
  20 For Rockchip RK3288:
  21
  22 grf: syscon@ff770000 {
  23         compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
  24
  25 ...
  26
  27         edp_phy: edp-phy {
  28                 compatible = "rockchip,rk3288-dp-phy";
  29                 clocks = <&cru SCLK_EDP_24M>;
  30                 clock-names = "24m";
  31                 #phy-cells = <0>;
  32         };
  33 };
  34
  35 For Rockchip RK3368:
  36
  37 grf: syscon@ff770000 {
  38         compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
  39
  40 ...
  41
  42         edp_phy: edp-phy {
  43                 compatible = "rockchip,rk3368-dp-phy";
  44                 clocks = <&cru SCLK_EDP_24M>;
  45                 clock-names = "24m";
  46                 resets = <&cru SRST_EDP_24M>;
  47                 reset-names = "edp_24m";
  48                 #phy-cells = <0>;
  49         };
  50 };