Documentation/devicetree/bindings/usb/dwc3-rockchip.txt

   1 Rockchip SuperSpeed DWC3 USB SoC controller
   2
   3 Required properties:
   4 - compatible:   should contain "rockchip,dwc3"
   5 - clocks:               A list of phandle + clock-specifier pairs for the
   6                                 clocks listed in clock-names
   7 - clock-names:  Should contain the following:
   8   "clk_usb3otg0_ref"    Controller reference clk
   9   "clk_usb3otg0_suspend"Controller suspend clk, can use 24 MHz or 32 KHz
  10   "aclk_usb3"           Master/Core clock, have to be >= 62.5 MHz for SS operation
  11
  12
  13 Optional clocks:
  14   "aclk_usb3otg0"       Aclk for specific usb controller clock.
  15   "aclk_usb3_rksoc_axi_perf"  USB AXI perf clock.  Not present on all platforms.
  16   "aclk_usb3_noc"       USB noc clock. Not present on all platforms.
  17   "aclk_usb3_grf"       USB grf clock.  Not present on all platforms.
  18
  19 Required child node:
  20 A child node must exist to represent the core DWC3 IP block. The name of
  21 the node is not important. The content of the node is defined in dwc3.txt.
  22
  23 Phy documentation is provided in the following places:
  24
  25 Example device nodes:
  26
  27         usbdrd3_0: usb@fe800000 {
  28                 compatible = "rockchip,dwc3";
  29                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
  30                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
  31                          <&cru ACLK_USB3>, <&cru ACLK_USB3_NOC>,
  32                          <&cru ACLK_USB3_GRF>;
  33                 clock-names = "clk_usb3otg0_ref", "clk_usb3otg0_suspend",
  34                               "aclk_usb3otg0", "aclk_usb3_rksoc_axi_perf",
  35                               "aclk_usb3", "aclk_usb3_noc",
  36                               "aclk_usb3_grf";
  37                 #address-cells = <2>;
  38                 #size-cells = <2>;
  39                 ranges;
  40                 status = "disabled";
  41                 usbdrd_dwc3_0: dwc3 {
  42                         compatible = "snps,dwc3";
  43                         reg = <0x0 0xfe800000 0x0 0x100000>;
  44                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
  45                         dr_mode = "otg";
  46                         tx-fifo-resize;
  47                         status = "disabled";
  48                 };
  49         };
  50