1 PINCTRL (PIN CONTROL) subsystem
2 This document outlines the pin control subsystem in Linux
4 This subsystem deals with:
6 - Enumerating and naming controllable pins
8 - Multiplexing of pins, pads, fingers (etc) see below for details
10 - Configuration of pins, pads, fingers (etc), such as software-controlled
11 biasing and driving mode specific pins, such as pull-up/down, open drain,
17 Definition of PIN CONTROLLER:
19 - A pin controller is a piece of hardware, usually a set of registers, that
20 can control PINs. It may be able to multiplex, bias, set load capacitance,
21 set drive strength etc for individual pins or groups of pins.
25 - PINS are equal to pads, fingers, balls or whatever packaging input or
26 output line you want to control and these are denoted by unsigned integers
27 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
28 there may be several such number spaces in a system. This pin space may
29 be sparse - i.e. there may be gaps in the space with numbers where no
32 When a PIN CONTROLLER is instantiated, it will register a descriptor to the
33 pin control framework, and this descriptor contains an array of pin descriptors
34 describing the pins handled by this specific pin controller.
36 Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
56 To register a pin controller and name all the pins on this package we can do
59 #include <linux/pinctrl/pinctrl.h>
61 const struct pinctrl_pin_desc foo_pins[] = {
66 PINCTRL_PIN(61, "F1"),
67 PINCTRL_PIN(62, "G1"),
68 PINCTRL_PIN(63, "H1"),
71 static struct pinctrl_desc foo_desc = {
74 .npins = ARRAY_SIZE(foo_pins),
79 int __init foo_probe(void)
81 struct pinctrl_dev *pctl;
83 pctl = pinctrl_register(&foo_desc, <PARENT>, NULL);
85 pr_err("could not register foo pin driver\n");
88 To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and
89 selected drivers, you need to select them from your machine's Kconfig entry,
90 since these are so tightly integrated with the machines they are used on.
91 See for example arch/arm/mach-u300/Kconfig for an example.
93 Pins usually have fancier names than this. You can find these in the dataheet
94 for your chip. Notice that the core pinctrl.h file provides a fancy macro
95 called PINCTRL_PIN() to create the struct entries. As you can see I enumerated
96 the pins from 0 in the upper left corner to 63 in the lower right corner.
97 This enumeration was arbitrarily chosen, in practice you need to think
98 through your numbering system so that it matches the layout of registers
99 and such things in your driver, or the code may become complicated. You must
100 also consider matching of offsets to the GPIO ranges that may be handled by
103 For a padring with 467 pads, as opposed to actual pins, I used an enumeration
104 like this, walking around the edge of the chip, which seems to be industry
105 standard too (all these pads had names, too):
119 Many controllers need to deal with groups of pins, so the pin controller
120 subsystem has a mechanism for enumerating groups of pins and retrieving the
121 actual enumerated pins that are part of a certain group.
123 For example, say that we have a group of pins dealing with an SPI interface
124 on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins
127 These two groups are presented to the pin control subsystem by implementing
128 some generic pinctrl_ops like this:
130 #include <linux/pinctrl/pinctrl.h>
134 const unsigned int *pins;
135 const unsigned num_pins;
138 static const unsigned int spi0_pins[] = { 0, 8, 16, 24 };
139 static const unsigned int i2c0_pins[] = { 24, 25 };
141 static const struct foo_group foo_groups[] = {
145 .num_pins = ARRAY_SIZE(spi0_pins),
150 .num_pins = ARRAY_SIZE(i2c0_pins),
155 static int foo_get_groups_count(struct pinctrl_dev *pctldev)
157 return ARRAY_SIZE(foo_groups);
160 static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
163 return foo_groups[selector].name;
166 static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
167 unsigned ** const pins,
168 unsigned * const num_pins)
170 *pins = (unsigned *) foo_groups[selector].pins;
171 *num_pins = foo_groups[selector].num_pins;
175 static struct pinctrl_ops foo_pctrl_ops = {
176 .get_groups_count = foo_get_groups_count,
177 .get_group_name = foo_get_group_name,
178 .get_group_pins = foo_get_group_pins,
182 static struct pinctrl_desc foo_desc = {
184 .pctlops = &foo_pctrl_ops,
187 The pin control subsystem will call the .get_groups_count() function to
188 determine total number of legal selectors, then it will call the other functions
189 to retrieve the name and pins of the group. Maintaining the data structure of
190 the groups is up to the driver, this is just a simple example - in practice you
191 may need more entries in your group structure, for example specific register
192 ranges associated with each group and so on.
198 Pins can sometimes be software-configured in an various ways, mostly related
199 to their electronic properties when used as inputs or outputs. For example you
200 may be able to make an output pin high impedance, or "tristate" meaning it is
201 effectively disconnected. You may be able to connect an input pin to VDD or GND
202 using a certain resistor value - pull up and pull down - so that the pin has a
203 stable value when nothing is driving the rail it is connected to, or when it's
206 Pin configuration can be programmed by adding configuration entries into the
207 mapping table; see section "Board/machine configuration" below.
209 The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP
210 above, is entirely defined by the pin controller driver.
212 The pin configuration driver implements callbacks for changing pin
213 configuration in the pin controller ops like this:
215 #include <linux/pinctrl/pinctrl.h>
216 #include <linux/pinctrl/pinconf.h>
217 #include "platform_x_pindefs.h"
219 static int foo_pin_config_get(struct pinctrl_dev *pctldev,
221 unsigned long *config)
223 struct my_conftype conf;
225 ... Find setting for pin @ offset ...
227 *config = (unsigned long) conf;
230 static int foo_pin_config_set(struct pinctrl_dev *pctldev,
232 unsigned long config)
234 struct my_conftype *conf = (struct my_conftype *) config;
237 case PLATFORM_X_PULL_UP:
243 static int foo_pin_config_group_get (struct pinctrl_dev *pctldev,
245 unsigned long *config)
250 static int foo_pin_config_group_set (struct pinctrl_dev *pctldev,
252 unsigned long config)
257 static struct pinconf_ops foo_pconf_ops = {
258 .pin_config_get = foo_pin_config_get,
259 .pin_config_set = foo_pin_config_set,
260 .pin_config_group_get = foo_pin_config_group_get,
261 .pin_config_group_set = foo_pin_config_group_set,
264 /* Pin config operations are handled by some pin controller */
265 static struct pinctrl_desc foo_desc = {
267 .confops = &foo_pconf_ops,
270 Since some controllers have special logic for handling entire groups of pins
271 they can exploit the special whole-group pin control function. The
272 pin_config_group_set() callback is allowed to return the error code -EAGAIN,
273 for groups it does not want to handle, or if it just wants to do some
274 group-level handling and then fall through to iterate over all pins, in which
275 case each individual pin will be treated by separate pin_config_set() calls as
279 Interaction with the GPIO subsystem
280 ===================================
282 The GPIO drivers may want to perform operations of various types on the same
283 physical pins that are also registered as pin controller pins.
285 First and foremost, the two subsystems can be used as completely orthogonal,
286 see the section named "pin control requests from drivers" and
287 "drivers needing both pin control and GPIOs" below for details. But in some
288 situations a cross-subsystem mapping between pins and GPIOs is needed.
290 Since the pin controller subsystem have its pinspace local to the pin
291 controller we need a mapping so that the pin control subsystem can figure out
292 which pin controller handles control of a certain GPIO pin. Since a single
293 pin controller may be muxing several GPIO ranges (typically SoCs that have
294 one set of pins but internally several GPIO silicon blocks, each modeled as
295 a struct gpio_chip) any number of GPIO ranges can be added to a pin controller
298 struct gpio_chip chip_a;
299 struct gpio_chip chip_b;
301 static struct pinctrl_gpio_range gpio_range_a = {
310 static struct pinctrl_gpio_range gpio_range_b = {
320 struct pinctrl_dev *pctl;
322 pinctrl_add_gpio_range(pctl, &gpio_range_a);
323 pinctrl_add_gpio_range(pctl, &gpio_range_b);
326 So this complex system has one pin controller handling two different
327 GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and
328 "chip b" have different .pin_base, which means a start pin number of the
331 The GPIO range of "chip a" starts from the GPIO base of 32 and actual
332 pin range also starts from 32. However "chip b" has different starting
333 offset for the GPIO range and pin range. The GPIO range of "chip b" starts
334 from GPIO number 48, while the pin range of "chip b" starts from 64.
336 We can convert a gpio number to actual pin number using this "pin_base".
337 They are mapped in the global GPIO pin space at:
340 - GPIO range : [32 .. 47]
341 - pin range : [32 .. 47]
343 - GPIO range : [48 .. 55]
344 - pin range : [64 .. 71]
346 When GPIO-specific functions in the pin control subsystem are called, these
347 ranges will be used to look up the appropriate pin controller by inspecting
348 and matching the pin to the pin ranges across all controllers. When a
349 pin controller handling the matching range is found, GPIO-specific functions
350 will be called on that specific pin controller.
352 For all functionalities dealing with pin biasing, pin muxing etc, the pin
353 controller subsystem will subtract the range's .base offset from the passed
354 in gpio number, and add the ranges's .pin_base offset to retrive a pin number.
355 After that, the subsystem passes it on to the pin control driver, so the driver
356 will get an pin number into its handled number range. Further it is also passed
357 the range ID value, so that the pin controller knows which range it should
360 Calling pinctrl_add_gpio_range from pinctrl driver is DEPRECATED. Please see
361 section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind
362 pinctrl and gpio drivers.
367 These calls use the pinmux_* naming prefix. No other calls should use that
374 PINMUX, also known as padmux, ballmux, alternate functions or mission modes
375 is a way for chip vendors producing some kind of electrical packages to use
376 a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive
377 functions, depending on the application. By "application" in this context
378 we usually mean a way of soldering or wiring the package into an electronic
379 system, even though the framework makes it possible to also change the function
382 Here is an example of a PGA (Pin Grid Array) chip seen from underneath:
386 8 | o | o o o o o o o
388 7 | o | o o o o o o o
390 6 | o | o o o o o o o
392 5 | o | o | o o o o o o
394 4 o o o o o o | o | o
396 3 o o o o o o | o | o
398 2 o o o o o o | o | o
399 +-------+-------+-------+---+---+
400 1 | o o | o o | o o | o | o |
401 +-------+-------+-------+---+---+
403 This is not tetris. The game to think of is chess. Not all PGA/BGA packages
404 are chessboard-like, big ones have "holes" in some arrangement according to
405 different design patterns, but we're using this as a simple example. Of the
406 pins you see some will be taken by things like a few VCC and GND to feed power
407 to the chip, and quite a few will be taken by large ports like an external
408 memory interface. The remaining pins will often be subject to pin multiplexing.
410 The example 8x8 PGA package above will have pin numbers 0 thru 63 assigned to
411 its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using
412 pinctrl_register_pins() and a suitable data set as shown earlier.
414 In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port
415 (these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as
416 some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can
417 be used as an I2C port (these are just two pins: SCL, SDA). Needless to say,
418 we cannot use the SPI port and I2C port at the same time. However in the inside
419 of the package the silicon performing the SPI logic can alternatively be routed
420 out on pins { G4, G3, G2, G1 }.
422 On the botton row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something
423 special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will
424 consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or
425 { A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI
426 port on pins { G4, G3, G2, G1 } of course.
428 This way the silicon blocks present inside the chip can be multiplexed "muxed"
429 out on different pin ranges. Often contemporary SoC (systems on chip) will
430 contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to
431 different pins by pinmux settings.
433 Since general-purpose I/O pins (GPIO) are typically always in shortage, it is
434 common to be able to use almost any pin as a GPIO pin if it is not currently
435 in use by some other I/O port.
441 The purpose of the pinmux functionality in the pin controller subsystem is to
442 abstract and provide pinmux settings to the devices you choose to instantiate
443 in your machine configuration. It is inspired by the clk, GPIO and regulator
444 subsystems, so devices will request their mux setting, but it's also possible
445 to request a single pin for e.g. GPIO.
449 - FUNCTIONS can be switched in and out by a driver residing with the pin
450 control subsystem in the drivers/pinctrl/* directory of the kernel. The
451 pin control driver knows the possible functions. In the example above you can
452 identify three pinmux functions, one for spi, one for i2c and one for mmc.
454 - FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array.
455 In this case the array could be something like: { spi0, i2c0, mmc0 }
456 for the three available functions.
458 - FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain
459 function is *always* associated with a certain set of pin groups, could
460 be just a single one, but could also be many. In the example above the
461 function i2c is associated with the pins { A5, B5 }, enumerated as
462 { 24, 25 } in the controller pin space.
464 The Function spi is associated with pin groups { A8, A7, A6, A5 }
465 and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and
466 { 38, 46, 54, 62 } respectively.
468 Group names must be unique per pin controller, no two groups on the same
469 controller may have the same name.
471 - The combination of a FUNCTION and a PIN GROUP determine a certain function
472 for a certain set of pins. The knowledge of the functions and pin groups
473 and their machine-specific particulars are kept inside the pinmux driver,
474 from the outside only the enumerators are known, and the driver core can:
476 - Request the name of a function with a certain selector (>= 0)
477 - A list of groups associated with a certain function
478 - Request that a certain group in that list to be activated for a certain
481 As already described above, pin groups are in turn self-descriptive, so
482 the core will retrieve the actual pin range in a certain group from the
485 - FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain
486 device by the board file, device tree or similar machine setup configuration
487 mechanism, similar to how regulators are connected to devices, usually by
488 name. Defining a pin controller, function and group thus uniquely identify
489 the set of pins to be used by a certain device. (If only one possible group
490 of pins is available for the function, no group name need to be supplied -
491 the core will simply select the first and only group available.)
493 In the example case we can define that this particular machine shall
494 use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function
495 fi2c0 group gi2c0, on the primary pin controller, we get mappings
499 {"map-spi0", spi0, pinctrl0, fspi0, gspi0},
500 {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0}
503 Every map must be assigned a state name, pin controller, device and
504 function. The group is not compulsory - if it is omitted the first group
505 presented by the driver as applicable for the function will be selected,
506 which is useful for simple cases.
508 It is possible to map several groups to the same combination of device,
509 pin controller and function. This is for cases where a certain function on
510 a certain pin controller may use different sets of pins in different
513 - PINS for a certain FUNCTION using a certain PIN GROUP on a certain
514 PIN CONTROLLER are provided on a first-come first-serve basis, so if some
515 other device mux setting or GPIO pin request has already taken your physical
516 pin, you will be denied the use of it. To get (activate) a new setting, the
517 old one has to be put (deactivated) first.
519 Sometimes the documentation and hardware registers will be oriented around
520 pads (or "fingers") rather than pins - these are the soldering surfaces on the
521 silicon inside the package, and may or may not match the actual number of
522 pins/balls underneath the capsule. Pick some enumeration that makes sense to
523 you. Define enumerators only for the pins you can control if that makes sense.
527 We assume that the number of possible function maps to pin groups is limited by
528 the hardware. I.e. we assume that there is no system where any function can be
529 mapped to any pin, like in a phone exchange. So the available pins groups for
530 a certain function will be limited to a few choices (say up to eight or so),
531 not hundreds or any amount of choices. This is the characteristic we have found
532 by inspecting available pinmux hardware, and a necessary assumption since we
533 expect pinmux drivers to present *all* possible function vs pin group mappings
540 The pinmux core takes care of preventing conflicts on pins and calling
541 the pin controller driver to execute different settings.
543 It is the responsibility of the pinmux driver to impose further restrictions
544 (say for example infer electronic limitations due to load etc) to determine
545 whether or not the requested function can actually be allowed, and in case it
546 is possible to perform the requested mux setting, poke the hardware so that
549 Pinmux drivers are required to supply a few callback functions, some are
550 optional. Usually the enable() and disable() functions are implemented,
551 writing values into some certain registers to activate a certain mux setting
554 A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4
555 into some register named MUX to select a certain function with a certain
556 group of pins would work something like this:
558 #include <linux/pinctrl/pinctrl.h>
559 #include <linux/pinctrl/pinmux.h>
563 const unsigned int *pins;
564 const unsigned num_pins;
567 static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 };
568 static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 };
569 static const unsigned i2c0_pins[] = { 24, 25 };
570 static const unsigned mmc0_1_pins[] = { 56, 57 };
571 static const unsigned mmc0_2_pins[] = { 58, 59 };
572 static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 };
574 static const struct foo_group foo_groups[] = {
576 .name = "spi0_0_grp",
578 .num_pins = ARRAY_SIZE(spi0_0_pins),
581 .name = "spi0_1_grp",
583 .num_pins = ARRAY_SIZE(spi0_1_pins),
588 .num_pins = ARRAY_SIZE(i2c0_pins),
591 .name = "mmc0_1_grp",
593 .num_pins = ARRAY_SIZE(mmc0_1_pins),
596 .name = "mmc0_2_grp",
598 .num_pins = ARRAY_SIZE(mmc0_2_pins),
601 .name = "mmc0_3_grp",
603 .num_pins = ARRAY_SIZE(mmc0_3_pins),
608 static int foo_get_groups_count(struct pinctrl_dev *pctldev)
610 return ARRAY_SIZE(foo_groups);
613 static const char *foo_get_group_name(struct pinctrl_dev *pctldev,
616 return foo_groups[selector].name;
619 static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
620 unsigned ** const pins,
621 unsigned * const num_pins)
623 *pins = (unsigned *) foo_groups[selector].pins;
624 *num_pins = foo_groups[selector].num_pins;
628 static struct pinctrl_ops foo_pctrl_ops = {
629 .get_groups_count = foo_get_groups_count,
630 .get_group_name = foo_get_group_name,
631 .get_group_pins = foo_get_group_pins,
634 struct foo_pmx_func {
636 const char * const *groups;
637 const unsigned num_groups;
640 static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" };
641 static const char * const i2c0_groups[] = { "i2c0_grp" };
642 static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp",
645 static const struct foo_pmx_func foo_functions[] = {
648 .groups = spi0_groups,
649 .num_groups = ARRAY_SIZE(spi0_groups),
653 .groups = i2c0_groups,
654 .num_groups = ARRAY_SIZE(i2c0_groups),
658 .groups = mmc0_groups,
659 .num_groups = ARRAY_SIZE(mmc0_groups),
663 int foo_get_functions_count(struct pinctrl_dev *pctldev)
665 return ARRAY_SIZE(foo_functions);
668 const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector)
670 return foo_functions[selector].name;
673 static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
674 const char * const **groups,
675 unsigned * const num_groups)
677 *groups = foo_functions[selector].groups;
678 *num_groups = foo_functions[selector].num_groups;
682 int foo_enable(struct pinctrl_dev *pctldev, unsigned selector,
685 u8 regbit = (1 << selector + group);
687 writeb((readb(MUX)|regbit), MUX)
691 void foo_disable(struct pinctrl_dev *pctldev, unsigned selector,
694 u8 regbit = (1 << selector + group);
696 writeb((readb(MUX) & ~(regbit)), MUX)
700 struct pinmux_ops foo_pmxops = {
701 .get_functions_count = foo_get_functions_count,
702 .get_function_name = foo_get_fname,
703 .get_function_groups = foo_get_groups,
704 .enable = foo_enable,
705 .disable = foo_disable,
708 /* Pinmux operations are handled by some pin controller */
709 static struct pinctrl_desc foo_desc = {
711 .pctlops = &foo_pctrl_ops,
712 .pmxops = &foo_pmxops,
715 In the example activating muxing 0 and 1 at the same time setting bits
716 0 and 1, uses one pin in common so they would collide.
718 The beauty of the pinmux subsystem is that since it keeps track of all
719 pins and who is using them, it will already have denied an impossible
720 request like that, so the driver does not need to worry about such
721 things - when it gets a selector passed in, the pinmux subsystem makes
722 sure no other device or GPIO assignment is already using the selected
723 pins. Thus bits 0 and 1 in the control register will never be set at the
726 All the above functions are mandatory to implement for a pinmux driver.
729 Pin control interaction with the GPIO subsystem
730 ===============================================
732 Note that the following implies that the use case is to use a certain pin
733 from the Linux kernel using the API in <linux/gpio.h> with gpio_request()
734 and similar functions. There are cases where you may be using something
735 that your datasheet calls "GPIO mode" but actually is just an electrical
736 configuration for a certain device. See the section below named
737 "GPIO mode pitfalls" for more details on this scenario.
739 The public pinmux API contains two functions named pinctrl_request_gpio()
740 and pinctrl_free_gpio(). These two functions shall *ONLY* be called from
741 gpiolib-based drivers as part of their gpio_request() and
742 gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output]
743 shall only be called from within respective gpio_direction_[input|output]
744 gpiolib implementation.
746 NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be
747 controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have
748 that driver request proper muxing and other control for its pins.
750 The function list could become long, especially if you can convert every
751 individual pin into a GPIO pin independent of any other pins, and then try
752 the approach to define every pin as a function.
754 In this case, the function array would become 64 entries for each GPIO
755 setting and then the device functions.
757 For this reason there are two functions a pin control driver can implement
758 to enable only GPIO on an individual pin: .gpio_request_enable() and
759 .gpio_disable_free().
761 This function will pass in the affected GPIO range identified by the pin
762 controller core, so you know which GPIO pins are being affected by the request
765 If your driver needs to have an indication from the framework of whether the
766 GPIO pin shall be used for input or output you can implement the
767 .gpio_set_direction() function. As described this shall be called from the
768 gpiolib driver and the affected GPIO range, pin offset and desired direction
769 will be passed along to this function.
771 Alternatively to using these special functions, it is fully allowed to use
772 named functions for each GPIO pin, the pinctrl_request_gpio() will attempt to
773 obtain the function "gpioN" where "N" is the global GPIO pin number if no
774 special GPIO-handler is registered.
780 Sometime the developer may be confused by a datasheet talking about a pin
781 being possible to set into "GPIO mode". It appears that what hardware
782 engineers mean with "GPIO mode" is not necessarily the use case that is
783 implied in the kernel interface <linux/gpio.h>: a pin that you grab from
784 kernel code and then either listen for input or drive high/low to
785 assert/deassert some external line.
787 Rather hardware engineers think that "GPIO mode" means that you can
788 software-control a few electrical properties of the pin that you would
789 not be able to control if the pin was in some other mode, such as muxed in
792 Example: a pin is usually muxed in to be used as a UART TX line. But during
793 system sleep, we need to put this pin into "GPIO mode" and ground it.
795 If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start
796 to think that you need to come up with something real complex, that the
797 pin shall be used for UART TX and GPIO at the same time, that you will grab
798 a pin control handle and set it to a certain state to enable UART TX to be
799 muxed in, then twist it over to GPIO mode and use gpio_direction_output()
800 to drive it low during sleep, then mux it over to UART TX again when you
801 wake up and maybe even gpio_request/gpio_free as part of this cycle. This
802 all gets very complicated.
804 The solution is to not think that what the datasheet calls "GPIO mode"
805 has to be handled by the <linux/gpio.h> interface. Instead view this as
806 a certain pin config setting. Look in e.g. <linux/pinctrl/pinconf-generic.h>
807 and you find this in the documentation:
809 PIN_CONFIG_OUTPUT: this will configure the pin in output, use argument
810 1 to indicate high level, argument 0 to indicate low level.
812 So it is perfectly possible to push a pin into "GPIO mode" and drive the
813 line low as part of the usual pin control map. So for example your UART
814 driver may look like this:
816 #include <linux/pinctrl/consumer.h>
818 struct pinctrl *pinctrl;
819 struct pinctrl_state *pins_default;
820 struct pinctrl_state *pins_sleep;
822 pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT);
823 pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP);
826 retval = pinctrl_select_state(pinctrl, pins_default);
828 retval = pinctrl_select_state(pinctrl, pins_sleep);
830 And your machine configuration may look like this:
831 --------------------------------------------------
833 static unsigned long uart_default_mode[] = {
834 PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0),
837 static unsigned long uart_sleep_mode[] = {
838 PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0),
841 static struct pinctrl_map __initdata pinmap[] = {
842 PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
844 PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo",
845 "UART_TX_PIN", uart_default_mode),
846 PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
847 "u0_group", "gpio-mode"),
848 PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo",
849 "UART_TX_PIN", uart_sleep_mode),
853 pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap));
856 Here the pins we want to control are in the "u0_group" and there is some
857 function called "u0" that can be enabled on this group of pins, and then
858 everything is UART business as usual. But there is also some function
859 named "gpio-mode" that can be mapped onto the same pins to move them into
862 This will give the desired effect without any bogus interaction with the
863 GPIO subsystem. It is just an electrical configuration used by that device
864 when going to sleep, it might imply that the pin is set into something the
865 datasheet calls "GPIO mode" but that is not the point: it is still used
866 by that UART device to control the pins that pertain to that very UART
867 driver, putting them into modes needed by the UART. GPIO in the Linux
868 kernel sense are just some 1-bit line, and is a different use case.
870 How the registers are poked to attain the push/pull and output low
871 configuration and the muxing of the "u0" or "gpio-mode" group onto these
872 pins is a question for the driver.
874 Some datasheets will be more helpful and refer to the "GPIO mode" as
875 "low power mode" rather than anything to do with GPIO. This often means
876 the same thing electrically speaking, but in this latter case the
877 software engineers will usually quickly identify that this is some
878 specific muxing/configuration rather than anything related to the GPIO
882 Board/machine configuration
883 ==================================
885 Boards and machines define how a certain complete running system is put
886 together, including how GPIOs and devices are muxed, how regulators are
887 constrained and how the clock tree looks. Of course pinmux settings are also
890 A pin controller configuration for a machine looks pretty much like a simple
891 regulator configuration, so for the example array above we want to enable i2c
892 and spi on the second function mapping:
894 #include <linux/pinctrl/machine.h>
896 static const struct pinctrl_map mapping[] __initconst = {
898 .dev_name = "foo-spi.0",
899 .name = PINCTRL_STATE_DEFAULT,
900 .type = PIN_MAP_TYPE_MUX_GROUP,
901 .ctrl_dev_name = "pinctrl-foo",
902 .data.mux.function = "spi0",
905 .dev_name = "foo-i2c.0",
906 .name = PINCTRL_STATE_DEFAULT,
907 .type = PIN_MAP_TYPE_MUX_GROUP,
908 .ctrl_dev_name = "pinctrl-foo",
909 .data.mux.function = "i2c0",
912 .dev_name = "foo-mmc.0",
913 .name = PINCTRL_STATE_DEFAULT,
914 .type = PIN_MAP_TYPE_MUX_GROUP,
915 .ctrl_dev_name = "pinctrl-foo",
916 .data.mux.function = "mmc0",
920 The dev_name here matches to the unique device name that can be used to look
921 up the device struct (just like with clockdev or regulators). The function name
922 must match a function provided by the pinmux driver handling this pin range.
924 As you can see we may have several pin controllers on the system and thus
925 we need to specify which one of them that contain the functions we wish
928 You register this pinmux mapping to the pinmux subsystem by simply:
930 ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping));
932 Since the above construct is pretty common there is a helper macro to make
933 it even more compact which assumes you want to use pinctrl-foo and position
934 0 for mapping, for example:
936 static struct pinctrl_map __initdata mapping[] = {
937 PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, "pinctrl-foo", NULL, "i2c0"),
940 The mapping table may also contain pin configuration entries. It's common for
941 each pin/group to have a number of configuration entries that affect it, so
942 the table entries for configuration reference an array of config parameters
943 and values. An example using the convenience macros is shown below:
945 static unsigned long i2c_grp_configs[] = {
950 static unsigned long i2c_pin_configs[] = {
955 static struct pinctrl_map __initdata mapping[] = {
956 PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"),
957 PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs),
958 PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs),
959 PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs),
962 Finally, some devices expect the mapping table to contain certain specific
963 named states. When running on hardware that doesn't need any pin controller
964 configuration, the mapping table must still contain those named states, in
965 order to explicitly indicate that the states were provided and intended to
966 be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining
967 a named state without causing any pin controller to be programmed:
969 static struct pinctrl_map __initdata mapping[] = {
970 PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT),
977 As it is possible to map a function to different groups of pins an optional
978 .group can be specified like this:
982 .dev_name = "foo-spi.0",
983 .name = "spi0-pos-A",
984 .type = PIN_MAP_TYPE_MUX_GROUP,
985 .ctrl_dev_name = "pinctrl-foo",
987 .group = "spi0_0_grp",
990 .dev_name = "foo-spi.0",
991 .name = "spi0-pos-B",
992 .type = PIN_MAP_TYPE_MUX_GROUP,
993 .ctrl_dev_name = "pinctrl-foo",
995 .group = "spi0_1_grp",
999 This example mapping is used to switch between two positions for spi0 at
1000 runtime, as described further below under the heading "Runtime pinmuxing".
1002 Further it is possible for one named state to affect the muxing of several
1003 groups of pins, say for example in the mmc0 example above, where you can
1004 additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all
1005 three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the
1006 case), we define a mapping like this:
1010 .dev_name = "foo-mmc.0",
1012 .type = PIN_MAP_TYPE_MUX_GROUP,
1013 .ctrl_dev_name = "pinctrl-foo",
1015 .group = "mmc0_1_grp",
1018 .dev_name = "foo-mmc.0",
1020 .type = PIN_MAP_TYPE_MUX_GROUP,
1021 .ctrl_dev_name = "pinctrl-foo",
1023 .group = "mmc0_1_grp",
1026 .dev_name = "foo-mmc.0",
1028 .type = PIN_MAP_TYPE_MUX_GROUP,
1029 .ctrl_dev_name = "pinctrl-foo",
1031 .group = "mmc0_2_grp",
1034 .dev_name = "foo-mmc.0",
1036 .type = PIN_MAP_TYPE_MUX_GROUP,
1037 .ctrl_dev_name = "pinctrl-foo",
1039 .group = "mmc0_1_grp",
1042 .dev_name = "foo-mmc.0",
1044 .type = PIN_MAP_TYPE_MUX_GROUP,
1045 .ctrl_dev_name = "pinctrl-foo",
1047 .group = "mmc0_2_grp",
1050 .dev_name = "foo-mmc.0",
1052 .type = PIN_MAP_TYPE_MUX_GROUP,
1053 .ctrl_dev_name = "pinctrl-foo",
1055 .group = "mmc0_3_grp",
1059 The result of grabbing this mapping from the device with something like
1060 this (see next paragraph):
1062 p = devm_pinctrl_get(dev);
1063 s = pinctrl_lookup_state(p, "8bit");
1064 ret = pinctrl_select_state(p, s);
1068 p = devm_pinctrl_get_select(dev, "8bit");
1070 Will be that you activate all the three bottom records in the mapping at
1071 once. Since they share the same name, pin controller device, function and
1072 device, and since we allow multiple groups to match to a single device, they
1073 all get selected, and they all get enabled and disable simultaneously by the
1077 Pin control requests from drivers
1078 =================================
1080 When a device driver is about to probe the device core will automatically
1081 attempt to issue pinctrl_get_select_default() on these devices.
1082 This way driver writers do not need to add any of the boilerplate code
1083 of the type found below. However when doing fine-grained state selection
1084 and not using the "default" state, you may have to do some device driver
1085 handling of the pinctrl handles and states.
1087 So if you just want to put the pins for a certain device into the default
1088 state and be done with it, there is nothing you need to do besides
1089 providing the proper mapping table. The device core will take care of
1092 Generally it is discouraged to let individual drivers get and enable pin
1093 control. So if possible, handle the pin control in platform code or some other
1094 place where you have access to all the affected struct device * pointers. In
1095 some cases where a driver needs to e.g. switch between different mux mappings
1096 at runtime this is not possible.
1098 A typical case is if a driver needs to switch bias of pins from normal
1099 operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to
1100 PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save
1101 current in sleep mode.
1103 A driver may request a certain control state to be activated, usually just the
1104 default state like this:
1106 #include <linux/pinctrl/consumer.h>
1110 struct pinctrl_state *s;
1116 /* Allocate a state holder named "foo" etc */
1117 struct foo_state *foo = ...;
1119 foo->p = devm_pinctrl_get(&device);
1120 if (IS_ERR(foo->p)) {
1121 /* FIXME: clean up "foo" here */
1122 return PTR_ERR(foo->p);
1125 foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT);
1126 if (IS_ERR(foo->s)) {
1127 /* FIXME: clean up "foo" here */
1131 ret = pinctrl_select_state(foo->s);
1133 /* FIXME: clean up "foo" here */
1138 This get/lookup/select/put sequence can just as well be handled by bus drivers
1139 if you don't want each and every driver to handle it and you know the
1140 arrangement on your bus.
1142 The semantics of the pinctrl APIs are:
1144 - pinctrl_get() is called in process context to obtain a handle to all pinctrl
1145 information for a given client device. It will allocate a struct from the
1146 kernel memory to hold the pinmux state. All mapping table parsing or similar
1147 slow operations take place within this API.
1149 - devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put()
1150 to be called automatically on the retrieved pointer when the associated
1151 device is removed. It is recommended to use this function over plain
1154 - pinctrl_lookup_state() is called in process context to obtain a handle to a
1155 specific state for a the client device. This operation may be slow too.
1157 - pinctrl_select_state() programs pin controller hardware according to the
1158 definition of the state as given by the mapping table. In theory this is a
1159 fast-path operation, since it only involved blasting some register settings
1160 into hardware. However, note that some pin controllers may have their
1161 registers on a slow/IRQ-based bus, so client devices should not assume they
1162 can call pinctrl_select_state() from non-blocking contexts.
1164 - pinctrl_put() frees all information associated with a pinctrl handle.
1166 - devm_pinctrl_put() is a variant of pinctrl_put() that may be used to
1167 explicitly destroy a pinctrl object returned by devm_pinctrl_get().
1168 However, use of this function will be rare, due to the automatic cleanup
1169 that will occur even without calling it.
1171 pinctrl_get() must be paired with a plain pinctrl_put().
1172 pinctrl_get() may not be paired with devm_pinctrl_put().
1173 devm_pinctrl_get() can optionally be paired with devm_pinctrl_put().
1174 devm_pinctrl_get() may not be paired with plain pinctrl_put().
1176 Usually the pin control core handled the get/put pair and call out to the
1177 device drivers bookkeeping operations, like checking available functions and
1178 the associated pins, whereas the enable/disable pass on to the pin controller
1179 driver which takes care of activating and/or deactivating the mux setting by
1180 quickly poking some registers.
1182 The pins are allocated for your device when you issue the devm_pinctrl_get()
1183 call, after this you should be able to see this in the debugfs listing of all
1186 NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the
1187 requested pinctrl handles, for example if the pinctrl driver has not yet
1188 registered. Thus make sure that the error path in your driver gracefully
1189 cleans up and is ready to retry the probing later in the startup process.
1192 Drivers needing both pin control and GPIOs
1193 ==========================================
1195 Again, it is discouraged to let drivers lookup and select pin control states
1196 themselves, but again sometimes this is unavoidable.
1198 So say that your driver is fetching its resources like this:
1200 #include <linux/pinctrl/consumer.h>
1201 #include <linux/gpio.h>
1203 struct pinctrl *pinctrl;
1206 pinctrl = devm_pinctrl_get_select_default(&dev);
1207 gpio = devm_gpio_request(&dev, 14, "foo");
1209 Here we first request a certain pin state and then request GPIO 14 to be
1210 used. If you're using the subsystems orthogonally like this, you should
1211 nominally always get your pinctrl handle and select the desired pinctrl
1212 state BEFORE requesting the GPIO. This is a semantic convention to avoid
1213 situations that can be electrically unpleasant, you will certainly want to
1214 mux in and bias pins in a certain way before the GPIO subsystems starts to
1217 The above can be hidden: using the device core, the pinctrl core may be
1218 setting up the config and muxing for the pins right before the device is
1219 probing, nevertheless orthogonal to the GPIO subsystem.
1221 But there are also situations where it makes sense for the GPIO subsystem
1222 to communicate directly with with the pinctrl subsystem, using the latter
1223 as a back-end. This is when the GPIO driver may call out to the functions
1224 described in the section "Pin control interaction with the GPIO subsystem"
1225 above. This only involves per-pin multiplexing, and will be completely
1226 hidden behind the gpio_*() function namespace. In this case, the driver
1227 need not interact with the pin control subsystem at all.
1229 If a pin control driver and a GPIO driver is dealing with the same pins
1230 and the use cases involve multiplexing, you MUST implement the pin controller
1231 as a back-end for the GPIO driver like this, unless your hardware design
1232 is such that the GPIO controller can override the pin controller's
1233 multiplexing state through hardware without the need to interact with the
1237 System pin control hogging
1238 ==========================
1240 Pin control map entries can be hogged by the core when the pin controller
1241 is registered. This means that the core will attempt to call pinctrl_get(),
1242 lookup_state() and select_state() on it immediately after the pin control
1243 device has been registered.
1245 This occurs for mapping table entries where the client device name is equal
1246 to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT.
1249 .dev_name = "pinctrl-foo",
1250 .name = PINCTRL_STATE_DEFAULT,
1251 .type = PIN_MAP_TYPE_MUX_GROUP,
1252 .ctrl_dev_name = "pinctrl-foo",
1253 .function = "power_func",
1256 Since it may be common to request the core to hog a few always-applicable
1257 mux settings on the primary pin controller, there is a convenience macro for
1260 PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func")
1262 This gives the exact same result as the above construction.
1268 It is possible to mux a certain function in and out at runtime, say to move
1269 an SPI port from one set of pins to another set of pins. Say for example for
1270 spi0 in the example above, we expose two different groups of pins for the same
1271 function, but with different named in the mapping as described under
1272 "Advanced mapping" above. So that for an SPI device, we have two states named
1273 "pos-A" and "pos-B".
1275 This snippet first muxes the function in the pins defined by group A, enables
1276 it, disables and releases it, and muxes it in on the pins defined by group B:
1278 #include <linux/pinctrl/consumer.h>
1281 struct pinctrl_state *s1, *s2;
1286 p = devm_pinctrl_get(&device);
1290 s1 = pinctrl_lookup_state(foo->p, "pos-A");
1294 s2 = pinctrl_lookup_state(foo->p, "pos-B");
1301 /* Enable on position A */
1302 ret = pinctrl_select_state(s1);
1308 /* Enable on position B */
1309 ret = pinctrl_select_state(s2);
1316 The above has to be done from process context. The reservation of the pins
1317 will be done when the state is activated, so in effect one specific pin
1318 can be used by different functions at different times on a running system.