1 //=- HexagonInstrInfoV3.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Hexagon V3 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 def callv3 : SDNode<"HexagonISD::CALLv3", SDT_SPCall,
15 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
17 def callv3nr : SDNode<"HexagonISD::CALLv3nr", SDT_SPCall,
18 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>;
20 //===----------------------------------------------------------------------===//
22 //===----------------------------------------------------------------------===//
24 let isCall = 1, neverHasSideEffects = 1,
25 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31,
26 P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
27 def CALLv3 : JInst<(outs), (ins calltarget:$dst),
28 "call $dst", []>, Requires<[HasV3T]>;
31 //===----------------------------------------------------------------------===//
33 //===----------------------------------------------------------------------===//
36 //===----------------------------------------------------------------------===//
38 //===----------------------------------------------------------------------===//
39 // Call subroutine from register.
40 let isCall = 1, neverHasSideEffects = 1,
41 Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31,
42 P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
43 def CALLRv3 : JRInst<(outs), (ins IntRegs:$dst),
45 []>, Requires<[HasV3TOnly]>;
48 //===----------------------------------------------------------------------===//
50 //===----------------------------------------------------------------------===//
52 //===----------------------------------------------------------------------===//
54 //===----------------------------------------------------------------------===//
56 let AddedComplexity = 200 in
57 def MAXw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
59 "$dst = max($src2, $src1)",
60 [(set (i64 DoubleRegs:$dst),
61 (i64 (select (i1 (setlt (i64 DoubleRegs:$src2),
62 (i64 DoubleRegs:$src1))),
63 (i64 DoubleRegs:$src1),
64 (i64 DoubleRegs:$src2))))]>,
67 let AddedComplexity = 200 in
68 def MINw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
70 "$dst = min($src2, $src1)",
71 [(set (i64 DoubleRegs:$dst),
72 (i64 (select (i1 (setgt (i64 DoubleRegs:$src2),
73 (i64 DoubleRegs:$src1))),
74 (i64 DoubleRegs:$src1),
75 (i64 DoubleRegs:$src2))))]>,
78 //===----------------------------------------------------------------------===//
80 //===----------------------------------------------------------------------===//
85 //def : Pat <(brcond (i1 (seteq (i32 IntRegs:$src1), 0)), bb:$offset),
86 // (JMP_RegEzt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
88 //def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), 0)), bb:$offset),
89 // (JMP_RegNzt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
91 //def : Pat <(brcond (i1 (setle (i32 IntRegs:$src1), 0)), bb:$offset),
92 // (JMP_RegLezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
94 //def : Pat <(brcond (i1 (setge (i32 IntRegs:$src1), 0)), bb:$offset),
95 // (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
97 //def : Pat <(brcond (i1 (setgt (i32 IntRegs:$src1), -1)), bb:$offset),
98 // (JMP_RegGezt (i32 IntRegs:$src1), bb:$offset)>, Requires<[HasV3T]>;
101 // Map call instruction
102 def : Pat<(call (i32 IntRegs:$dst)),
103 (CALLRv3 (i32 IntRegs:$dst))>, Requires<[HasV3T]>;
104 def : Pat<(call tglobaladdr:$dst),
105 (CALLv3 tglobaladdr:$dst)>, Requires<[HasV3T]>;
106 def : Pat<(call texternalsym:$dst),
107 (CALLv3 texternalsym:$dst)>, Requires<[HasV3T]>;