1 //===-- HexagonPeephole.cpp - Hexagon Peephole Optimiztions ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 // This peephole pass optimizes in the following cases.
9 // 1. Optimizes redundant sign extends for the following case
10 // Transform the following pattern
11 // %vreg170<def> = SXTW %vreg166
13 // %vreg176<def> = COPY %vreg170:subreg_loreg
16 // %vreg176<def> = COPY vreg166
18 // 2. Optimizes redundant negation of predicates.
19 // %vreg15<def> = CMPGTrr %vreg6, %vreg2
21 // %vreg16<def> = NOT_p %vreg15<kill>
23 // JMP_c %vreg16<kill>, <BB#1>, %PC<imp-def,dead>
26 // %vreg15<def> = CMPGTrr %vreg6, %vreg2;
28 // JMP_cNot %vreg15<kill>, <BB#1>, %PC<imp-def,dead>;
30 // Note: The peephole pass makes the instrucstions like
31 // %vreg170<def> = SXTW %vreg166 or %vreg16<def> = NOT_p %vreg15<kill>
32 // redundant and relies on some form of dead removal instructions, like
33 // DCE or DIE to actually eliminate them.
36 //===----------------------------------------------------------------------===//
39 #include "HexagonTargetMachine.h"
40 #include "llvm/ADT/DenseMap.h"
41 #include "llvm/ADT/Statistic.h"
42 #include "llvm/CodeGen/MachineFunction.h"
43 #include "llvm/CodeGen/MachineFunctionPass.h"
44 #include "llvm/CodeGen/MachineInstrBuilder.h"
45 #include "llvm/CodeGen/MachineRegisterInfo.h"
46 #include "llvm/CodeGen/Passes.h"
47 #include "llvm/IR/Constants.h"
48 #include "llvm/PassSupport.h"
49 #include "llvm/Support/CommandLine.h"
50 #include "llvm/Support/Debug.h"
51 #include "llvm/Support/raw_ostream.h"
52 #include "llvm/Target/TargetInstrInfo.h"
53 #include "llvm/Target/TargetMachine.h"
54 #include "llvm/Target/TargetRegisterInfo.h"
59 #define DEBUG_TYPE "hexagon-peephole"
61 static cl::opt<bool> DisableHexagonPeephole("disable-hexagon-peephole",
62 cl::Hidden, cl::ZeroOrMore, cl::init(false),
63 cl::desc("Disable Peephole Optimization"));
65 static cl::opt<bool> DisablePNotP("disable-hexagon-pnotp",
66 cl::Hidden, cl::ZeroOrMore, cl::init(false),
67 cl::desc("Disable Optimization of PNotP"));
69 static cl::opt<bool> DisableOptSZExt("disable-hexagon-optszext",
70 cl::Hidden, cl::ZeroOrMore, cl::init(false),
71 cl::desc("Disable Optimization of Sign/Zero Extends"));
73 static cl::opt<bool> DisableOptExtTo64("disable-hexagon-opt-ext-to-64",
74 cl::Hidden, cl::ZeroOrMore, cl::init(false),
75 cl::desc("Disable Optimization of extensions to i64."));
78 void initializeHexagonPeepholePass(PassRegistry&);
82 struct HexagonPeephole : public MachineFunctionPass {
83 const HexagonInstrInfo *QII;
84 const HexagonRegisterInfo *QRI;
85 const MachineRegisterInfo *MRI;
89 HexagonPeephole() : MachineFunctionPass(ID) {
90 initializeHexagonPeepholePass(*PassRegistry::getPassRegistry());
93 bool runOnMachineFunction(MachineFunction &MF) override;
95 const char *getPassName() const override {
96 return "Hexagon optimize redundant zero and size extends";
99 void getAnalysisUsage(AnalysisUsage &AU) const override {
100 MachineFunctionPass::getAnalysisUsage(AU);
104 void ChangeOpInto(MachineOperand &Dst, MachineOperand &Src);
108 char HexagonPeephole::ID = 0;
110 INITIALIZE_PASS(HexagonPeephole, "hexagon-peephole", "Hexagon Peephole",
113 bool HexagonPeephole::runOnMachineFunction(MachineFunction &MF) {
114 QII = static_cast<const HexagonInstrInfo *>(MF.getSubtarget().getInstrInfo());
115 QRI = MF.getTarget().getSubtarget<HexagonSubtarget>().getRegisterInfo();
116 MRI = &MF.getRegInfo();
118 DenseMap<unsigned, unsigned> PeepholeMap;
119 DenseMap<unsigned, std::pair<unsigned, unsigned> > PeepholeDoubleRegsMap;
121 if (DisableHexagonPeephole) return false;
123 // Loop over all of the basic blocks.
124 for (MachineFunction::iterator MBBb = MF.begin(), MBBe = MF.end();
125 MBBb != MBBe; ++MBBb) {
126 MachineBasicBlock* MBB = MBBb;
128 PeepholeDoubleRegsMap.clear();
130 // Traverse the basic block.
131 for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end();
133 MachineInstr *MI = MII;
134 // Look for sign extends:
135 // %vreg170<def> = SXTW %vreg166
136 if (!DisableOptSZExt && MI->getOpcode() == Hexagon::SXTW) {
137 assert (MI->getNumOperands() == 2);
138 MachineOperand &Dst = MI->getOperand(0);
139 MachineOperand &Src = MI->getOperand(1);
140 unsigned DstReg = Dst.getReg();
141 unsigned SrcReg = Src.getReg();
142 // Just handle virtual registers.
143 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
144 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
145 // Map the following:
146 // %vreg170<def> = SXTW %vreg166
147 // PeepholeMap[170] = vreg166
148 PeepholeMap[DstReg] = SrcReg;
152 // Look for %vreg170<def> = COMBINE_ir_V4 (0, %vreg169)
153 // %vreg170:DoublRegs, %vreg169:IntRegs
154 if (!DisableOptExtTo64 &&
155 MI->getOpcode () == Hexagon::COMBINE_Ir_V4) {
156 assert (MI->getNumOperands() == 3);
157 MachineOperand &Dst = MI->getOperand(0);
158 MachineOperand &Src1 = MI->getOperand(1);
159 MachineOperand &Src2 = MI->getOperand(2);
160 if (Src1.getImm() != 0)
162 unsigned DstReg = Dst.getReg();
163 unsigned SrcReg = Src2.getReg();
164 PeepholeMap[DstReg] = SrcReg;
167 // Look for this sequence below
168 // %vregDoubleReg1 = LSRd_ri %vregDoubleReg0, 32
169 // %vregIntReg = COPY %vregDoubleReg1:subreg_loreg.
171 // %vregIntReg = COPY %vregDoubleReg0:subreg_hireg.
172 if (MI->getOpcode() == Hexagon::LSRd_ri) {
173 assert(MI->getNumOperands() == 3);
174 MachineOperand &Dst = MI->getOperand(0);
175 MachineOperand &Src1 = MI->getOperand(1);
176 MachineOperand &Src2 = MI->getOperand(2);
177 if (Src2.getImm() != 32)
179 unsigned DstReg = Dst.getReg();
180 unsigned SrcReg = Src1.getReg();
181 PeepholeDoubleRegsMap[DstReg] =
182 std::make_pair(*&SrcReg, 1/*Hexagon::subreg_hireg*/);
185 // Look for P=NOT(P).
187 (MI->getOpcode() == Hexagon::NOT_p)) {
188 assert (MI->getNumOperands() == 2);
189 MachineOperand &Dst = MI->getOperand(0);
190 MachineOperand &Src = MI->getOperand(1);
191 unsigned DstReg = Dst.getReg();
192 unsigned SrcReg = Src.getReg();
193 // Just handle virtual registers.
194 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
195 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
196 // Map the following:
197 // %vreg170<def> = NOT_xx %vreg166
198 // PeepholeMap[170] = vreg166
199 PeepholeMap[DstReg] = SrcReg;
204 // %vreg176<def> = COPY %vreg170:subreg_loreg
205 if (!DisableOptSZExt && MI->isCopy()) {
206 assert (MI->getNumOperands() == 2);
207 MachineOperand &Dst = MI->getOperand(0);
208 MachineOperand &Src = MI->getOperand(1);
210 // Make sure we are copying the lower 32 bits.
211 if (Src.getSubReg() != Hexagon::subreg_loreg)
214 unsigned DstReg = Dst.getReg();
215 unsigned SrcReg = Src.getReg();
216 if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
217 TargetRegisterInfo::isVirtualRegister(SrcReg)) {
218 // Try to find in the map.
219 if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) {
220 // Change the 1st operand.
221 MI->RemoveOperand(1);
222 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc, false));
224 DenseMap<unsigned, std::pair<unsigned, unsigned> >::iterator DI =
225 PeepholeDoubleRegsMap.find(SrcReg);
226 if (DI != PeepholeDoubleRegsMap.end()) {
227 std::pair<unsigned,unsigned> PeepholeSrc = DI->second;
228 MI->RemoveOperand(1);
229 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc.first,
235 false /*isEarlyClobber*/,
236 PeepholeSrc.second));
242 // Look for Predicated instructions.
245 if (QII->isPredicated(MI)) {
246 MachineOperand &Op0 = MI->getOperand(0);
247 unsigned Reg0 = Op0.getReg();
248 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
249 if (RC0->getID() == Hexagon::PredRegsRegClassID) {
250 // Handle instructions that have a prediate register in op0
251 // (most cases of predicable instructions).
252 if (TargetRegisterInfo::isVirtualRegister(Reg0)) {
253 // Try to find in the map.
254 if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
255 // Change the 1st operand and, flip the opcode.
256 MI->getOperand(0).setReg(PeepholeSrc);
257 int NewOp = QII->getInvertedPredicatedOpcode(MI->getOpcode());
258 MI->setDesc(QII->get(NewOp));
266 // Handle special instructions.
267 unsigned Op = MI->getOpcode();
269 unsigned PR = 1, S1 = 2, S2 = 3; // Operand indices.
272 case Hexagon::TFR_condset_rr:
273 case Hexagon::TFR_condset_ii:
274 case Hexagon::MUX_ii:
275 case Hexagon::MUX_rr:
278 case Hexagon::TFR_condset_ri:
279 NewOp = Hexagon::TFR_condset_ir;
281 case Hexagon::TFR_condset_ir:
282 NewOp = Hexagon::TFR_condset_ri;
284 case Hexagon::MUX_ri:
285 NewOp = Hexagon::MUX_ir;
287 case Hexagon::MUX_ir:
288 NewOp = Hexagon::MUX_ri;
292 unsigned PSrc = MI->getOperand(PR).getReg();
293 if (unsigned POrig = PeepholeMap.lookup(PSrc)) {
294 MI->getOperand(PR).setReg(POrig);
295 MI->setDesc(QII->get(NewOp));
296 // Swap operands S1 and S2.
297 MachineOperand Op1 = MI->getOperand(S1);
298 MachineOperand Op2 = MI->getOperand(S2);
299 ChangeOpInto(MI->getOperand(S1), Op2);
300 ChangeOpInto(MI->getOperand(S2), Op1);
305 } // if (!DisablePNotP)
312 void HexagonPeephole::ChangeOpInto(MachineOperand &Dst, MachineOperand &Src) {
313 assert (&Dst != &Src && "Cannot duplicate into itself");
314 switch (Dst.getType()) {
315 case MachineOperand::MO_Register:
317 Dst.setReg(Src.getReg());
318 } else if (Src.isImm()) {
319 Dst.ChangeToImmediate(Src.getImm());
321 llvm_unreachable("Unexpected src operand type");
325 case MachineOperand::MO_Immediate:
327 Dst.setImm(Src.getImm());
328 } else if (Src.isReg()) {
329 Dst.ChangeToRegister(Src.getReg(), Src.isDef(), Src.isImplicit(),
330 Src.isKill(), Src.isDead(), Src.isUndef(),
333 llvm_unreachable("Unexpected src operand type");
338 llvm_unreachable("Unexpected dst operand type");
343 FunctionPass *llvm::createHexagonPeephole() {
344 return new HexagonPeephole();