1 //===-- lib/CodeGen/MachineInstr.cpp --------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Methods common to all machine instructions.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineInstr.h"
15 #include "llvm/ADT/FoldingSet.h"
16 #include "llvm/ADT/Hashing.h"
17 #include "llvm/Analysis/AliasAnalysis.h"
18 #include "llvm/CodeGen/MachineConstantPool.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineMemOperand.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/DebugInfo.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/IR/InlineAsm.h"
28 #include "llvm/IR/LLVMContext.h"
29 #include "llvm/IR/Metadata.h"
30 #include "llvm/IR/Module.h"
31 #include "llvm/IR/ModuleSlotTracker.h"
32 #include "llvm/IR/Type.h"
33 #include "llvm/IR/Value.h"
34 #include "llvm/MC/MCInstrDesc.h"
35 #include "llvm/MC/MCSymbol.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetMachine.h"
42 #include "llvm/Target/TargetRegisterInfo.h"
43 #include "llvm/Target/TargetSubtargetInfo.h"
46 //===----------------------------------------------------------------------===//
47 // MachineOperand Implementation
48 //===----------------------------------------------------------------------===//
50 void MachineOperand::setReg(unsigned Reg) {
51 if (getReg() == Reg) return; // No change.
53 // Otherwise, we have to change the register. If this operand is embedded
54 // into a machine function, we need to update the old and new register's
56 if (MachineInstr *MI = getParent())
57 if (MachineBasicBlock *MBB = MI->getParent())
58 if (MachineFunction *MF = MBB->getParent()) {
59 MachineRegisterInfo &MRI = MF->getRegInfo();
60 MRI.removeRegOperandFromUseList(this);
61 SmallContents.RegNo = Reg;
62 MRI.addRegOperandToUseList(this);
66 // Otherwise, just change the register, no problem. :)
67 SmallContents.RegNo = Reg;
70 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx,
71 const TargetRegisterInfo &TRI) {
72 assert(TargetRegisterInfo::isVirtualRegister(Reg));
73 if (SubIdx && getSubReg())
74 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
80 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
81 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
83 Reg = TRI.getSubReg(Reg, getSubReg());
84 // Note that getSubReg() may return 0 if the sub-register doesn't exist.
85 // That won't happen in legal code.
91 /// Change a def to a use, or a use to a def.
92 void MachineOperand::setIsDef(bool Val) {
93 assert(isReg() && "Wrong MachineOperand accessor");
94 assert((!Val || !isDebug()) && "Marking a debug operation as def");
97 // MRI may keep uses and defs in different list positions.
98 if (MachineInstr *MI = getParent())
99 if (MachineBasicBlock *MBB = MI->getParent())
100 if (MachineFunction *MF = MBB->getParent()) {
101 MachineRegisterInfo &MRI = MF->getRegInfo();
102 MRI.removeRegOperandFromUseList(this);
104 MRI.addRegOperandToUseList(this);
110 // If this operand is currently a register operand, and if this is in a
111 // function, deregister the operand from the register's use/def list.
112 void MachineOperand::removeRegFromUses() {
113 if (!isReg() || !isOnRegUseList())
116 if (MachineInstr *MI = getParent()) {
117 if (MachineBasicBlock *MBB = MI->getParent()) {
118 if (MachineFunction *MF = MBB->getParent())
119 MF->getRegInfo().removeRegOperandFromUseList(this);
124 /// ChangeToImmediate - Replace this operand with a new immediate operand of
125 /// the specified value. If an operand is known to be an immediate already,
126 /// the setImm method should be used.
127 void MachineOperand::ChangeToImmediate(int64_t ImmVal) {
128 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
132 OpKind = MO_Immediate;
133 Contents.ImmVal = ImmVal;
136 void MachineOperand::ChangeToFPImmediate(const ConstantFP *FPImm) {
137 assert((!isReg() || !isTied()) && "Cannot change a tied operand into an imm");
141 OpKind = MO_FPImmediate;
142 Contents.CFP = FPImm;
145 void MachineOperand::ChangeToES(const char *SymName, unsigned char TargetFlags) {
146 assert((!isReg() || !isTied()) &&
147 "Cannot change a tied operand into an external symbol");
151 OpKind = MO_ExternalSymbol;
152 Contents.OffsetedInfo.Val.SymbolName = SymName;
153 setOffset(0); // Offset is always 0.
154 setTargetFlags(TargetFlags);
157 void MachineOperand::ChangeToMCSymbol(MCSymbol *Sym) {
158 assert((!isReg() || !isTied()) &&
159 "Cannot change a tied operand into an MCSymbol");
163 OpKind = MO_MCSymbol;
167 /// ChangeToRegister - Replace this operand with a new register operand of
168 /// the specified value. If an operand is known to be an register already,
169 /// the setReg method should be used.
170 void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
171 bool isKill, bool isDead, bool isUndef,
173 MachineRegisterInfo *RegInfo = nullptr;
174 if (MachineInstr *MI = getParent())
175 if (MachineBasicBlock *MBB = MI->getParent())
176 if (MachineFunction *MF = MBB->getParent())
177 RegInfo = &MF->getRegInfo();
178 // If this operand is already a register operand, remove it from the
179 // register's use/def lists.
180 bool WasReg = isReg();
181 if (RegInfo && WasReg)
182 RegInfo->removeRegOperandFromUseList(this);
184 // Change this to a register and set the reg#.
185 OpKind = MO_Register;
186 SmallContents.RegNo = Reg;
187 SubReg_TargetFlags = 0;
193 IsInternalRead = false;
194 IsEarlyClobber = false;
196 // Ensure isOnRegUseList() returns false.
197 Contents.Reg.Prev = nullptr;
198 // Preserve the tie when the operand was already a register.
202 // If this operand is embedded in a function, add the operand to the
203 // register's use/def list.
205 RegInfo->addRegOperandToUseList(this);
208 /// isIdenticalTo - Return true if this operand is identical to the specified
209 /// operand. Note that this should stay in sync with the hash_value overload
211 bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
212 if (getType() != Other.getType() ||
213 getTargetFlags() != Other.getTargetFlags())
217 case MachineOperand::MO_Register:
218 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
219 getSubReg() == Other.getSubReg();
220 case MachineOperand::MO_Immediate:
221 return getImm() == Other.getImm();
222 case MachineOperand::MO_CImmediate:
223 return getCImm() == Other.getCImm();
224 case MachineOperand::MO_FPImmediate:
225 return getFPImm() == Other.getFPImm();
226 case MachineOperand::MO_MachineBasicBlock:
227 return getMBB() == Other.getMBB();
228 case MachineOperand::MO_FrameIndex:
229 return getIndex() == Other.getIndex();
230 case MachineOperand::MO_ConstantPoolIndex:
231 case MachineOperand::MO_TargetIndex:
232 return getIndex() == Other.getIndex() && getOffset() == Other.getOffset();
233 case MachineOperand::MO_JumpTableIndex:
234 return getIndex() == Other.getIndex();
235 case MachineOperand::MO_GlobalAddress:
236 return getGlobal() == Other.getGlobal() && getOffset() == Other.getOffset();
237 case MachineOperand::MO_ExternalSymbol:
238 return !strcmp(getSymbolName(), Other.getSymbolName()) &&
239 getOffset() == Other.getOffset();
240 case MachineOperand::MO_BlockAddress:
241 return getBlockAddress() == Other.getBlockAddress() &&
242 getOffset() == Other.getOffset();
243 case MachineOperand::MO_RegisterMask:
244 case MachineOperand::MO_RegisterLiveOut:
245 return getRegMask() == Other.getRegMask();
246 case MachineOperand::MO_MCSymbol:
247 return getMCSymbol() == Other.getMCSymbol();
248 case MachineOperand::MO_CFIIndex:
249 return getCFIIndex() == Other.getCFIIndex();
250 case MachineOperand::MO_Metadata:
251 return getMetadata() == Other.getMetadata();
253 llvm_unreachable("Invalid machine operand type");
256 // Note: this must stay exactly in sync with isIdenticalTo above.
257 hash_code llvm::hash_value(const MachineOperand &MO) {
258 switch (MO.getType()) {
259 case MachineOperand::MO_Register:
260 // Register operands don't have target flags.
261 return hash_combine(MO.getType(), MO.getReg(), MO.getSubReg(), MO.isDef());
262 case MachineOperand::MO_Immediate:
263 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
264 case MachineOperand::MO_CImmediate:
265 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
266 case MachineOperand::MO_FPImmediate:
267 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
268 case MachineOperand::MO_MachineBasicBlock:
269 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
270 case MachineOperand::MO_FrameIndex:
271 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
272 case MachineOperand::MO_ConstantPoolIndex:
273 case MachineOperand::MO_TargetIndex:
274 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
276 case MachineOperand::MO_JumpTableIndex:
277 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
278 case MachineOperand::MO_ExternalSymbol:
279 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
281 case MachineOperand::MO_GlobalAddress:
282 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
284 case MachineOperand::MO_BlockAddress:
285 return hash_combine(MO.getType(), MO.getTargetFlags(),
286 MO.getBlockAddress(), MO.getOffset());
287 case MachineOperand::MO_RegisterMask:
288 case MachineOperand::MO_RegisterLiveOut:
289 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
290 case MachineOperand::MO_Metadata:
291 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
292 case MachineOperand::MO_MCSymbol:
293 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
294 case MachineOperand::MO_CFIIndex:
295 return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
297 llvm_unreachable("Invalid machine operand type");
300 void MachineOperand::print(raw_ostream &OS,
301 const TargetRegisterInfo *TRI) const {
302 ModuleSlotTracker DummyMST(nullptr);
303 print(OS, DummyMST, TRI);
306 void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
307 const TargetRegisterInfo *TRI) const {
309 case MachineOperand::MO_Register:
310 OS << PrintReg(getReg(), TRI, getSubReg());
312 if (isDef() || isKill() || isDead() || isImplicit() || isUndef() ||
313 isInternalRead() || isEarlyClobber() || isTied()) {
315 bool NeedComma = false;
317 if (NeedComma) OS << ',';
318 if (isEarlyClobber())
319 OS << "earlyclobber,";
324 // <def,read-undef> only makes sense when getSubReg() is set.
325 // Don't clutter the output otherwise.
326 if (isUndef() && getSubReg())
328 } else if (isImplicit()) {
334 if (NeedComma) OS << ',';
339 if (NeedComma) OS << ',';
343 if (isUndef() && isUse()) {
344 if (NeedComma) OS << ',';
348 if (isInternalRead()) {
349 if (NeedComma) OS << ',';
354 if (NeedComma) OS << ',';
357 OS << unsigned(TiedTo - 1);
362 case MachineOperand::MO_Immediate:
365 case MachineOperand::MO_CImmediate:
366 getCImm()->getValue().print(OS, false);
368 case MachineOperand::MO_FPImmediate:
369 if (getFPImm()->getType()->isFloatTy())
370 OS << getFPImm()->getValueAPF().convertToFloat();
372 OS << getFPImm()->getValueAPF().convertToDouble();
374 case MachineOperand::MO_MachineBasicBlock:
375 OS << "<BB#" << getMBB()->getNumber() << ">";
377 case MachineOperand::MO_FrameIndex:
378 OS << "<fi#" << getIndex() << '>';
380 case MachineOperand::MO_ConstantPoolIndex:
381 OS << "<cp#" << getIndex();
382 if (getOffset()) OS << "+" << getOffset();
385 case MachineOperand::MO_TargetIndex:
386 OS << "<ti#" << getIndex();
387 if (getOffset()) OS << "+" << getOffset();
390 case MachineOperand::MO_JumpTableIndex:
391 OS << "<jt#" << getIndex() << '>';
393 case MachineOperand::MO_GlobalAddress:
395 getGlobal()->printAsOperand(OS, /*PrintType=*/false, MST);
396 if (getOffset()) OS << "+" << getOffset();
399 case MachineOperand::MO_ExternalSymbol:
400 OS << "<es:" << getSymbolName();
401 if (getOffset()) OS << "+" << getOffset();
404 case MachineOperand::MO_BlockAddress:
406 getBlockAddress()->printAsOperand(OS, /*PrintType=*/false, MST);
407 if (getOffset()) OS << "+" << getOffset();
410 case MachineOperand::MO_RegisterMask:
413 case MachineOperand::MO_RegisterLiveOut:
414 OS << "<regliveout>";
416 case MachineOperand::MO_Metadata:
418 getMetadata()->printAsOperand(OS, MST);
421 case MachineOperand::MO_MCSymbol:
422 OS << "<MCSym=" << *getMCSymbol() << '>';
424 case MachineOperand::MO_CFIIndex:
425 OS << "<call frame instruction>";
429 if (unsigned TF = getTargetFlags())
430 OS << "[TF=" << TF << ']';
433 //===----------------------------------------------------------------------===//
434 // MachineMemOperand Implementation
435 //===----------------------------------------------------------------------===//
437 /// getAddrSpace - Return the LLVM IR address space number that this pointer
439 unsigned MachinePointerInfo::getAddrSpace() const {
440 if (V.isNull() || V.is<const PseudoSourceValue*>()) return 0;
441 return cast<PointerType>(V.get<const Value*>()->getType())->getAddressSpace();
444 /// getConstantPool - Return a MachinePointerInfo record that refers to the
446 MachinePointerInfo MachinePointerInfo::getConstantPool() {
447 return MachinePointerInfo(PseudoSourceValue::getConstantPool());
450 /// getFixedStack - Return a MachinePointerInfo record that refers to the
451 /// the specified FrameIndex.
452 MachinePointerInfo MachinePointerInfo::getFixedStack(int FI, int64_t offset) {
453 return MachinePointerInfo(PseudoSourceValue::getFixedStack(FI), offset);
456 MachinePointerInfo MachinePointerInfo::getJumpTable() {
457 return MachinePointerInfo(PseudoSourceValue::getJumpTable());
460 MachinePointerInfo MachinePointerInfo::getGOT() {
461 return MachinePointerInfo(PseudoSourceValue::getGOT());
464 MachinePointerInfo MachinePointerInfo::getStack(int64_t Offset) {
465 return MachinePointerInfo(PseudoSourceValue::getStack(), Offset);
468 MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f,
469 uint64_t s, unsigned int a,
470 const AAMDNodes &AAInfo,
471 const MDNode *Ranges)
472 : PtrInfo(ptrinfo), Size(s),
473 Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)),
474 AAInfo(AAInfo), Ranges(Ranges) {
475 assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue*>() ||
476 isa<PointerType>(PtrInfo.V.get<const Value*>()->getType())) &&
477 "invalid pointer value");
478 assert(getBaseAlignment() == a && "Alignment is not a power of 2!");
479 assert((isLoad() || isStore()) && "Not a load/store!");
482 /// Profile - Gather unique data for the object.
484 void MachineMemOperand::Profile(FoldingSetNodeID &ID) const {
485 ID.AddInteger(getOffset());
487 ID.AddPointer(getOpaqueValue());
488 ID.AddInteger(Flags);
491 void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) {
492 // The Value and Offset may differ due to CSE. But the flags and size
493 // should be the same.
494 assert(MMO->getFlags() == getFlags() && "Flags mismatch!");
495 assert(MMO->getSize() == getSize() && "Size mismatch!");
497 if (MMO->getBaseAlignment() >= getBaseAlignment()) {
498 // Update the alignment value.
499 Flags = (Flags & ((1 << MOMaxBits) - 1)) |
500 ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits);
501 // Also update the base and offset, because the new alignment may
502 // not be applicable with the old ones.
503 PtrInfo = MMO->PtrInfo;
507 /// getAlignment - Return the minimum known alignment in bytes of the
508 /// actual memory reference.
509 uint64_t MachineMemOperand::getAlignment() const {
510 return MinAlign(getBaseAlignment(), getOffset());
513 void MachineMemOperand::print(raw_ostream &OS) const {
514 ModuleSlotTracker DummyMST(nullptr);
517 void MachineMemOperand::print(raw_ostream &OS, ModuleSlotTracker &MST) const {
518 assert((isLoad() || isStore()) &&
519 "SV has to be a load, store or both.");
530 // Print the address information.
532 if (const Value *V = getValue())
533 V->printAsOperand(OS, /*PrintType=*/false, MST);
534 else if (const PseudoSourceValue *PSV = getPseudoValue())
535 PSV->printCustom(OS);
539 unsigned AS = getAddrSpace();
541 OS << "(addrspace=" << AS << ')';
543 // If the alignment of the memory reference itself differs from the alignment
544 // of the base pointer, print the base alignment explicitly, next to the base
546 if (getBaseAlignment() != getAlignment())
547 OS << "(align=" << getBaseAlignment() << ")";
549 if (getOffset() != 0)
550 OS << "+" << getOffset();
553 // Print the alignment of the reference.
554 if (getBaseAlignment() != getAlignment() || getBaseAlignment() != getSize())
555 OS << "(align=" << getAlignment() << ")";
558 if (const MDNode *TBAAInfo = getAAInfo().TBAA) {
560 if (TBAAInfo->getNumOperands() > 0)
561 TBAAInfo->getOperand(0)->printAsOperand(OS, MST);
567 // Print AA scope info.
568 if (const MDNode *ScopeInfo = getAAInfo().Scope) {
569 OS << "(alias.scope=";
570 if (ScopeInfo->getNumOperands() > 0)
571 for (unsigned i = 0, ie = ScopeInfo->getNumOperands(); i != ie; ++i) {
572 ScopeInfo->getOperand(i)->printAsOperand(OS, MST);
581 // Print AA noalias scope info.
582 if (const MDNode *NoAliasInfo = getAAInfo().NoAlias) {
584 if (NoAliasInfo->getNumOperands() > 0)
585 for (unsigned i = 0, ie = NoAliasInfo->getNumOperands(); i != ie; ++i) {
586 NoAliasInfo->getOperand(i)->printAsOperand(OS, MST);
595 // Print nontemporal info.
597 OS << "(nontemporal)";
603 //===----------------------------------------------------------------------===//
604 // MachineInstr Implementation
605 //===----------------------------------------------------------------------===//
607 void MachineInstr::addImplicitDefUseOperands(MachineFunction &MF) {
608 if (MCID->ImplicitDefs)
609 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
610 addOperand(MF, MachineOperand::CreateReg(*ImpDefs, true, true));
611 if (MCID->ImplicitUses)
612 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses)
613 addOperand(MF, MachineOperand::CreateReg(*ImpUses, false, true));
616 /// MachineInstr ctor - This constructor creates a MachineInstr and adds the
617 /// implicit operands. It reserves space for the number of operands specified by
619 MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid,
620 DebugLoc dl, bool NoImp)
621 : MCID(&tid), Parent(nullptr), Operands(nullptr), NumOperands(0), Flags(0),
622 AsmPrinterFlags(0), NumMemRefs(0), MemRefs(nullptr),
623 debugLoc(std::move(dl)) {
624 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
626 // Reserve space for the expected number of operands.
627 if (unsigned NumOps = MCID->getNumOperands() +
628 MCID->getNumImplicitDefs() + MCID->getNumImplicitUses()) {
629 CapOperands = OperandCapacity::get(NumOps);
630 Operands = MF.allocateOperandArray(CapOperands);
634 addImplicitDefUseOperands(MF);
637 /// MachineInstr ctor - Copies MachineInstr arg exactly
639 MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI)
640 : MCID(&MI.getDesc()), Parent(nullptr), Operands(nullptr), NumOperands(0),
641 Flags(0), AsmPrinterFlags(0),
642 NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs),
643 debugLoc(MI.getDebugLoc()) {
644 assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor");
646 CapOperands = OperandCapacity::get(MI.getNumOperands());
647 Operands = MF.allocateOperandArray(CapOperands);
650 for (const MachineOperand &MO : MI.operands())
653 // Copy all the sensible flags.
657 /// getRegInfo - If this instruction is embedded into a MachineFunction,
658 /// return the MachineRegisterInfo object for the current function, otherwise
660 MachineRegisterInfo *MachineInstr::getRegInfo() {
661 if (MachineBasicBlock *MBB = getParent())
662 return &MBB->getParent()->getRegInfo();
666 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
667 /// this instruction from their respective use lists. This requires that the
668 /// operands already be on their use lists.
669 void MachineInstr::RemoveRegOperandsFromUseLists(MachineRegisterInfo &MRI) {
670 for (MachineOperand &MO : operands())
672 MRI.removeRegOperandFromUseList(&MO);
675 /// AddRegOperandsToUseLists - Add all of the register operands in
676 /// this instruction from their respective use lists. This requires that the
677 /// operands not be on their use lists yet.
678 void MachineInstr::AddRegOperandsToUseLists(MachineRegisterInfo &MRI) {
679 for (MachineOperand &MO : operands())
681 MRI.addRegOperandToUseList(&MO);
684 void MachineInstr::addOperand(const MachineOperand &Op) {
685 MachineBasicBlock *MBB = getParent();
686 assert(MBB && "Use MachineInstrBuilder to add operands to dangling instrs");
687 MachineFunction *MF = MBB->getParent();
688 assert(MF && "Use MachineInstrBuilder to add operands to dangling instrs");
692 /// Move NumOps MachineOperands from Src to Dst, with support for overlapping
693 /// ranges. If MRI is non-null also update use-def chains.
694 static void moveOperands(MachineOperand *Dst, MachineOperand *Src,
695 unsigned NumOps, MachineRegisterInfo *MRI) {
697 return MRI->moveOperands(Dst, Src, NumOps);
699 // MachineOperand is a trivially copyable type so we can just use memmove.
700 std::memmove(Dst, Src, NumOps * sizeof(MachineOperand));
703 /// addOperand - Add the specified operand to the instruction. If it is an
704 /// implicit operand, it is added to the end of the operand list. If it is
705 /// an explicit operand it is added at the end of the explicit operand list
706 /// (before the first implicit operand).
707 void MachineInstr::addOperand(MachineFunction &MF, const MachineOperand &Op) {
708 assert(MCID && "Cannot add operands before providing an instr descriptor");
710 // Check if we're adding one of our existing operands.
711 if (&Op >= Operands && &Op < Operands + NumOperands) {
712 // This is unusual: MI->addOperand(MI->getOperand(i)).
713 // If adding Op requires reallocating or moving existing operands around,
714 // the Op reference could go stale. Support it by copying Op.
715 MachineOperand CopyOp(Op);
716 return addOperand(MF, CopyOp);
719 // Find the insert location for the new operand. Implicit registers go at
720 // the end, everything else goes before the implicit regs.
722 // FIXME: Allow mixed explicit and implicit operands on inline asm.
723 // InstrEmitter::EmitSpecialNode() is marking inline asm clobbers as
724 // implicit-defs, but they must not be moved around. See the FIXME in
726 unsigned OpNo = getNumOperands();
727 bool isImpReg = Op.isReg() && Op.isImplicit();
728 if (!isImpReg && !isInlineAsm()) {
729 while (OpNo && Operands[OpNo-1].isReg() && Operands[OpNo-1].isImplicit()) {
731 assert(!Operands[OpNo].isTied() && "Cannot move tied operands");
736 bool isMetaDataOp = Op.getType() == MachineOperand::MO_Metadata;
737 // OpNo now points as the desired insertion point. Unless this is a variadic
738 // instruction, only implicit regs are allowed beyond MCID->getNumOperands().
739 // RegMask operands go between the explicit and implicit operands.
740 assert((isImpReg || Op.isRegMask() || MCID->isVariadic() ||
741 OpNo < MCID->getNumOperands() || isMetaDataOp) &&
742 "Trying to add an operand to a machine instr that is already done!");
745 MachineRegisterInfo *MRI = getRegInfo();
747 // Determine if the Operands array needs to be reallocated.
748 // Save the old capacity and operand array.
749 OperandCapacity OldCap = CapOperands;
750 MachineOperand *OldOperands = Operands;
751 if (!OldOperands || OldCap.getSize() == getNumOperands()) {
752 CapOperands = OldOperands ? OldCap.getNext() : OldCap.get(1);
753 Operands = MF.allocateOperandArray(CapOperands);
754 // Move the operands before the insertion point.
756 moveOperands(Operands, OldOperands, OpNo, MRI);
759 // Move the operands following the insertion point.
760 if (OpNo != NumOperands)
761 moveOperands(Operands + OpNo + 1, OldOperands + OpNo, NumOperands - OpNo,
765 // Deallocate the old operand array.
766 if (OldOperands != Operands && OldOperands)
767 MF.deallocateOperandArray(OldCap, OldOperands);
769 // Copy Op into place. It still needs to be inserted into the MRI use lists.
770 MachineOperand *NewMO = new (Operands + OpNo) MachineOperand(Op);
771 NewMO->ParentMI = this;
773 // When adding a register operand, tell MRI about it.
774 if (NewMO->isReg()) {
775 // Ensure isOnRegUseList() returns false, regardless of Op's status.
776 NewMO->Contents.Reg.Prev = nullptr;
777 // Ignore existing ties. This is not a property that can be copied.
779 // Add the new operand to MRI, but only for instructions in an MBB.
781 MRI->addRegOperandToUseList(NewMO);
782 // The MCID operand information isn't accurate until we start adding
783 // explicit operands. The implicit operands are added first, then the
784 // explicits are inserted before them.
786 // Tie uses to defs as indicated in MCInstrDesc.
787 if (NewMO->isUse()) {
788 int DefIdx = MCID->getOperandConstraint(OpNo, MCOI::TIED_TO);
790 tieOperands(DefIdx, OpNo);
792 // If the register operand is flagged as early, mark the operand as such.
793 if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
794 NewMO->setIsEarlyClobber(true);
799 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
800 /// fewer operand than it started with.
802 void MachineInstr::RemoveOperand(unsigned OpNo) {
803 assert(OpNo < getNumOperands() && "Invalid operand number");
804 untieRegOperand(OpNo);
807 // Moving tied operands would break the ties.
808 for (unsigned i = OpNo + 1, e = getNumOperands(); i != e; ++i)
809 if (Operands[i].isReg())
810 assert(!Operands[i].isTied() && "Cannot move tied operands");
813 MachineRegisterInfo *MRI = getRegInfo();
814 if (MRI && Operands[OpNo].isReg())
815 MRI->removeRegOperandFromUseList(Operands + OpNo);
817 // Don't call the MachineOperand destructor. A lot of this code depends on
818 // MachineOperand having a trivial destructor anyway, and adding a call here
819 // wouldn't make it 'destructor-correct'.
821 if (unsigned N = NumOperands - 1 - OpNo)
822 moveOperands(Operands + OpNo, Operands + OpNo + 1, N, MRI);
826 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
827 /// This function should be used only occasionally. The setMemRefs function
828 /// is the primary method for setting up a MachineInstr's MemRefs list.
829 void MachineInstr::addMemOperand(MachineFunction &MF,
830 MachineMemOperand *MO) {
831 mmo_iterator OldMemRefs = MemRefs;
832 unsigned OldNumMemRefs = NumMemRefs;
834 unsigned NewNum = NumMemRefs + 1;
835 mmo_iterator NewMemRefs = MF.allocateMemRefsArray(NewNum);
837 std::copy(OldMemRefs, OldMemRefs + OldNumMemRefs, NewMemRefs);
838 NewMemRefs[NewNum - 1] = MO;
839 setMemRefs(NewMemRefs, NewMemRefs + NewNum);
842 bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const {
843 assert(!isBundledWithPred() && "Must be called on bundle header");
844 for (MachineBasicBlock::const_instr_iterator MII = this;; ++MII) {
845 if (MII->getDesc().getFlags() & Mask) {
846 if (Type == AnyInBundle)
849 if (Type == AllInBundle && !MII->isBundle())
852 // This was the last instruction in the bundle.
853 if (!MII->isBundledWithSucc())
854 return Type == AllInBundle;
858 bool MachineInstr::isIdenticalTo(const MachineInstr *Other,
859 MICheckType Check) const {
860 // If opcodes or number of operands are not the same then the two
861 // instructions are obviously not identical.
862 if (Other->getOpcode() != getOpcode() ||
863 Other->getNumOperands() != getNumOperands())
867 // Both instructions are bundles, compare MIs inside the bundle.
868 MachineBasicBlock::const_instr_iterator I1 = *this;
869 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
870 MachineBasicBlock::const_instr_iterator I2 = *Other;
871 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
872 while (++I1 != E1 && I1->isInsideBundle()) {
874 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
879 // Check operands to make sure they match.
880 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
881 const MachineOperand &MO = getOperand(i);
882 const MachineOperand &OMO = Other->getOperand(i);
884 if (!MO.isIdenticalTo(OMO))
889 // Clients may or may not want to ignore defs when testing for equality.
890 // For example, machine CSE pass only cares about finding common
891 // subexpressions, so it's safe to ignore virtual register defs.
893 if (Check == IgnoreDefs)
895 else if (Check == IgnoreVRegDefs) {
896 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()) ||
897 TargetRegisterInfo::isPhysicalRegister(OMO.getReg()))
898 if (MO.getReg() != OMO.getReg())
901 if (!MO.isIdenticalTo(OMO))
903 if (Check == CheckKillDead && MO.isDead() != OMO.isDead())
907 if (!MO.isIdenticalTo(OMO))
909 if (Check == CheckKillDead && MO.isKill() != OMO.isKill())
913 // If DebugLoc does not match then two dbg.values are not identical.
915 if (getDebugLoc() && Other->getDebugLoc() &&
916 getDebugLoc() != Other->getDebugLoc())
921 MachineInstr *MachineInstr::removeFromParent() {
922 assert(getParent() && "Not embedded in a basic block!");
923 return getParent()->remove(this);
926 MachineInstr *MachineInstr::removeFromBundle() {
927 assert(getParent() && "Not embedded in a basic block!");
928 return getParent()->remove_instr(this);
931 void MachineInstr::eraseFromParent() {
932 assert(getParent() && "Not embedded in a basic block!");
933 getParent()->erase(this);
936 void MachineInstr::eraseFromParentAndMarkDBGValuesForRemoval() {
937 assert(getParent() && "Not embedded in a basic block!");
938 MachineBasicBlock *MBB = getParent();
939 MachineFunction *MF = MBB->getParent();
940 assert(MF && "Not embedded in a function!");
942 MachineInstr *MI = (MachineInstr *)this;
943 MachineRegisterInfo &MRI = MF->getRegInfo();
945 for (const MachineOperand &MO : MI->operands()) {
946 if (!MO.isReg() || !MO.isDef())
948 unsigned Reg = MO.getReg();
949 if (!TargetRegisterInfo::isVirtualRegister(Reg))
951 MRI.markUsesInDebugValueAsUndef(Reg);
953 MI->eraseFromParent();
956 void MachineInstr::eraseFromBundle() {
957 assert(getParent() && "Not embedded in a basic block!");
958 getParent()->erase_instr(this);
961 /// getNumExplicitOperands - Returns the number of non-implicit operands.
963 unsigned MachineInstr::getNumExplicitOperands() const {
964 unsigned NumOperands = MCID->getNumOperands();
965 if (!MCID->isVariadic())
968 for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) {
969 const MachineOperand &MO = getOperand(i);
970 if (!MO.isReg() || !MO.isImplicit())
976 void MachineInstr::bundleWithPred() {
977 assert(!isBundledWithPred() && "MI is already bundled with its predecessor");
978 setFlag(BundledPred);
979 MachineBasicBlock::instr_iterator Pred = this;
981 assert(!Pred->isBundledWithSucc() && "Inconsistent bundle flags");
982 Pred->setFlag(BundledSucc);
985 void MachineInstr::bundleWithSucc() {
986 assert(!isBundledWithSucc() && "MI is already bundled with its successor");
987 setFlag(BundledSucc);
988 MachineBasicBlock::instr_iterator Succ = this;
990 assert(!Succ->isBundledWithPred() && "Inconsistent bundle flags");
991 Succ->setFlag(BundledPred);
994 void MachineInstr::unbundleFromPred() {
995 assert(isBundledWithPred() && "MI isn't bundled with its predecessor");
996 clearFlag(BundledPred);
997 MachineBasicBlock::instr_iterator Pred = this;
999 assert(Pred->isBundledWithSucc() && "Inconsistent bundle flags");
1000 Pred->clearFlag(BundledSucc);
1003 void MachineInstr::unbundleFromSucc() {
1004 assert(isBundledWithSucc() && "MI isn't bundled with its successor");
1005 clearFlag(BundledSucc);
1006 MachineBasicBlock::instr_iterator Succ = this;
1008 assert(Succ->isBundledWithPred() && "Inconsistent bundle flags");
1009 Succ->clearFlag(BundledPred);
1012 bool MachineInstr::isStackAligningInlineAsm() const {
1013 if (isInlineAsm()) {
1014 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1015 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1021 InlineAsm::AsmDialect MachineInstr::getInlineAsmDialect() const {
1022 assert(isInlineAsm() && "getInlineAsmDialect() only works for inline asms!");
1023 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1024 return InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect) != 0);
1027 int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx,
1028 unsigned *GroupNo) const {
1029 assert(isInlineAsm() && "Expected an inline asm instruction");
1030 assert(OpIdx < getNumOperands() && "OpIdx out of range");
1032 // Ignore queries about the initial operands.
1033 if (OpIdx < InlineAsm::MIOp_FirstOperand)
1038 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1040 const MachineOperand &FlagMO = getOperand(i);
1041 // If we reach the implicit register operands, stop looking.
1042 if (!FlagMO.isImm())
1044 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1045 if (i + NumOps > OpIdx) {
1055 const TargetRegisterClass*
1056 MachineInstr::getRegClassConstraint(unsigned OpIdx,
1057 const TargetInstrInfo *TII,
1058 const TargetRegisterInfo *TRI) const {
1059 assert(getParent() && "Can't have an MBB reference here!");
1060 assert(getParent()->getParent() && "Can't have an MF reference here!");
1061 const MachineFunction &MF = *getParent()->getParent();
1063 // Most opcodes have fixed constraints in their MCInstrDesc.
1065 return TII->getRegClass(getDesc(), OpIdx, TRI, MF);
1067 if (!getOperand(OpIdx).isReg())
1070 // For tied uses on inline asm, get the constraint from the def.
1072 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
1075 // Inline asm stores register class constraints in the flag word.
1076 int FlagIdx = findInlineAsmFlagIdx(OpIdx);
1080 unsigned Flag = getOperand(FlagIdx).getImm();
1082 if (InlineAsm::hasRegClassConstraint(Flag, RCID))
1083 return TRI->getRegClass(RCID);
1085 // Assume that all registers in a memory operand are pointers.
1086 if (InlineAsm::getKind(Flag) == InlineAsm::Kind_Mem)
1087 return TRI->getPointerRegClass(MF);
1092 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
1093 unsigned Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
1094 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
1095 // Check every operands inside the bundle if we have
1098 for (ConstMIBundleOperands OpndIt(this); OpndIt.isValid() && CurRC;
1100 CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(
1101 OpndIt.getOperandNo(), Reg, CurRC, TII, TRI);
1103 // Otherwise, just check the current operands.
1104 for (unsigned i = 0, e = NumOperands; i < e && CurRC; ++i)
1105 CurRC = getRegClassConstraintEffectForVRegImpl(i, Reg, CurRC, TII, TRI);
1109 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
1110 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1111 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
1112 assert(CurRC && "Invalid initial register class");
1113 // Check if Reg is constrained by some of its use/def from MI.
1114 const MachineOperand &MO = getOperand(OpIdx);
1115 if (!MO.isReg() || MO.getReg() != Reg)
1117 // If yes, accumulate the constraints through the operand.
1118 return getRegClassConstraintEffect(OpIdx, CurRC, TII, TRI);
1121 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
1122 unsigned OpIdx, const TargetRegisterClass *CurRC,
1123 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
1124 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
1125 const MachineOperand &MO = getOperand(OpIdx);
1126 assert(MO.isReg() &&
1127 "Cannot get register constraints for non-register operand");
1128 assert(CurRC && "Invalid initial register class");
1129 if (unsigned SubIdx = MO.getSubReg()) {
1131 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx);
1133 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx);
1135 CurRC = TRI->getCommonSubClass(CurRC, OpRC);
1139 /// Return the number of instructions inside the MI bundle, not counting the
1140 /// header instruction.
1141 unsigned MachineInstr::getBundleSize() const {
1142 MachineBasicBlock::const_instr_iterator I = this;
1144 while (I->isBundledWithSucc())
1149 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
1150 /// the specific register or -1 if it is not found. It further tightens
1151 /// the search criteria to a use that kills the register if isKill is true.
1152 int MachineInstr::findRegisterUseOperandIdx(unsigned Reg, bool isKill,
1153 const TargetRegisterInfo *TRI) const {
1154 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1155 const MachineOperand &MO = getOperand(i);
1156 if (!MO.isReg() || !MO.isUse())
1158 unsigned MOReg = MO.getReg();
1163 TargetRegisterInfo::isPhysicalRegister(MOReg) &&
1164 TargetRegisterInfo::isPhysicalRegister(Reg) &&
1165 TRI->isSubRegister(MOReg, Reg)))
1166 if (!isKill || MO.isKill())
1172 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
1173 /// indicating if this instruction reads or writes Reg. This also considers
1174 /// partial defines.
1175 std::pair<bool,bool>
1176 MachineInstr::readsWritesVirtualRegister(unsigned Reg,
1177 SmallVectorImpl<unsigned> *Ops) const {
1178 bool PartDef = false; // Partial redefine.
1179 bool FullDef = false; // Full define.
1182 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1183 const MachineOperand &MO = getOperand(i);
1184 if (!MO.isReg() || MO.getReg() != Reg)
1189 Use |= !MO.isUndef();
1190 else if (MO.getSubReg() && !MO.isUndef())
1191 // A partial <def,undef> doesn't count as reading the register.
1196 // A partial redefine uses Reg unless there is also a full define.
1197 return std::make_pair(Use || (PartDef && !FullDef), PartDef || FullDef);
1200 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
1201 /// the specified register or -1 if it is not found. If isDead is true, defs
1202 /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it
1203 /// also checks if there is a def of a super-register.
1205 MachineInstr::findRegisterDefOperandIdx(unsigned Reg, bool isDead, bool Overlap,
1206 const TargetRegisterInfo *TRI) const {
1207 bool isPhys = TargetRegisterInfo::isPhysicalRegister(Reg);
1208 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1209 const MachineOperand &MO = getOperand(i);
1210 // Accept regmask operands when Overlap is set.
1211 // Ignore them when looking for a specific def operand (Overlap == false).
1212 if (isPhys && Overlap && MO.isRegMask() && MO.clobbersPhysReg(Reg))
1214 if (!MO.isReg() || !MO.isDef())
1216 unsigned MOReg = MO.getReg();
1217 bool Found = (MOReg == Reg);
1218 if (!Found && TRI && isPhys &&
1219 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1221 Found = TRI->regsOverlap(MOReg, Reg);
1223 Found = TRI->isSubRegister(MOReg, Reg);
1225 if (Found && (!isDead || MO.isDead()))
1231 /// findFirstPredOperandIdx() - Find the index of the first operand in the
1232 /// operand list that is used to represent the predicate. It returns -1 if
1234 int MachineInstr::findFirstPredOperandIdx() const {
1235 // Don't call MCID.findFirstPredOperandIdx() because this variant
1236 // is sometimes called on an instruction that's not yet complete, and
1237 // so the number of operands is less than the MCID indicates. In
1238 // particular, the PTX target does this.
1239 const MCInstrDesc &MCID = getDesc();
1240 if (MCID.isPredicable()) {
1241 for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
1242 if (MCID.OpInfo[i].isPredicate())
1249 // MachineOperand::TiedTo is 4 bits wide.
1250 const unsigned TiedMax = 15;
1252 /// tieOperands - Mark operands at DefIdx and UseIdx as tied to each other.
1254 /// Use and def operands can be tied together, indicated by a non-zero TiedTo
1255 /// field. TiedTo can have these values:
1257 /// 0: Operand is not tied to anything.
1258 /// 1 to TiedMax-1: Tied to getOperand(TiedTo-1).
1259 /// TiedMax: Tied to an operand >= TiedMax-1.
1261 /// The tied def must be one of the first TiedMax operands on a normal
1262 /// instruction. INLINEASM instructions allow more tied defs.
1264 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) {
1265 MachineOperand &DefMO = getOperand(DefIdx);
1266 MachineOperand &UseMO = getOperand(UseIdx);
1267 assert(DefMO.isDef() && "DefIdx must be a def operand");
1268 assert(UseMO.isUse() && "UseIdx must be a use operand");
1269 assert(!DefMO.isTied() && "Def is already tied to another use");
1270 assert(!UseMO.isTied() && "Use is already tied to another def");
1272 if (DefIdx < TiedMax)
1273 UseMO.TiedTo = DefIdx + 1;
1275 // Inline asm can use the group descriptors to find tied operands, but on
1276 // normal instruction, the tied def must be within the first TiedMax
1278 assert(isInlineAsm() && "DefIdx out of range");
1279 UseMO.TiedTo = TiedMax;
1282 // UseIdx can be out of range, we'll search for it in findTiedOperandIdx().
1283 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax);
1286 /// Given the index of a tied register operand, find the operand it is tied to.
1287 /// Defs are tied to uses and vice versa. Returns the index of the tied operand
1288 /// which must exist.
1289 unsigned MachineInstr::findTiedOperandIdx(unsigned OpIdx) const {
1290 const MachineOperand &MO = getOperand(OpIdx);
1291 assert(MO.isTied() && "Operand isn't tied");
1293 // Normally TiedTo is in range.
1294 if (MO.TiedTo < TiedMax)
1295 return MO.TiedTo - 1;
1297 // Uses on normal instructions can be out of range.
1298 if (!isInlineAsm()) {
1299 // Normal tied defs must be in the 0..TiedMax-1 range.
1302 // MO is a def. Search for the tied use.
1303 for (unsigned i = TiedMax - 1, e = getNumOperands(); i != e; ++i) {
1304 const MachineOperand &UseMO = getOperand(i);
1305 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1308 llvm_unreachable("Can't find tied use");
1311 // Now deal with inline asm by parsing the operand group descriptor flags.
1312 // Find the beginning of each operand group.
1313 SmallVector<unsigned, 8> GroupIdx;
1314 unsigned OpIdxGroup = ~0u;
1316 for (unsigned i = InlineAsm::MIOp_FirstOperand, e = getNumOperands(); i < e;
1318 const MachineOperand &FlagMO = getOperand(i);
1319 assert(FlagMO.isImm() && "Invalid tied operand on inline asm");
1320 unsigned CurGroup = GroupIdx.size();
1321 GroupIdx.push_back(i);
1322 NumOps = 1 + InlineAsm::getNumOperandRegisters(FlagMO.getImm());
1323 // OpIdx belongs to this operand group.
1324 if (OpIdx > i && OpIdx < i + NumOps)
1325 OpIdxGroup = CurGroup;
1327 if (!InlineAsm::isUseOperandTiedToDef(FlagMO.getImm(), TiedGroup))
1329 // Operands in this group are tied to operands in TiedGroup which must be
1330 // earlier. Find the number of operands between the two groups.
1331 unsigned Delta = i - GroupIdx[TiedGroup];
1333 // OpIdx is a use tied to TiedGroup.
1334 if (OpIdxGroup == CurGroup)
1335 return OpIdx - Delta;
1337 // OpIdx is a def tied to this use group.
1338 if (OpIdxGroup == TiedGroup)
1339 return OpIdx + Delta;
1341 llvm_unreachable("Invalid tied operand on inline asm");
1344 /// clearKillInfo - Clears kill flags on all operands.
1346 void MachineInstr::clearKillInfo() {
1347 for (MachineOperand &MO : operands()) {
1348 if (MO.isReg() && MO.isUse())
1349 MO.setIsKill(false);
1353 void MachineInstr::substituteRegister(unsigned FromReg,
1356 const TargetRegisterInfo &RegInfo) {
1357 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
1359 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1360 for (MachineOperand &MO : operands()) {
1361 if (!MO.isReg() || MO.getReg() != FromReg)
1363 MO.substPhysReg(ToReg, RegInfo);
1366 for (MachineOperand &MO : operands()) {
1367 if (!MO.isReg() || MO.getReg() != FromReg)
1369 MO.substVirtReg(ToReg, SubIdx, RegInfo);
1374 /// isSafeToMove - Return true if it is safe to move this instruction. If
1375 /// SawStore is set to true, it means that there is a store (or call) between
1376 /// the instruction's location and its intended destination.
1377 bool MachineInstr::isSafeToMove(AliasAnalysis *AA, bool &SawStore) const {
1378 // Ignore stuff that we obviously can't move.
1380 // Treat volatile loads as stores. This is not strictly necessary for
1381 // volatiles, but it is required for atomic loads. It is not allowed to move
1382 // a load across an atomic load with Ordering > Monotonic.
1383 if (mayStore() || isCall() ||
1384 (mayLoad() && hasOrderedMemoryRef())) {
1389 if (isPosition() || isDebugValue() || isTerminator() ||
1390 hasUnmodeledSideEffects())
1393 // See if this instruction does a load. If so, we have to guarantee that the
1394 // loaded value doesn't change between the load and the its intended
1395 // destination. The check for isInvariantLoad gives the targe the chance to
1396 // classify the load as always returning a constant, e.g. a constant pool
1398 if (mayLoad() && !isInvariantLoad(AA))
1399 // Otherwise, this is a real load. If there is a store between the load and
1400 // end of block, we can't move it.
1406 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1407 /// or volatile memory reference, or if the information describing the memory
1408 /// reference is not available. Return false if it is known to have no ordered
1409 /// memory references.
1410 bool MachineInstr::hasOrderedMemoryRef() const {
1411 // An instruction known never to access memory won't have a volatile access.
1415 !hasUnmodeledSideEffects())
1418 // Otherwise, if the instruction has no memory reference information,
1419 // conservatively assume it wasn't preserved.
1420 if (memoperands_empty())
1423 // Check the memory reference information for ordered references.
1424 for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I)
1425 if (!(*I)->isUnordered())
1431 /// isInvariantLoad - Return true if this instruction is loading from a
1432 /// location whose value is invariant across the function. For example,
1433 /// loading a value from the constant pool or from the argument area
1434 /// of a function if it does not change. This should only return true of
1435 /// *all* loads the instruction does are invariant (if it does multiple loads).
1436 bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const {
1437 // If the instruction doesn't load at all, it isn't an invariant load.
1441 // If the instruction has lost its memoperands, conservatively assume that
1442 // it may not be an invariant load.
1443 if (memoperands_empty())
1446 const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo();
1448 for (mmo_iterator I = memoperands_begin(),
1449 E = memoperands_end(); I != E; ++I) {
1450 if ((*I)->isVolatile()) return false;
1451 if ((*I)->isStore()) return false;
1452 if ((*I)->isInvariant()) return true;
1455 // A load from a constant PseudoSourceValue is invariant.
1456 if (const PseudoSourceValue *PSV = (*I)->getPseudoValue())
1457 if (PSV->isConstant(MFI))
1460 if (const Value *V = (*I)->getValue()) {
1461 // If we have an AliasAnalysis, ask it whether the memory is constant.
1463 AA->pointsToConstantMemory(
1464 MemoryLocation(V, (*I)->getSize(), (*I)->getAAInfo())))
1468 // Otherwise assume conservatively.
1472 // Everything checks out.
1476 /// isConstantValuePHI - If the specified instruction is a PHI that always
1477 /// merges together the same virtual register, return the register, otherwise
1479 unsigned MachineInstr::isConstantValuePHI() const {
1482 assert(getNumOperands() >= 3 &&
1483 "It's illegal to have a PHI without source operands");
1485 unsigned Reg = getOperand(1).getReg();
1486 for (unsigned i = 3, e = getNumOperands(); i < e; i += 2)
1487 if (getOperand(i).getReg() != Reg)
1492 bool MachineInstr::hasUnmodeledSideEffects() const {
1493 if (hasProperty(MCID::UnmodeledSideEffects))
1495 if (isInlineAsm()) {
1496 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1497 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1504 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1506 bool MachineInstr::allDefsAreDead() const {
1507 for (const MachineOperand &MO : operands()) {
1508 if (!MO.isReg() || MO.isUse())
1516 /// copyImplicitOps - Copy implicit register operands from specified
1517 /// instruction to this instruction.
1518 void MachineInstr::copyImplicitOps(MachineFunction &MF,
1519 const MachineInstr *MI) {
1520 for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands();
1522 const MachineOperand &MO = MI->getOperand(i);
1523 if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask())
1528 void MachineInstr::dump() const {
1529 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
1530 dbgs() << " " << *this;
1534 void MachineInstr::print(raw_ostream &OS, bool SkipOpers) const {
1535 const Module *M = nullptr;
1536 if (const MachineBasicBlock *MBB = getParent())
1537 if (const MachineFunction *MF = MBB->getParent())
1538 M = MF->getFunction()->getParent();
1540 ModuleSlotTracker MST(M);
1541 print(OS, MST, SkipOpers);
1544 void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
1545 bool SkipOpers) const {
1546 // We can be a bit tidier if we know the MachineFunction.
1547 const MachineFunction *MF = nullptr;
1548 const TargetRegisterInfo *TRI = nullptr;
1549 const MachineRegisterInfo *MRI = nullptr;
1550 const TargetInstrInfo *TII = nullptr;
1551 if (const MachineBasicBlock *MBB = getParent()) {
1552 MF = MBB->getParent();
1554 MRI = &MF->getRegInfo();
1555 TRI = MF->getSubtarget().getRegisterInfo();
1556 TII = MF->getSubtarget().getInstrInfo();
1560 // Save a list of virtual registers.
1561 SmallVector<unsigned, 8> VirtRegs;
1563 // Print explicitly defined operands on the left of an assignment syntax.
1564 unsigned StartOp = 0, e = getNumOperands();
1565 for (; StartOp < e && getOperand(StartOp).isReg() &&
1566 getOperand(StartOp).isDef() &&
1567 !getOperand(StartOp).isImplicit();
1569 if (StartOp != 0) OS << ", ";
1570 getOperand(StartOp).print(OS, MST, TRI);
1571 unsigned Reg = getOperand(StartOp).getReg();
1572 if (TargetRegisterInfo::isVirtualRegister(Reg))
1573 VirtRegs.push_back(Reg);
1579 // Print the opcode name.
1581 OS << TII->getName(getOpcode());
1588 // Print the rest of the operands.
1589 bool OmittedAnyCallClobbers = false;
1590 bool FirstOp = true;
1591 unsigned AsmDescOp = ~0u;
1592 unsigned AsmOpCount = 0;
1594 if (isInlineAsm() && e >= InlineAsm::MIOp_FirstOperand) {
1595 // Print asm string.
1597 getOperand(InlineAsm::MIOp_AsmString).print(OS, MST, TRI);
1599 // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
1600 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
1601 if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
1602 OS << " [sideeffect]";
1603 if (ExtraInfo & InlineAsm::Extra_MayLoad)
1605 if (ExtraInfo & InlineAsm::Extra_MayStore)
1606 OS << " [maystore]";
1607 if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
1608 OS << " [alignstack]";
1609 if (getInlineAsmDialect() == InlineAsm::AD_ATT)
1610 OS << " [attdialect]";
1611 if (getInlineAsmDialect() == InlineAsm::AD_Intel)
1612 OS << " [inteldialect]";
1614 StartOp = AsmDescOp = InlineAsm::MIOp_FirstOperand;
1619 for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
1620 const MachineOperand &MO = getOperand(i);
1622 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1623 VirtRegs.push_back(MO.getReg());
1625 // Omit call-clobbered registers which aren't used anywhere. This makes
1626 // call instructions much less noisy on targets where calls clobber lots
1627 // of registers. Don't rely on MO.isDead() because we may be called before
1628 // LiveVariables is run, or we may be looking at a non-allocatable reg.
1629 if (MRI && isCall() &&
1630 MO.isReg() && MO.isImplicit() && MO.isDef()) {
1631 unsigned Reg = MO.getReg();
1632 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1633 if (MRI->use_empty(Reg)) {
1634 bool HasAliasLive = false;
1635 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
1636 unsigned AliasReg = *AI;
1637 if (!MRI->use_empty(AliasReg)) {
1638 HasAliasLive = true;
1642 if (!HasAliasLive) {
1643 OmittedAnyCallClobbers = true;
1650 if (FirstOp) FirstOp = false; else OS << ",";
1652 if (i < getDesc().NumOperands) {
1653 const MCOperandInfo &MCOI = getDesc().OpInfo[i];
1654 if (MCOI.isPredicate())
1656 if (MCOI.isOptionalDef())
1659 if (isDebugValue() && MO.isMetadata()) {
1660 // Pretty print DBG_VALUE instructions.
1661 auto *DIV = dyn_cast<DILocalVariable>(MO.getMetadata());
1662 if (DIV && !DIV->getName().empty())
1663 OS << "!\"" << DIV->getName() << '\"';
1665 MO.print(OS, MST, TRI);
1666 } else if (TRI && (isInsertSubreg() || isRegSequence()) && MO.isImm()) {
1667 OS << TRI->getSubRegIndexName(MO.getImm());
1668 } else if (i == AsmDescOp && MO.isImm()) {
1669 // Pretty print the inline asm operand descriptor.
1670 OS << '$' << AsmOpCount++;
1671 unsigned Flag = MO.getImm();
1672 switch (InlineAsm::getKind(Flag)) {
1673 case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
1674 case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
1675 case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
1676 case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
1677 case InlineAsm::Kind_Imm: OS << ":[imm"; break;
1678 case InlineAsm::Kind_Mem: OS << ":[mem"; break;
1679 default: OS << ":[??" << InlineAsm::getKind(Flag); break;
1683 if (InlineAsm::hasRegClassConstraint(Flag, RCID)) {
1685 OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
1687 OS << ":RC" << RCID;
1690 unsigned TiedTo = 0;
1691 if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
1692 OS << " tiedto:$" << TiedTo;
1696 // Compute the index of the next operand descriptor.
1697 AsmDescOp += 1 + InlineAsm::getNumOperandRegisters(Flag);
1699 MO.print(OS, MST, TRI);
1702 // Briefly indicate whether any call clobbers were omitted.
1703 if (OmittedAnyCallClobbers) {
1704 if (!FirstOp) OS << ",";
1708 bool HaveSemi = false;
1709 const unsigned PrintableFlags = FrameSetup;
1710 if (Flags & PrintableFlags) {
1711 if (!HaveSemi) OS << ";"; HaveSemi = true;
1714 if (Flags & FrameSetup)
1718 if (!memoperands_empty()) {
1719 if (!HaveSemi) OS << ";"; HaveSemi = true;
1722 for (mmo_iterator i = memoperands_begin(), e = memoperands_end();
1724 (*i)->print(OS, MST);
1725 if (std::next(i) != e)
1730 // Print the regclass of any virtual registers encountered.
1731 if (MRI && !VirtRegs.empty()) {
1732 if (!HaveSemi) OS << ";"; HaveSemi = true;
1733 for (unsigned i = 0; i != VirtRegs.size(); ++i) {
1734 const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]);
1735 OS << " " << TRI->getRegClassName(RC)
1736 << ':' << PrintReg(VirtRegs[i]);
1737 for (unsigned j = i+1; j != VirtRegs.size();) {
1738 if (MRI->getRegClass(VirtRegs[j]) != RC) {
1742 if (VirtRegs[i] != VirtRegs[j])
1743 OS << "," << PrintReg(VirtRegs[j]);
1744 VirtRegs.erase(VirtRegs.begin()+j);
1749 // Print debug location information.
1750 if (isDebugValue() && getOperand(e - 2).isMetadata()) {
1751 if (!HaveSemi) OS << ";";
1752 auto *DV = cast<DILocalVariable>(getOperand(e - 2).getMetadata());
1753 OS << " line no:" << DV->getLine();
1754 if (auto *InlinedAt = debugLoc->getInlinedAt()) {
1755 DebugLoc InlinedAtDL(InlinedAt);
1756 if (InlinedAtDL && MF) {
1757 OS << " inlined @[ ";
1758 InlinedAtDL.print(OS);
1762 if (isIndirectDebugValue())
1764 } else if (debugLoc && MF) {
1765 if (!HaveSemi) OS << ";";
1773 bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
1774 const TargetRegisterInfo *RegInfo,
1775 bool AddIfNotFound) {
1776 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(IncomingReg);
1777 bool hasAliases = isPhysReg &&
1778 MCRegAliasIterator(IncomingReg, RegInfo, false).isValid();
1780 SmallVector<unsigned,4> DeadOps;
1781 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1782 MachineOperand &MO = getOperand(i);
1783 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1785 unsigned Reg = MO.getReg();
1789 if (Reg == IncomingReg) {
1792 // The register is already marked kill.
1794 if (isPhysReg && isRegTiedToDefOperand(i))
1795 // Two-address uses of physregs must not be marked kill.
1800 } else if (hasAliases && MO.isKill() &&
1801 TargetRegisterInfo::isPhysicalRegister(Reg)) {
1802 // A super-register kill already exists.
1803 if (RegInfo->isSuperRegister(IncomingReg, Reg))
1805 if (RegInfo->isSubRegister(IncomingReg, Reg))
1806 DeadOps.push_back(i);
1810 // Trim unneeded kill operands.
1811 while (!DeadOps.empty()) {
1812 unsigned OpIdx = DeadOps.back();
1813 if (getOperand(OpIdx).isImplicit())
1814 RemoveOperand(OpIdx);
1816 getOperand(OpIdx).setIsKill(false);
1820 // If not found, this means an alias of one of the operands is killed. Add a
1821 // new implicit operand if required.
1822 if (!Found && AddIfNotFound) {
1823 addOperand(MachineOperand::CreateReg(IncomingReg,
1832 void MachineInstr::clearRegisterKills(unsigned Reg,
1833 const TargetRegisterInfo *RegInfo) {
1834 if (!TargetRegisterInfo::isPhysicalRegister(Reg))
1836 for (MachineOperand &MO : operands()) {
1837 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
1839 unsigned OpReg = MO.getReg();
1840 if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg)))
1841 MO.setIsKill(false);
1845 bool MachineInstr::addRegisterDead(unsigned Reg,
1846 const TargetRegisterInfo *RegInfo,
1847 bool AddIfNotFound) {
1848 bool isPhysReg = TargetRegisterInfo::isPhysicalRegister(Reg);
1849 bool hasAliases = isPhysReg &&
1850 MCRegAliasIterator(Reg, RegInfo, false).isValid();
1852 SmallVector<unsigned,4> DeadOps;
1853 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
1854 MachineOperand &MO = getOperand(i);
1855 if (!MO.isReg() || !MO.isDef())
1857 unsigned MOReg = MO.getReg();
1864 } else if (hasAliases && MO.isDead() &&
1865 TargetRegisterInfo::isPhysicalRegister(MOReg)) {
1866 // There exists a super-register that's marked dead.
1867 if (RegInfo->isSuperRegister(Reg, MOReg))
1869 if (RegInfo->isSubRegister(Reg, MOReg))
1870 DeadOps.push_back(i);
1874 // Trim unneeded dead operands.
1875 while (!DeadOps.empty()) {
1876 unsigned OpIdx = DeadOps.back();
1877 if (getOperand(OpIdx).isImplicit())
1878 RemoveOperand(OpIdx);
1880 getOperand(OpIdx).setIsDead(false);
1884 // If not found, this means an alias of one of the operands is dead. Add a
1885 // new implicit operand if required.
1886 if (Found || !AddIfNotFound)
1889 addOperand(MachineOperand::CreateReg(Reg,
1897 void MachineInstr::clearRegisterDeads(unsigned Reg) {
1898 for (MachineOperand &MO : operands()) {
1899 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1901 MO.setIsDead(false);
1905 void MachineInstr::addRegisterDefReadUndef(unsigned Reg) {
1906 for (MachineOperand &MO : operands()) {
1907 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1913 void MachineInstr::addRegisterDefined(unsigned Reg,
1914 const TargetRegisterInfo *RegInfo) {
1915 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
1916 MachineOperand *MO = findRegisterDefOperand(Reg, false, RegInfo);
1920 for (const MachineOperand &MO : operands()) {
1921 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1922 MO.getSubReg() == 0)
1926 addOperand(MachineOperand::CreateReg(Reg,
1931 void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1932 const TargetRegisterInfo &TRI) {
1933 bool HasRegMask = false;
1934 for (MachineOperand &MO : operands()) {
1935 if (MO.isRegMask()) {
1939 if (!MO.isReg() || !MO.isDef()) continue;
1940 unsigned Reg = MO.getReg();
1941 if (!TargetRegisterInfo::isPhysicalRegister(Reg)) continue;
1942 // If there are no uses, including partial uses, the def is dead.
1943 if (std::none_of(UsedRegs.begin(), UsedRegs.end(),
1944 [&](unsigned Use) { return TRI.regsOverlap(Use, Reg); }))
1948 // This is a call with a register mask operand.
1949 // Mask clobbers are always dead, so add defs for the non-dead defines.
1951 for (ArrayRef<unsigned>::iterator I = UsedRegs.begin(), E = UsedRegs.end();
1953 addRegisterDefined(*I, &TRI);
1957 MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
1958 // Build up a buffer of hash code components.
1959 SmallVector<size_t, 8> HashComponents;
1960 HashComponents.reserve(MI->getNumOperands() + 1);
1961 HashComponents.push_back(MI->getOpcode());
1962 for (const MachineOperand &MO : MI->operands()) {
1963 if (MO.isReg() && MO.isDef() &&
1964 TargetRegisterInfo::isVirtualRegister(MO.getReg()))
1965 continue; // Skip virtual register defs.
1967 HashComponents.push_back(hash_value(MO));
1969 return hash_combine_range(HashComponents.begin(), HashComponents.end());
1972 void MachineInstr::emitError(StringRef Msg) const {
1973 // Find the source location cookie.
1974 unsigned LocCookie = 0;
1975 const MDNode *LocMD = nullptr;
1976 for (unsigned i = getNumOperands(); i != 0; --i) {
1977 if (getOperand(i-1).isMetadata() &&
1978 (LocMD = getOperand(i-1).getMetadata()) &&
1979 LocMD->getNumOperands() != 0) {
1980 if (const ConstantInt *CI =
1981 mdconst::dyn_extract<ConstantInt>(LocMD->getOperand(0))) {
1982 LocCookie = CI->getZExtValue();
1988 if (const MachineBasicBlock *MBB = getParent())
1989 if (const MachineFunction *MF = MBB->getParent())
1990 return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg);
1991 report_fatal_error(Msg);