1 //===-- lib/Codegen/MachineRegisterInfo.cpp -------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Implementation of the MachineRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "llvm/CodeGen/MachineRegisterInfo.h"
15 #include "llvm/CodeGen/MachineInstrBuilder.h"
16 #include "llvm/Support/raw_os_ostream.h"
17 #include "llvm/Target/TargetInstrInfo.h"
18 #include "llvm/Target/TargetMachine.h"
19 #include "llvm/Target/TargetSubtargetInfo.h"
23 // Pin the vtable to this file.
24 void MachineRegisterInfo::Delegate::anchor() {}
26 MachineRegisterInfo::MachineRegisterInfo(const MachineFunction *MF)
27 : MF(MF), TheDelegate(nullptr), IsSSA(true), TracksLiveness(true) {
28 VRegInfo.reserve(256);
29 RegAllocHints.reserve(256);
30 UsedRegUnits.resize(getTargetRegisterInfo()->getNumRegUnits());
31 UsedPhysRegMask.resize(getTargetRegisterInfo()->getNumRegs());
33 // Create the physreg use/def lists.
35 new MachineOperand*[getTargetRegisterInfo()->getNumRegs()];
36 memset(PhysRegUseDefLists, 0,
37 sizeof(MachineOperand*)*getTargetRegisterInfo()->getNumRegs());
40 MachineRegisterInfo::~MachineRegisterInfo() {
41 delete [] PhysRegUseDefLists;
44 /// setRegClass - Set the register class of the specified virtual register.
47 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
48 assert(RC && RC->isAllocatable() && "Invalid RC for virtual register");
49 VRegInfo[Reg].first = RC;
52 const TargetRegisterClass *
53 MachineRegisterInfo::constrainRegClass(unsigned Reg,
54 const TargetRegisterClass *RC,
55 unsigned MinNumRegs) {
56 const TargetRegisterClass *OldRC = getRegClass(Reg);
59 const TargetRegisterClass *NewRC =
60 getTargetRegisterInfo()->getCommonSubClass(OldRC, RC);
61 if (!NewRC || NewRC == OldRC)
63 if (NewRC->getNumRegs() < MinNumRegs)
65 setRegClass(Reg, NewRC);
70 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) {
71 const TargetInstrInfo *TII = TM.getSubtargetImpl()->getInstrInfo();
72 const TargetRegisterClass *OldRC = getRegClass(Reg);
73 const TargetRegisterClass *NewRC =
74 getTargetRegisterInfo()->getLargestLegalSuperClass(OldRC);
76 // Stop early if there is no room to grow.
80 // Accumulate constraints from all uses.
81 for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
82 // Apply the effect of the given operand to NewRC.
83 MachineInstr *MI = MO.getParent();
84 unsigned OpNo = &MO - &MI->getOperand(0);
85 NewRC = MI->getRegClassConstraintEffect(OpNo, NewRC, TII,
86 getTargetRegisterInfo());
87 if (!NewRC || NewRC == OldRC)
90 setRegClass(Reg, NewRC);
94 /// createVirtualRegister - Create and return a new virtual register in the
95 /// function with the specified register class.
98 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){
99 assert(RegClass && "Cannot create register without RegClass!");
100 assert(RegClass->isAllocatable() &&
101 "Virtual register RegClass must be allocatable.");
103 // New virtual register number.
104 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs());
106 VRegInfo[Reg].first = RegClass;
107 RegAllocHints.grow(Reg);
109 TheDelegate->MRI_NoteNewVirtualRegister(Reg);
113 /// clearVirtRegs - Remove all virtual registers (after physreg assignment).
114 void MachineRegisterInfo::clearVirtRegs() {
116 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i) {
117 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
118 if (!VRegInfo[Reg].second)
121 llvm_unreachable("Remaining virtual register operands");
127 void MachineRegisterInfo::verifyUseList(unsigned Reg) const {
130 for (MachineOperand &M : reg_operands(Reg)) {
131 MachineOperand *MO = &M;
132 MachineInstr *MI = MO->getParent();
134 errs() << PrintReg(Reg, getTargetRegisterInfo())
135 << " use list MachineOperand " << MO
136 << " has no parent instruction.\n";
139 MachineOperand *MO0 = &MI->getOperand(0);
140 unsigned NumOps = MI->getNumOperands();
141 if (!(MO >= MO0 && MO < MO0+NumOps)) {
142 errs() << PrintReg(Reg, getTargetRegisterInfo())
143 << " use list MachineOperand " << MO
144 << " doesn't belong to parent MI: " << *MI;
148 errs() << PrintReg(Reg, getTargetRegisterInfo())
149 << " MachineOperand " << MO << ": " << *MO
150 << " is not a register\n";
153 if (MO->getReg() != Reg) {
154 errs() << PrintReg(Reg, getTargetRegisterInfo())
155 << " use-list MachineOperand " << MO << ": "
156 << *MO << " is the wrong register\n";
160 assert(Valid && "Invalid use list");
164 void MachineRegisterInfo::verifyUseLists() const {
166 for (unsigned i = 0, e = getNumVirtRegs(); i != e; ++i)
167 verifyUseList(TargetRegisterInfo::index2VirtReg(i));
168 for (unsigned i = 1, e = getTargetRegisterInfo()->getNumRegs(); i != e; ++i)
173 /// Add MO to the linked list of operands for its register.
174 void MachineRegisterInfo::addRegOperandToUseList(MachineOperand *MO) {
175 assert(!MO->isOnRegUseList() && "Already on list");
176 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
177 MachineOperand *const Head = HeadRef;
179 // Head points to the first list element.
180 // Next is NULL on the last list element.
181 // Prev pointers are circular, so Head->Prev == Last.
183 // Head is NULL for an empty list.
185 MO->Contents.Reg.Prev = MO;
186 MO->Contents.Reg.Next = nullptr;
190 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
192 // Insert MO between Last and Head in the circular Prev chain.
193 MachineOperand *Last = Head->Contents.Reg.Prev;
194 assert(Last && "Inconsistent use list");
195 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
196 Head->Contents.Reg.Prev = MO;
197 MO->Contents.Reg.Prev = Last;
199 // Def operands always precede uses. This allows def_iterator to stop early.
200 // Insert def operands at the front, and use operands at the back.
202 // Insert def at the front.
203 MO->Contents.Reg.Next = Head;
206 // Insert use at the end.
207 MO->Contents.Reg.Next = nullptr;
208 Last->Contents.Reg.Next = MO;
212 /// Remove MO from its use-def list.
213 void MachineRegisterInfo::removeRegOperandFromUseList(MachineOperand *MO) {
214 assert(MO->isOnRegUseList() && "Operand not on use list");
215 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
216 MachineOperand *const Head = HeadRef;
217 assert(Head && "List already empty");
219 // Unlink this from the doubly linked list of operands.
220 MachineOperand *Next = MO->Contents.Reg.Next;
221 MachineOperand *Prev = MO->Contents.Reg.Prev;
223 // Prev links are circular, next link is NULL instead of looping back to Head.
227 Prev->Contents.Reg.Next = Next;
229 (Next ? Next : Head)->Contents.Reg.Prev = Prev;
231 MO->Contents.Reg.Prev = nullptr;
232 MO->Contents.Reg.Next = nullptr;
235 /// Move NumOps operands from Src to Dst, updating use-def lists as needed.
237 /// The Dst range is assumed to be uninitialized memory. (Or it may contain
238 /// operands that won't be destroyed, which is OK because the MO destructor is
241 /// The Src and Dst ranges may overlap.
242 void MachineRegisterInfo::moveOperands(MachineOperand *Dst,
245 assert(Src != Dst && NumOps && "Noop moveOperands");
247 // Copy backwards if Dst is within the Src range.
249 if (Dst >= Src && Dst < Src + NumOps) {
255 // Copy one operand at a time.
257 new (Dst) MachineOperand(*Src);
259 // Dst takes Src's place in the use-def chain.
261 MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
262 MachineOperand *Prev = Src->Contents.Reg.Prev;
263 MachineOperand *Next = Src->Contents.Reg.Next;
264 assert(Head && "List empty, but operand is chained");
265 assert(Prev && "Operand was not on use-def list");
267 // Prev links are circular, next link is NULL instead of looping back to
272 Prev->Contents.Reg.Next = Dst;
274 // Update Prev pointer. This also works when Src was pointing to itself
275 // in a 1-element list. In that case Head == Dst.
276 (Next ? Next : Head)->Contents.Reg.Prev = Dst;
284 /// replaceRegWith - Replace all instances of FromReg with ToReg in the
285 /// machine function. This is like llvm-level X->replaceAllUsesWith(Y),
286 /// except that it also changes any definitions of the register as well.
287 /// If ToReg is a physical register we apply the sub register to obtain the
288 /// final/proper physical register.
289 void MachineRegisterInfo::replaceRegWith(unsigned FromReg, unsigned ToReg) {
290 assert(FromReg != ToReg && "Cannot replace a reg with itself");
292 const TargetRegisterInfo *TRI = getTargetRegisterInfo();
294 // TODO: This could be more efficient by bulk changing the operands.
295 for (reg_iterator I = reg_begin(FromReg), E = reg_end(); I != E; ) {
296 MachineOperand &O = *I;
298 if (TargetRegisterInfo::isPhysicalRegister(ToReg)) {
299 O.substPhysReg(ToReg, *TRI);
306 /// getVRegDef - Return the machine instr that defines the specified virtual
307 /// register or null if none is found. This assumes that the code is in SSA
308 /// form, so there should only be one definition.
309 MachineInstr *MachineRegisterInfo::getVRegDef(unsigned Reg) const {
310 // Since we are in SSA form, we can use the first definition.
311 def_instr_iterator I = def_instr_begin(Reg);
312 assert((I.atEnd() || std::next(I) == def_instr_end()) &&
313 "getVRegDef assumes a single definition or no definition");
314 return !I.atEnd() ? &*I : nullptr;
317 /// getUniqueVRegDef - Return the unique machine instr that defines the
318 /// specified virtual register or null if none is found. If there are
319 /// multiple definitions or no definition, return null.
320 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(unsigned Reg) const {
321 if (def_empty(Reg)) return nullptr;
322 def_instr_iterator I = def_instr_begin(Reg);
323 if (std::next(I) != def_instr_end())
328 bool MachineRegisterInfo::hasOneNonDBGUse(unsigned RegNo) const {
329 use_nodbg_iterator UI = use_nodbg_begin(RegNo);
330 if (UI == use_nodbg_end())
332 return ++UI == use_nodbg_end();
335 /// clearKillFlags - Iterate over all the uses of the given register and
336 /// clear the kill flag from the MachineOperand. This function is used by
337 /// optimization passes which extend register lifetimes and need only
338 /// preserve conservative kill flag information.
339 void MachineRegisterInfo::clearKillFlags(unsigned Reg) const {
340 for (MachineOperand &MO : use_operands(Reg))
344 bool MachineRegisterInfo::isLiveIn(unsigned Reg) const {
345 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
346 if (I->first == Reg || I->second == Reg)
351 /// getLiveInPhysReg - If VReg is a live-in virtual register, return the
352 /// corresponding live-in physical register.
353 unsigned MachineRegisterInfo::getLiveInPhysReg(unsigned VReg) const {
354 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
355 if (I->second == VReg)
360 /// getLiveInVirtReg - If PReg is a live-in physical register, return the
361 /// corresponding live-in physical register.
362 unsigned MachineRegisterInfo::getLiveInVirtReg(unsigned PReg) const {
363 for (livein_iterator I = livein_begin(), E = livein_end(); I != E; ++I)
364 if (I->first == PReg)
369 /// EmitLiveInCopies - Emit copies to initialize livein virtual registers
370 /// into the given entry block.
372 MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
373 const TargetRegisterInfo &TRI,
374 const TargetInstrInfo &TII) {
375 // Emit the copies into the top of the block.
376 for (unsigned i = 0, e = LiveIns.size(); i != e; ++i)
377 if (LiveIns[i].second) {
378 if (use_empty(LiveIns[i].second)) {
379 // The livein has no uses. Drop it.
381 // It would be preferable to have isel avoid creating live-in
382 // records for unused arguments in the first place, but it's
383 // complicated by the debug info code for arguments.
384 LiveIns.erase(LiveIns.begin() + i);
388 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
389 TII.get(TargetOpcode::COPY), LiveIns[i].second)
390 .addReg(LiveIns[i].first);
392 // Add the register to the entry block live-in set.
393 EntryMBB->addLiveIn(LiveIns[i].first);
396 // Add the register to the entry block live-in set.
397 EntryMBB->addLiveIn(LiveIns[i].first);
402 void MachineRegisterInfo::dumpUses(unsigned Reg) const {
403 for (MachineInstr &I : use_instructions(Reg))
408 void MachineRegisterInfo::freezeReservedRegs(const MachineFunction &MF) {
409 ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
410 assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
411 "Invalid ReservedRegs vector from target");
414 bool MachineRegisterInfo::isConstantPhysReg(unsigned PhysReg,
415 const MachineFunction &MF) const {
416 assert(TargetRegisterInfo::isPhysicalRegister(PhysReg));
418 // Check if any overlapping register is modified, or allocatable so it may be
420 for (MCRegAliasIterator AI(PhysReg, getTargetRegisterInfo(), true);
422 if (!def_empty(*AI) || isAllocatable(*AI))
427 /// markUsesInDebugValueAsUndef - Mark every DBG_VALUE referencing the
428 /// specified register as undefined which causes the DBG_VALUE to be
429 /// deleted during LiveDebugVariables analysis.
430 void MachineRegisterInfo::markUsesInDebugValueAsUndef(unsigned Reg) const {
431 // Mark any DBG_VALUE that uses Reg as undef (but don't delete it.)
432 MachineRegisterInfo::use_instr_iterator nextI;
433 for (use_instr_iterator I = use_instr_begin(Reg), E = use_instr_end();
435 nextI = std::next(I); // I is invalidated by the setReg
436 MachineInstr *UseMI = &*I;
437 if (UseMI->isDebugValue())
438 UseMI->getOperand(0).setReg(0U);