1 //===-- Passes.cpp - Target independent code generation passes ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines interfaces to access the target independent code
11 // generation passes provided by the LLVM backend.
13 //===---------------------------------------------------------------------===//
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/Analysis/Passes.h"
17 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/RegAllocRegistry.h"
19 #include "llvm/IR/IRPrintingPasses.h"
20 #include "llvm/IR/LegacyPassManager.h"
21 #include "llvm/IR/Verifier.h"
22 #include "llvm/MC/MCAsmInfo.h"
23 #include "llvm/Support/CommandLine.h"
24 #include "llvm/Support/Debug.h"
25 #include "llvm/Support/ErrorHandling.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Transforms/Instrumentation.h"
28 #include "llvm/Transforms/Scalar.h"
29 #include "llvm/Transforms/Utils/SymbolRewriter.h"
33 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden,
34 cl::desc("Disable Post Regalloc"));
35 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden,
36 cl::desc("Disable branch folding"));
37 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden,
38 cl::desc("Disable tail duplication"));
39 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden,
40 cl::desc("Disable pre-register allocation tail duplication"));
41 static cl::opt<bool> DisableBlockPlacement("disable-block-placement",
42 cl::Hidden, cl::desc("Disable probability-driven block placement"));
43 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats",
44 cl::Hidden, cl::desc("Collect probability-driven block placement stats"));
45 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden,
46 cl::desc("Disable Stack Slot Coloring"));
47 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden,
48 cl::desc("Disable Machine Dead Code Elimination"));
49 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden,
50 cl::desc("Disable Early If-conversion"));
51 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden,
52 cl::desc("Disable Machine LICM"));
53 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden,
54 cl::desc("Disable Machine Common Subexpression Elimination"));
55 static cl::opt<cl::boolOrDefault>
56 EnableShrinkWrapOpt("enable-shrink-wrap", cl::Hidden,
57 cl::desc("enable the shrink-wrapping pass"));
58 static cl::opt<cl::boolOrDefault> OptimizeRegAlloc(
59 "optimize-regalloc", cl::Hidden,
60 cl::desc("Enable optimized register allocation compilation path."));
61 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm",
63 cl::desc("Disable Machine LICM"));
64 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden,
65 cl::desc("Disable Machine Sinking"));
66 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden,
67 cl::desc("Disable Loop Strength Reduction Pass"));
68 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting",
69 cl::Hidden, cl::desc("Disable ConstantHoisting"));
70 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden,
71 cl::desc("Disable Codegen Prepare"));
72 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden,
73 cl::desc("Disable Copy Propagation pass"));
74 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining",
75 cl::Hidden, cl::desc("Disable Partial Libcall Inlining"));
76 static cl::opt<bool> EnableImplicitNullChecks(
77 "enable-implicit-null-checks",
78 cl::desc("Fold null checks into faulting memory operations"),
80 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden,
81 cl::desc("Print LLVM IR produced by the loop-reduce pass"));
82 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden,
83 cl::desc("Print LLVM IR input to isel pass"));
84 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden,
85 cl::desc("Dump garbage collector data"));
86 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden,
87 cl::desc("Verify generated machine code"),
91 static cl::opt<std::string>
92 PrintMachineInstrs("print-machineinstrs", cl::ValueOptional,
93 cl::desc("Print machine instrs"),
94 cl::value_desc("pass-name"), cl::init("option-unspecified"));
96 // Temporary option to allow experimenting with MachineScheduler as a post-RA
97 // scheduler. Targets can "properly" enable this with
98 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID); Ideally it
99 // wouldn't be part of the standard pass pipeline, and the target would just add
100 // a PostRA scheduling pass wherever it wants.
101 static cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden,
102 cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)"));
104 // Experimental option to run live interval analysis early.
105 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden,
106 cl::desc("Run live interval analysis earlier in the pipeline"));
108 static cl::opt<bool> UseCFLAA("use-cfl-aa-in-codegen",
109 cl::init(false), cl::Hidden,
110 cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"));
112 /// Allow standard passes to be disabled by command line options. This supports
113 /// simple binary flags that either suppress the pass or do nothing.
114 /// i.e. -disable-mypass=false has no effect.
115 /// These should be converted to boolOrDefault in order to use applyOverride.
116 static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID,
119 return IdentifyingPassPtr();
123 /// Allow standard passes to be disabled by the command line, regardless of who
124 /// is adding the pass.
126 /// StandardID is the pass identified in the standard pass pipeline and provided
127 /// to addPass(). It may be a target-specific ID in the case that the target
128 /// directly adds its own pass, but in that case we harmlessly fall through.
130 /// TargetID is the pass that the target has configured to override StandardID.
132 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real
133 /// pass to run. This allows multiple options to control a single pass depending
134 /// on where in the pipeline that pass is added.
135 static IdentifyingPassPtr overridePass(AnalysisID StandardID,
136 IdentifyingPassPtr TargetID) {
137 if (StandardID == &PostRASchedulerID)
138 return applyDisable(TargetID, DisablePostRA);
140 if (StandardID == &BranchFolderPassID)
141 return applyDisable(TargetID, DisableBranchFold);
143 if (StandardID == &TailDuplicateID)
144 return applyDisable(TargetID, DisableTailDuplicate);
146 if (StandardID == &TargetPassConfig::EarlyTailDuplicateID)
147 return applyDisable(TargetID, DisableEarlyTailDup);
149 if (StandardID == &MachineBlockPlacementID)
150 return applyDisable(TargetID, DisableBlockPlacement);
152 if (StandardID == &StackSlotColoringID)
153 return applyDisable(TargetID, DisableSSC);
155 if (StandardID == &DeadMachineInstructionElimID)
156 return applyDisable(TargetID, DisableMachineDCE);
158 if (StandardID == &EarlyIfConverterID)
159 return applyDisable(TargetID, DisableEarlyIfConversion);
161 if (StandardID == &MachineLICMID)
162 return applyDisable(TargetID, DisableMachineLICM);
164 if (StandardID == &MachineCSEID)
165 return applyDisable(TargetID, DisableMachineCSE);
167 if (StandardID == &TargetPassConfig::PostRAMachineLICMID)
168 return applyDisable(TargetID, DisablePostRAMachineLICM);
170 if (StandardID == &MachineSinkingID)
171 return applyDisable(TargetID, DisableMachineSink);
173 if (StandardID == &MachineCopyPropagationID)
174 return applyDisable(TargetID, DisableCopyProp);
179 //===---------------------------------------------------------------------===//
181 //===---------------------------------------------------------------------===//
183 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig",
184 "Target Pass Configuration", false, false)
185 char TargetPassConfig::ID = 0;
188 char TargetPassConfig::EarlyTailDuplicateID = 0;
189 char TargetPassConfig::PostRAMachineLICMID = 0;
192 class PassConfigImpl {
194 // List of passes explicitly substituted by this target. Normally this is
195 // empty, but it is a convenient way to suppress or replace specific passes
196 // that are part of a standard pass pipeline without overridding the entire
197 // pipeline. This mechanism allows target options to inherit a standard pass's
198 // user interface. For example, a target may disable a standard pass by
199 // default by substituting a pass ID of zero, and the user may still enable
200 // that standard pass with an explicit command line option.
201 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses;
203 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass
204 /// is inserted after each instance of the first one.
205 SmallVector<std::pair<AnalysisID, IdentifyingPassPtr>, 4> InsertedPasses;
209 // Out of line virtual method.
210 TargetPassConfig::~TargetPassConfig() {
214 // Out of line constructor provides default values for pass options and
215 // registers all common codegen passes.
216 TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm)
217 : ImmutablePass(ID), PM(&pm), StartBefore(nullptr), StartAfter(nullptr),
218 StopAfter(nullptr), Started(true), Stopped(false),
219 AddingMachinePasses(false), TM(tm), Impl(nullptr), Initialized(false),
220 DisableVerify(false), EnableTailMerge(true), EnableShrinkWrap(false) {
222 Impl = new PassConfigImpl();
224 // Register all target independent codegen passes to activate their PassIDs,
225 // including this pass itself.
226 initializeCodeGen(*PassRegistry::getPassRegistry());
228 // Substitute Pseudo Pass IDs for real ones.
229 substitutePass(&EarlyTailDuplicateID, &TailDuplicateID);
230 substitutePass(&PostRAMachineLICMID, &MachineLICMID);
233 /// Insert InsertedPassID pass after TargetPassID.
234 void TargetPassConfig::insertPass(AnalysisID TargetPassID,
235 IdentifyingPassPtr InsertedPassID) {
236 assert(((!InsertedPassID.isInstance() &&
237 TargetPassID != InsertedPassID.getID()) ||
238 (InsertedPassID.isInstance() &&
239 TargetPassID != InsertedPassID.getInstance()->getPassID())) &&
240 "Insert a pass after itself!");
241 std::pair<AnalysisID, IdentifyingPassPtr> P(TargetPassID, InsertedPassID);
242 Impl->InsertedPasses.push_back(P);
245 /// createPassConfig - Create a pass configuration object to be used by
246 /// addPassToEmitX methods for generating a pipeline of CodeGen passes.
248 /// Targets may override this to extend TargetPassConfig.
249 TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) {
250 return new TargetPassConfig(this, PM);
253 TargetPassConfig::TargetPassConfig()
254 : ImmutablePass(ID), PM(nullptr) {
255 llvm_unreachable("TargetPassConfig should not be constructed on-the-fly");
258 // Helper to verify the analysis is really immutable.
259 void TargetPassConfig::setOpt(bool &Opt, bool Val) {
260 assert(!Initialized && "PassConfig is immutable");
264 void TargetPassConfig::substitutePass(AnalysisID StandardID,
265 IdentifyingPassPtr TargetID) {
266 Impl->TargetPasses[StandardID] = TargetID;
269 IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const {
270 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator
271 I = Impl->TargetPasses.find(ID);
272 if (I == Impl->TargetPasses.end())
277 /// Add a pass to the PassManager if that pass is supposed to be run. If the
278 /// Started/Stopped flags indicate either that the compilation should start at
279 /// a later pass or that it should stop after an earlier pass, then do not add
280 /// the pass. Finally, compare the current pass against the StartAfter
281 /// and StopAfter options and change the Started/Stopped flags accordingly.
282 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) {
283 assert(!Initialized && "PassConfig is immutable");
285 // Cache the Pass ID here in case the pass manager finds this pass is
286 // redundant with ones already scheduled / available, and deletes it.
287 // Fundamentally, once we add the pass to the manager, we no longer own it
288 // and shouldn't reference it.
289 AnalysisID PassID = P->getPassID();
291 if (StartBefore == PassID)
293 if (Started && !Stopped) {
295 // Construct banner message before PM->add() as that may delete the pass.
296 if (AddingMachinePasses && (printAfter || verifyAfter))
297 Banner = std::string("After ") + std::string(P->getPassName());
299 if (AddingMachinePasses) {
301 addPrintPass(Banner);
303 addVerifyPass(Banner);
306 // Add the passes after the pass P if there is any.
307 for (SmallVectorImpl<std::pair<AnalysisID, IdentifyingPassPtr> >::iterator
308 I = Impl->InsertedPasses.begin(),
309 E = Impl->InsertedPasses.end();
311 if ((*I).first == PassID) {
312 assert((*I).second.isValid() && "Illegal Pass ID!");
314 if ((*I).second.isInstance())
315 NP = (*I).second.getInstance();
317 NP = Pass::createPass((*I).second.getID());
318 assert(NP && "Pass ID not registered");
320 addPass(NP, false, false);
326 if (StopAfter == PassID)
328 if (StartAfter == PassID)
330 if (Stopped && !Started)
331 report_fatal_error("Cannot stop compilation after pass that is not run");
334 /// Add a CodeGen pass at this point in the pipeline after checking for target
335 /// and command line overrides.
337 /// addPass cannot return a pointer to the pass instance because is internal the
338 /// PassManager and the instance we create here may already be freed.
339 AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter,
341 IdentifyingPassPtr TargetID = getPassSubstitution(PassID);
342 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID);
343 if (!FinalPtr.isValid())
347 if (FinalPtr.isInstance())
348 P = FinalPtr.getInstance();
350 P = Pass::createPass(FinalPtr.getID());
352 llvm_unreachable("Pass ID not registered");
354 AnalysisID FinalID = P->getPassID();
355 addPass(P, verifyAfter, printAfter); // Ends the lifetime of P.
360 void TargetPassConfig::printAndVerify(const std::string &Banner) {
361 addPrintPass(Banner);
362 addVerifyPass(Banner);
365 void TargetPassConfig::addPrintPass(const std::string &Banner) {
366 if (TM->shouldPrintMachineCode())
367 PM->add(createMachineFunctionPrinterPass(dbgs(), Banner));
370 void TargetPassConfig::addVerifyPass(const std::string &Banner) {
371 if (VerifyMachineCode)
372 PM->add(createMachineVerifierPass(Banner));
375 /// Add common target configurable passes that perform LLVM IR to IR transforms
376 /// following machine independent optimization.
377 void TargetPassConfig::addIRPasses() {
378 // Basic AliasAnalysis support.
379 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that
380 // BasicAliasAnalysis wins if they disagree. This is intended to help
381 // support "obvious" type-punning idioms.
383 addPass(createCFLAliasAnalysisPass());
384 addPass(createTypeBasedAliasAnalysisPass());
385 addPass(createScopedNoAliasAAPass());
386 addPass(createBasicAliasAnalysisPass());
388 // Before running any passes, run the verifier to determine if the input
389 // coming from the front-end and/or optimizer is valid.
391 addPass(createVerifierPass());
393 // Run loop strength reduction before anything else.
394 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) {
395 addPass(createLoopStrengthReducePass());
397 addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n"));
400 // Run GC lowering passes for builtin collectors
401 // TODO: add a pass insertion point here
402 addPass(createGCLoweringPass());
403 addPass(createShadowStackGCLoweringPass());
405 // Make sure that no unreachable blocks are instruction selected.
406 addPass(createUnreachableBlockEliminationPass());
408 // Prepare expensive constants for SelectionDAG.
409 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting)
410 addPass(createConstantHoistingPass());
412 if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining)
413 addPass(createPartiallyInlineLibCallsPass());
416 /// Turn exception handling constructs into something the code generators can
418 void TargetPassConfig::addPassesToHandleExceptions() {
419 switch (TM->getMCAsmInfo()->getExceptionHandlingType()) {
420 case ExceptionHandling::SjLj:
421 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both
422 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise,
423 // catch info can get misplaced when a selector ends up more than one block
424 // removed from the parent invoke(s). This could happen when a landing
425 // pad is shared by multiple invokes and is also a target of a normal
426 // edge from elsewhere.
427 addPass(createSjLjEHPreparePass());
429 case ExceptionHandling::DwarfCFI:
430 case ExceptionHandling::ARM:
431 addPass(createDwarfEHPass(TM));
433 case ExceptionHandling::WinEH:
434 // We support using both GCC-style and MSVC-style exceptions on Windows, so
435 // add both preparation passes. Each pass will only actually run if it
436 // recognizes the personality function.
437 addPass(createWinEHPass(TM));
438 addPass(createDwarfEHPass(TM));
440 case ExceptionHandling::None:
441 addPass(createLowerInvokePass());
443 // The lower invoke pass may create unreachable code. Remove it.
444 addPass(createUnreachableBlockEliminationPass());
449 /// Add pass to prepare the LLVM IR for code generation. This should be done
450 /// before exception handling preparation passes.
451 void TargetPassConfig::addCodeGenPrepare() {
452 if (getOptLevel() != CodeGenOpt::None && !DisableCGP)
453 addPass(createCodeGenPreparePass(TM));
454 addPass(createRewriteSymbolsPass());
457 /// Add common passes that perform LLVM IR to IR transforms in preparation for
458 /// instruction selection.
459 void TargetPassConfig::addISelPrepare() {
462 // Add both the safe stack and the stack protection passes: each of them will
463 // only protect functions that have corresponding attributes.
464 addPass(createSafeStackPass());
465 addPass(createStackProtectorPass(TM));
468 addPass(createPrintFunctionPass(
469 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n"));
471 // All passes which modify the LLVM IR are now complete; run the verifier
472 // to ensure that the IR is valid.
474 addPass(createVerifierPass());
477 /// Add the complete set of target-independent postISel code generator passes.
479 /// This can be read as the standard order of major LLVM CodeGen stages. Stages
480 /// with nontrivial configuration or multiple passes are broken out below in
481 /// add%Stage routines.
483 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The
484 /// addPre/Post methods with empty header implementations allow injecting
485 /// target-specific fixups just before or after major stages. Additionally,
486 /// targets have the flexibility to change pass order within a stage by
487 /// overriding default implementation of add%Stage routines below. Each
488 /// technique has maintainability tradeoffs because alternate pass orders are
489 /// not well supported. addPre/Post works better if the target pass is easily
490 /// tied to a common pass. But if it has subtle dependencies on multiple passes,
491 /// the target should override the stage instead.
493 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection
494 /// before/after any target-independent pass. But it's currently overkill.
495 void TargetPassConfig::addMachinePasses() {
496 AddingMachinePasses = true;
498 // Insert a machine instr printer pass after the specified pass.
499 // If -print-machineinstrs specified, print machineinstrs after all passes.
500 if (StringRef(PrintMachineInstrs.getValue()).equals(""))
501 TM->Options.PrintMachineCode = true;
502 else if (!StringRef(PrintMachineInstrs.getValue())
503 .equals("option-unspecified")) {
504 const PassRegistry *PR = PassRegistry::getPassRegistry();
505 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue());
506 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer"));
507 assert (TPI && IPI && "Pass ID not registered!");
508 const char *TID = (const char *)(TPI->getTypeInfo());
509 const char *IID = (const char *)(IPI->getTypeInfo());
510 insertPass(TID, IID);
513 // Print the instruction selected machine code...
514 printAndVerify("After Instruction Selection");
516 // Expand pseudo-instructions emitted by ISel.
517 addPass(&ExpandISelPseudosID);
519 // Add passes that optimize machine instructions in SSA form.
520 if (getOptLevel() != CodeGenOpt::None) {
521 addMachineSSAOptimization();
523 // If the target requests it, assign local variables to stack slots relative
524 // to one another and simplify frame index references where possible.
525 addPass(&LocalStackSlotAllocationID, false);
528 // Run pre-ra passes.
531 // Run register allocation and passes that are tightly coupled with it,
532 // including phi elimination and scheduling.
533 if (getOptimizeRegAlloc())
534 addOptimizedRegAlloc(createRegAllocPass(true));
536 addFastRegAlloc(createRegAllocPass(false));
538 // Run post-ra passes.
541 // Insert prolog/epilog code. Eliminate abstract frame index references...
542 if (getEnableShrinkWrap())
543 addPass(&ShrinkWrapID);
544 addPass(&PrologEpilogCodeInserterID);
546 /// Add passes that optimize machine instructions after register allocation.
547 if (getOptLevel() != CodeGenOpt::None)
548 addMachineLateOptimization();
550 // Expand pseudo instructions before second scheduling pass.
551 addPass(&ExpandPostRAPseudosID);
553 // Run pre-sched2 passes.
556 if (EnableImplicitNullChecks)
557 addPass(&ImplicitNullChecksID);
559 // Second pass scheduler.
560 if (getOptLevel() != CodeGenOpt::None) {
562 addPass(&PostMachineSchedulerID);
564 addPass(&PostRASchedulerID);
570 addPass(createGCInfoPrinter(dbgs()), false, false);
573 // Basic block placement.
574 if (getOptLevel() != CodeGenOpt::None)
579 addPass(&StackMapLivenessID, false);
581 AddingMachinePasses = false;
584 /// Add passes that optimize machine instructions in SSA form.
585 void TargetPassConfig::addMachineSSAOptimization() {
586 // Pre-ra tail duplication.
587 addPass(&EarlyTailDuplicateID);
589 // Optimize PHIs before DCE: removing dead PHI cycles may make more
590 // instructions dead.
591 addPass(&OptimizePHIsID, false);
593 // This pass merges large allocas. StackSlotColoring is a different pass
594 // which merges spill slots.
595 addPass(&StackColoringID, false);
597 // If the target requests it, assign local variables to stack slots relative
598 // to one another and simplify frame index references where possible.
599 addPass(&LocalStackSlotAllocationID, false);
601 // With optimization, dead code should already be eliminated. However
602 // there is one known exception: lowered code for arguments that are only
603 // used by tail calls, where the tail calls reuse the incoming stack
604 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
605 addPass(&DeadMachineInstructionElimID);
607 // Allow targets to insert passes that improve instruction level parallelism,
608 // like if-conversion. Such passes will typically need dominator trees and
609 // loop info, just like LICM and CSE below.
612 addPass(&MachineLICMID, false);
613 addPass(&MachineCSEID, false);
614 addPass(&MachineSinkingID);
616 addPass(&PeepholeOptimizerID, false);
617 // Clean-up the dead code that may have been generated by peephole
619 addPass(&DeadMachineInstructionElimID);
622 bool TargetPassConfig::getEnableShrinkWrap() const {
623 switch (EnableShrinkWrapOpt) {
625 return EnableShrinkWrap && getOptLevel() != CodeGenOpt::None;
626 // If EnableShrinkWrap is set, it takes precedence on whatever the
627 // target sets. The rational is that we assume we want to test
628 // something related to shrink-wrapping.
634 llvm_unreachable("Invalid shrink-wrapping state");
637 //===---------------------------------------------------------------------===//
638 /// Register Allocation Pass Configuration
639 //===---------------------------------------------------------------------===//
641 bool TargetPassConfig::getOptimizeRegAlloc() const {
642 switch (OptimizeRegAlloc) {
643 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None;
644 case cl::BOU_TRUE: return true;
645 case cl::BOU_FALSE: return false;
647 llvm_unreachable("Invalid optimize-regalloc state");
650 /// RegisterRegAlloc's global Registry tracks allocator registration.
651 MachinePassRegistry RegisterRegAlloc::Registry;
653 /// A dummy default pass factory indicates whether the register allocator is
654 /// overridden on the command line.
655 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; }
656 static RegisterRegAlloc
657 defaultRegAlloc("default",
658 "pick register allocator based on -O option",
659 useDefaultRegisterAllocator);
661 /// -regalloc=... command line option.
662 static cl::opt<RegisterRegAlloc::FunctionPassCtor, false,
663 RegisterPassParser<RegisterRegAlloc> >
665 cl::init(&useDefaultRegisterAllocator),
666 cl::desc("Register allocator to use"));
669 /// Instantiate the default register allocator pass for this target for either
670 /// the optimized or unoptimized allocation path. This will be added to the pass
671 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc
672 /// in the optimized case.
674 /// A target that uses the standard regalloc pass order for fast or optimized
675 /// allocation may still override this for per-target regalloc
676 /// selection. But -regalloc=... always takes precedence.
677 FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) {
679 return createGreedyRegisterAllocator();
681 return createFastRegisterAllocator();
684 /// Find and instantiate the register allocation pass requested by this target
685 /// at the current optimization level. Different register allocators are
686 /// defined as separate passes because they may require different analysis.
688 /// This helper ensures that the regalloc= option is always available,
689 /// even for targets that override the default allocator.
691 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs,
692 /// this can be folded into addPass.
693 FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) {
694 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault();
696 // Initialize the global default.
699 RegisterRegAlloc::setDefault(RegAlloc);
701 if (Ctor != useDefaultRegisterAllocator)
704 // With no -regalloc= override, ask the target for a regalloc pass.
705 return createTargetRegisterAllocator(Optimized);
708 /// Return true if the default global register allocator is in use and
709 /// has not be overriden on the command line with '-regalloc=...'
710 bool TargetPassConfig::usingDefaultRegAlloc() const {
711 return RegAlloc.getNumOccurrences() == 0;
714 /// Add the minimum set of target-independent passes that are required for
715 /// register allocation. No coalescing or scheduling.
716 void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
717 addPass(&PHIEliminationID, false);
718 addPass(&TwoAddressInstructionPassID, false);
720 addPass(RegAllocPass);
723 /// Add standard target-independent passes that are tightly coupled with
724 /// optimized register allocation, including coalescing, machine instruction
725 /// scheduling, and register allocation itself.
726 void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
727 addPass(&ProcessImplicitDefsID, false);
729 // LiveVariables currently requires pure SSA form.
731 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags,
732 // LiveVariables can be removed completely, and LiveIntervals can be directly
733 // computed. (We still either need to regenerate kill flags after regalloc, or
734 // preferably fix the scavenger to not depend on them).
735 addPass(&LiveVariablesID, false);
737 // Edge splitting is smarter with machine loop info.
738 addPass(&MachineLoopInfoID, false);
739 addPass(&PHIEliminationID, false);
741 // Eventually, we want to run LiveIntervals before PHI elimination.
742 if (EarlyLiveIntervals)
743 addPass(&LiveIntervalsID, false);
745 addPass(&TwoAddressInstructionPassID, false);
746 addPass(&RegisterCoalescerID);
748 // PreRA instruction scheduling.
749 addPass(&MachineSchedulerID);
751 // Add the selected register allocation pass.
752 addPass(RegAllocPass);
754 // Allow targets to change the register assignments before rewriting.
757 // Finally rewrite virtual registers.
758 addPass(&VirtRegRewriterID);
760 // Perform stack slot coloring and post-ra machine LICM.
762 // FIXME: Re-enable coloring with register when it's capable of adding
764 addPass(&StackSlotColoringID);
766 // Run post-ra machine LICM to hoist reloads / remats.
768 // FIXME: can this move into MachineLateOptimization?
769 addPass(&PostRAMachineLICMID);
772 //===---------------------------------------------------------------------===//
773 /// Post RegAlloc Pass Configuration
774 //===---------------------------------------------------------------------===//
776 /// Add passes that optimize machine instructions after register allocation.
777 void TargetPassConfig::addMachineLateOptimization() {
778 // Branch folding must be run after regalloc and prolog/epilog insertion.
779 addPass(&BranchFolderPassID);
782 // Note that duplicating tail just increases code size and degrades
783 // performance for targets that require Structured Control Flow.
784 // In addition it can also make CFG irreducible. Thus we disable it.
785 if (!TM->requiresStructuredCFG())
786 addPass(&TailDuplicateID);
789 addPass(&MachineCopyPropagationID);
792 /// Add standard GC passes.
793 bool TargetPassConfig::addGCPasses() {
794 addPass(&GCMachineCodeAnalysisID, false);
798 /// Add standard basic block placement passes.
799 void TargetPassConfig::addBlockPlacement() {
800 if (addPass(&MachineBlockPlacementID, false)) {
801 // Run a separate pass to collect block placement statistics.
802 if (EnableBlockPlacementStats)
803 addPass(&MachineBlockPlacementStatsID);