1 //===-- XCoreInstrInfo.h - XCore Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H
15 #define LLVM_LIB_TARGET_XCORE_XCOREINSTRINFO_H
17 #include "XCoreRegisterInfo.h"
18 #include "llvm/Target/TargetInstrInfo.h"
20 #define GET_INSTRINFO_HEADER
21 #include "XCoreGenInstrInfo.inc"
25 class XCoreInstrInfo : public XCoreGenInstrInfo {
26 const XCoreRegisterInfo RI;
27 virtual void anchor();
31 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
32 /// such, whenever a client has an instance of instruction info, it should
33 /// always be able to get register info as well (through this method).
35 const TargetRegisterInfo &getRegisterInfo() const { return RI; }
37 /// isLoadFromStackSlot - If the specified machine instruction is a direct
38 /// load from a stack slot, return the virtual or physical register number of
39 /// the destination along with the FrameIndex of the loaded stack slot. If
40 /// not, return 0. This predicate must return 0 if the instruction has
41 /// any side effects other than loading from the stack slot.
42 unsigned isLoadFromStackSlot(const MachineInstr *MI,
43 int &FrameIndex) const override;
45 /// isStoreToStackSlot - If the specified machine instruction is a direct
46 /// store to a stack slot, return the virtual or physical register number of
47 /// the source reg along with the FrameIndex of the loaded stack slot. If
48 /// not, return 0. This predicate must return 0 if the instruction has
49 /// any side effects other than storing to the stack slot.
50 unsigned isStoreToStackSlot(const MachineInstr *MI,
51 int &FrameIndex) const override;
53 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
54 MachineBasicBlock *&FBB,
55 SmallVectorImpl<MachineOperand> &Cond,
56 bool AllowModify) const override;
58 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
59 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
60 DebugLoc DL) const override;
62 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
64 void copyPhysReg(MachineBasicBlock &MBB,
65 MachineBasicBlock::iterator I, DebugLoc DL,
66 unsigned DestReg, unsigned SrcReg,
67 bool KillSrc) const override;
69 void storeRegToStackSlot(MachineBasicBlock &MBB,
70 MachineBasicBlock::iterator MI,
71 unsigned SrcReg, bool isKill, int FrameIndex,
72 const TargetRegisterClass *RC,
73 const TargetRegisterInfo *TRI) const override;
75 void loadRegFromStackSlot(MachineBasicBlock &MBB,
76 MachineBasicBlock::iterator MI,
77 unsigned DestReg, int FrameIndex,
78 const TargetRegisterClass *RC,
79 const TargetRegisterInfo *TRI) const override;
81 bool ReverseBranchCondition(
82 SmallVectorImpl<MachineOperand> &Cond) const override;
84 // Emit code before MBBI to load immediate value into physical register Reg.
85 // Returns an iterator to the new instruction.
86 MachineBasicBlock::iterator loadImmediate(MachineBasicBlock &MBB,
87 MachineBasicBlock::iterator MI,
88 unsigned Reg, uint64_t Value) const;