2 * linux/arch/alpha/kernel/time.c
4 * Copyright (C) 1991, 1992, 1995, 1999, 2000 Linus Torvalds
6 * This file contains the PC-specific time handling details:
7 * reading the RTC at bootup, etc..
8 * 1994-07-02 Alan Modra
9 * fixed set_rtc_mmss, fixed time.year for >= 2000, new mktime
10 * 1995-03-26 Markus Kuhn
11 * fixed 500 ms bug at call to set_rtc_mmss, fixed DS12887
12 * precision CMOS clock update
13 * 1997-09-10 Updated NTP code according to technical memorandum Jan '96
14 * "A Kernel Model for Precision Timekeeping" by Dave Mills
15 * 1997-01-09 Adrian Sun
16 * use interval timer if CONFIG_RTC=y
17 * 1997-10-29 John Bowman (bowman@math.ualberta.ca)
18 * fixed tick loss calculation in timer_interrupt
19 * (round system clock to nearest tick instead of truncating)
20 * fixed algorithm in time_init for getting time from CMOS clock
21 * 1999-04-16 Thorsten Kranzkowski (dl8bcu@gmx.net)
22 * fixed algorithm in do_gettimeofday() for calculating the precise time
23 * from processor cycle counter (now taking lost_ticks into account)
24 * 2000-08-13 Jan-Benedict Glaw <jbglaw@lug-owl.de>
25 * Fixed time_init to be aware of epoches != 1900. This prevents
26 * booting up in 2048 for me;) Code is stolen from rtc.c.
27 * 2003-06-03 R. Scott Bailey <scott.bailey@eds.com>
28 * Tighten sanity in time_init from 1% (10,000 PPM) to 250 PPM
30 #include <linux/errno.h>
31 #include <linux/module.h>
32 #include <linux/sched.h>
33 #include <linux/kernel.h>
34 #include <linux/param.h>
35 #include <linux/string.h>
37 #include <linux/delay.h>
38 #include <linux/ioport.h>
39 #include <linux/irq.h>
40 #include <linux/interrupt.h>
41 #include <linux/init.h>
42 #include <linux/bcd.h>
43 #include <linux/profile.h>
45 #include <asm/uaccess.h>
47 #include <asm/hwrpb.h>
48 #include <asm/8253pit.h>
51 #include <linux/mc146818rtc.h>
52 #include <linux/time.h>
53 #include <linux/timex.h>
54 #include <linux/clocksource.h>
59 static int set_rtc_mmss(unsigned long);
61 DEFINE_SPINLOCK(rtc_lock);
62 EXPORT_SYMBOL(rtc_lock);
64 #define TICK_SIZE (tick_nsec / 1000)
67 * Shift amount by which scaled_ticks_per_cycle is scaled. Shifting
68 * by 48 gives us 16 bits for HZ while keeping the accuracy good even
69 * for large CPU clock rates.
73 /* lump static variables together for more efficient access: */
75 /* cycle counter last time it got invoked */
77 /* ticks/cycle * 2^48 */
78 unsigned long scaled_ticks_per_cycle;
79 /* partial unused tick */
80 unsigned long partial_tick;
83 unsigned long est_cycle_freq;
86 static inline __u32 rpcc(void)
89 asm volatile ("rpcc %0" : "=r"(result));
93 int update_persistent_clock(struct timespec now)
95 return set_rtc_mmss(now.tv_sec);
98 void read_persistent_clock(struct timespec *ts)
100 unsigned int year, mon, day, hour, min, sec, epoch;
102 sec = CMOS_READ(RTC_SECONDS);
103 min = CMOS_READ(RTC_MINUTES);
104 hour = CMOS_READ(RTC_HOURS);
105 day = CMOS_READ(RTC_DAY_OF_MONTH);
106 mon = CMOS_READ(RTC_MONTH);
107 year = CMOS_READ(RTC_YEAR);
109 if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
112 hour = bcd2bin(hour);
115 year = bcd2bin(year);
118 /* PC-like is standard; used for year >= 70 */
122 else if (year >= 20 && year < 48)
125 else if (year >= 48 && year < 70)
126 /* Digital UNIX epoch */
129 printk(KERN_INFO "Using epoch = %d\n", epoch);
131 if ((year += epoch) < 1970)
134 ts->tv_sec = mktime(year, mon, day, hour, min, sec);
140 * timer_interrupt() needs to keep up the real-time clock,
141 * as well as call the "do_timer()" routine every clocktick
143 irqreturn_t timer_interrupt(int irq, void *dev)
150 /* Not SMP, do kernel PC profiling here. */
151 profile_tick(CPU_PROFILING);
154 write_seqlock(&xtime_lock);
157 * Calculate how many ticks have passed since the last update,
158 * including any previous partial leftover. Save any resulting
159 * fraction for the next pass.
162 delta = now - state.last_time;
163 state.last_time = now;
164 delta = delta * state.scaled_ticks_per_cycle + state.partial_tick;
165 state.partial_tick = delta & ((1UL << FIX_SHIFT) - 1);
166 nticks = delta >> FIX_SHIFT;
171 write_sequnlock(&xtime_lock);
175 update_process_times(user_mode(get_irq_regs()));
182 common_init_rtc(void)
186 /* Reset periodic interrupt frequency. */
187 x = CMOS_READ(RTC_FREQ_SELECT) & 0x3f;
188 /* Test includes known working values on various platforms
189 where 0x26 is wrong; we refuse to change those. */
190 if (x != 0x26 && x != 0x25 && x != 0x19 && x != 0x06) {
191 printk("Setting RTC_FREQ to 1024 Hz (%x)\n", x);
192 CMOS_WRITE(0x26, RTC_FREQ_SELECT);
195 /* Turn on periodic interrupts. */
196 x = CMOS_READ(RTC_CONTROL);
197 if (!(x & RTC_PIE)) {
198 printk("Turning on RTC interrupts.\n");
200 x &= ~(RTC_AIE | RTC_UIE);
201 CMOS_WRITE(x, RTC_CONTROL);
203 (void) CMOS_READ(RTC_INTR_FLAGS);
205 outb(0x36, 0x43); /* pit counter 0: system timer */
209 outb(0xb6, 0x43); /* pit counter 2: speaker */
216 unsigned int common_get_rtc_time(struct rtc_time *time)
218 return __get_rtc_time(time);
221 int common_set_rtc_time(struct rtc_time *time)
223 return __set_rtc_time(time);
226 /* Validate a computed cycle counter result against the known bounds for
227 the given processor core. There's too much brokenness in the way of
228 timing hardware for any one method to work everywhere. :-(
230 Return 0 if the result cannot be trusted, otherwise return the argument. */
232 static unsigned long __init
233 validate_cc_value(unsigned long cc)
235 static struct bounds {
236 unsigned int min, max;
237 } cpu_hz[] __initdata = {
238 [EV3_CPU] = { 50000000, 200000000 }, /* guess */
239 [EV4_CPU] = { 100000000, 300000000 },
240 [LCA4_CPU] = { 100000000, 300000000 }, /* guess */
241 [EV45_CPU] = { 200000000, 300000000 },
242 [EV5_CPU] = { 250000000, 433000000 },
243 [EV56_CPU] = { 333000000, 667000000 },
244 [PCA56_CPU] = { 400000000, 600000000 }, /* guess */
245 [PCA57_CPU] = { 500000000, 600000000 }, /* guess */
246 [EV6_CPU] = { 466000000, 600000000 },
247 [EV67_CPU] = { 600000000, 750000000 },
248 [EV68AL_CPU] = { 750000000, 940000000 },
249 [EV68CB_CPU] = { 1000000000, 1333333333 },
250 /* None of the following are shipping as of 2001-11-01. */
251 [EV68CX_CPU] = { 1000000000, 1700000000 }, /* guess */
252 [EV69_CPU] = { 1000000000, 1700000000 }, /* guess */
253 [EV7_CPU] = { 800000000, 1400000000 }, /* guess */
254 [EV79_CPU] = { 1000000000, 2000000000 }, /* guess */
257 /* Allow for some drift in the crystal. 10MHz is more than enough. */
258 const unsigned int deviation = 10000000;
260 struct percpu_struct *cpu;
263 cpu = (struct percpu_struct *)((char*)hwrpb + hwrpb->processor_offset);
264 index = cpu->type & 0xffffffff;
266 /* If index out of bounds, no way to validate. */
267 if (index >= ARRAY_SIZE(cpu_hz))
270 /* If index contains no data, no way to validate. */
271 if (cpu_hz[index].max == 0)
274 if (cc < cpu_hz[index].min - deviation
275 || cc > cpu_hz[index].max + deviation)
283 * Calibrate CPU clock using legacy 8254 timer/counter. Stolen from
287 #define CALIBRATE_LATCH 0xffff
288 #define TIMEOUT_COUNT 0x100000
290 static unsigned long __init
291 calibrate_cc_with_pit(void)
295 /* Set the Gate high, disable speaker */
296 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
299 * Now let's take care of CTC channel 2
301 * Set the Gate high, program CTC channel 2 for mode 0,
302 * (interrupt on terminal count mode), binary count,
303 * load 5 * LATCH count, (LSB and MSB) to begin countdown.
305 outb(0xb0, 0x43); /* binary, mode 0, LSB/MSB, Ch 2 */
306 outb(CALIBRATE_LATCH & 0xff, 0x42); /* LSB of count */
307 outb(CALIBRATE_LATCH >> 8, 0x42); /* MSB of count */
312 } while ((inb(0x61) & 0x20) == 0 && count < TIMEOUT_COUNT);
315 /* Error: ECTCNEVERSET or ECPUTOOFAST. */
316 if (count <= 1 || count == TIMEOUT_COUNT)
319 return ((long)cc * PIT_TICK_RATE) / (CALIBRATE_LATCH + 1);
322 /* The Linux interpretation of the CMOS clock register contents:
323 When the Update-In-Progress (UIP) flag goes from 1 to 0, the
324 RTC registers show the second which has precisely just started.
325 Let's hope other operating systems interpret the RTC the same way. */
327 static unsigned long __init
328 rpcc_after_update_in_progress(void)
330 do { } while (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP));
331 do { } while (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP);
337 /* Until and unless we figure out how to get cpu cycle counters
338 in sync and keep them there, we can't use the rpcc. */
339 static cycle_t read_rpcc(struct clocksource *cs)
341 cycle_t ret = (cycle_t)rpcc();
345 static struct clocksource clocksource_rpcc = {
349 .mask = CLOCKSOURCE_MASK(32),
350 .flags = CLOCK_SOURCE_IS_CONTINUOUS
353 static inline void register_rpcc_clocksource(long cycle_freq)
355 clocksource_calc_mult_shift(&clocksource_rpcc, cycle_freq, 4);
356 clocksource_register(&clocksource_rpcc);
358 #else /* !CONFIG_SMP */
359 static inline void register_rpcc_clocksource(long cycle_freq)
362 #endif /* !CONFIG_SMP */
367 unsigned int cc1, cc2;
368 unsigned long cycle_freq, tolerance;
371 /* Calibrate CPU clock -- attempt #1. */
373 est_cycle_freq = validate_cc_value(calibrate_cc_with_pit());
377 /* Calibrate CPU clock -- attempt #2. */
378 if (!est_cycle_freq) {
379 cc1 = rpcc_after_update_in_progress();
380 cc2 = rpcc_after_update_in_progress();
381 est_cycle_freq = validate_cc_value(cc2 - cc1);
385 cycle_freq = hwrpb->cycle_freq;
386 if (est_cycle_freq) {
387 /* If the given value is within 250 PPM of what we calculated,
388 accept it. Otherwise, use what we found. */
389 tolerance = cycle_freq / 4000;
390 diff = cycle_freq - est_cycle_freq;
393 if ((unsigned long)diff > tolerance) {
394 cycle_freq = est_cycle_freq;
395 printk("HWRPB cycle frequency bogus. "
396 "Estimated %lu Hz\n", cycle_freq);
400 } else if (! validate_cc_value (cycle_freq)) {
401 printk("HWRPB cycle frequency bogus, "
402 "and unable to estimate a proper value!\n");
405 /* From John Bowman <bowman@math.ualberta.ca>: allow the values
406 to settle, as the Update-In-Progress bit going low isn't good
407 enough on some hardware. 2ms is our guess; we haven't found
408 bogomips yet, but this is close on a 500Mhz box. */
413 extern void __you_loose (void);
417 register_rpcc_clocksource(cycle_freq);
419 state.last_time = cc1;
420 state.scaled_ticks_per_cycle
421 = ((unsigned long) HZ << FIX_SHIFT) / cycle_freq;
422 state.partial_tick = 0L;
424 /* Startup the timer source. */
429 * In order to set the CMOS clock precisely, set_rtc_mmss has to be
430 * called 500 ms after the second nowtime has started, because when
431 * nowtime is written into the registers of the CMOS clock, it will
432 * jump to the next second precisely 500 ms later. Check the Motorola
433 * MC146818A or Dallas DS12887 data sheet for details.
435 * BUG: This routine does not handle hour overflow properly; it just
436 * sets the minutes. Usually you won't notice until after reboot!
441 set_rtc_mmss(unsigned long nowtime)
444 int real_seconds, real_minutes, cmos_minutes;
445 unsigned char save_control, save_freq_select;
447 /* irq are locally disabled here */
448 spin_lock(&rtc_lock);
449 /* Tell the clock it's being set */
450 save_control = CMOS_READ(RTC_CONTROL);
451 CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
453 /* Stop and reset prescaler */
454 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
455 CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
457 cmos_minutes = CMOS_READ(RTC_MINUTES);
458 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
459 cmos_minutes = bcd2bin(cmos_minutes);
462 * since we're only adjusting minutes and seconds,
463 * don't interfere with hour overflow. This avoids
464 * messing with unknown time zones but requires your
465 * RTC not to be off by more than 15 minutes
467 real_seconds = nowtime % 60;
468 real_minutes = nowtime / 60;
469 if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) {
470 /* correct for half hour time zone */
475 if (abs(real_minutes - cmos_minutes) < 30) {
476 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
477 real_seconds = bin2bcd(real_seconds);
478 real_minutes = bin2bcd(real_minutes);
480 CMOS_WRITE(real_seconds,RTC_SECONDS);
481 CMOS_WRITE(real_minutes,RTC_MINUTES);
484 "set_rtc_mmss: can't update from %d to %d\n",
485 cmos_minutes, real_minutes);
489 /* The following flags have to be released exactly in this order,
490 * otherwise the DS12887 (popular MC146818A clone with integrated
491 * battery and quartz) will not reset the oscillator and will not
492 * update precisely 500 ms later. You won't find this mentioned in
493 * the Dallas Semiconductor data sheets, but who believes data
494 * sheets anyway ... -- Markus Kuhn
496 CMOS_WRITE(save_control, RTC_CONTROL);
497 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
498 spin_unlock(&rtc_lock);