2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 #ifndef _ASM_ARC_ARCREGS_H
10 #define _ASM_ARC_ARCREGS_H
12 /* Build Configuration Registers */
13 #define ARC_REG_DCCMBASE_BCR 0x61 /* DCCM Base Addr */
14 #define ARC_REG_CRC_BCR 0x62
15 #define ARC_REG_DVFB_BCR 0x64
16 #define ARC_REG_EXTARITH_BCR 0x65
17 #define ARC_REG_VECBASE_BCR 0x68
18 #define ARC_REG_PERIBASE_BCR 0x69
19 #define ARC_REG_FP_BCR 0x6B /* Single-Precision FPU */
20 #define ARC_REG_DPFP_BCR 0x6C /* Dbl Precision FPU */
21 #define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */
22 #define ARC_REG_TIMERS_BCR 0x75
23 #define ARC_REG_ICCM_BCR 0x78
24 #define ARC_REG_XY_MEM_BCR 0x79
25 #define ARC_REG_MAC_BCR 0x7a
26 #define ARC_REG_MUL_BCR 0x7b
27 #define ARC_REG_SWAP_BCR 0x7c
28 #define ARC_REG_NORM_BCR 0x7d
29 #define ARC_REG_MIXMAX_BCR 0x7e
30 #define ARC_REG_BARREL_BCR 0x7f
31 #define ARC_REG_D_UNCACH_BCR 0x6A
33 /* status32 Bits Positions */
34 #define STATUS_AE_BIT 5 /* Exception active */
35 #define STATUS_DE_BIT 6 /* PC is in delay slot */
36 #define STATUS_U_BIT 7 /* User/Kernel mode */
37 #define STATUS_L_BIT 12 /* Loop inhibit */
39 /* These masks correspond to the status word(STATUS_32) bits */
40 #define STATUS_AE_MASK (1<<STATUS_AE_BIT)
41 #define STATUS_DE_MASK (1<<STATUS_DE_BIT)
42 #define STATUS_U_MASK (1<<STATUS_U_BIT)
43 #define STATUS_L_MASK (1<<STATUS_L_BIT)
46 * ECR: Exception Cause Reg bits-n-pieces
47 * [23:16] = Exception Vector
48 * [15: 8] = Exception Cause Code
49 * [ 7: 0] = Exception Parameters (for certain types only)
51 #define ECR_VEC_MASK 0xff0000
52 #define ECR_CODE_MASK 0x00ff00
53 #define ECR_PARAM_MASK 0x0000ff
55 /* Exception Cause Vector Values */
56 #define ECR_V_INSN_ERR 0x02
57 #define ECR_V_MACH_CHK 0x20
58 #define ECR_V_ITLB_MISS 0x21
59 #define ECR_V_DTLB_MISS 0x22
60 #define ECR_V_PROTV 0x23
61 #define ECR_V_TRAP 0x25
63 /* Protection Violation Exception Cause Code Values */
64 #define ECR_C_PROTV_INST_FETCH 0x00
65 #define ECR_C_PROTV_LOAD 0x01
66 #define ECR_C_PROTV_STORE 0x02
67 #define ECR_C_PROTV_XCHG 0x03
68 #define ECR_C_PROTV_MISALIG_DATA 0x04
70 #define ECR_C_BIT_PROTV_MISALIG_DATA 10
72 /* Machine Check Cause Code Values */
73 #define ECR_C_MCHK_DUP_TLB 0x01
75 /* DTLB Miss Exception Cause Code Values */
76 #define ECR_C_BIT_DTLB_LD_MISS 8
77 #define ECR_C_BIT_DTLB_ST_MISS 9
79 /* Dummy ECR values for Interrupts */
80 #define event_IRQ1 0x0031abcd
81 #define event_IRQ2 0x0032abcd
83 /* Auxiliary registers */
84 #define AUX_IDENTITY 4
85 #define AUX_INTR_VEC_BASE 0x25
89 * Floating Pt Registers
90 * Status regs are read-only (build-time) so need not be saved/restored
92 #define ARC_AUX_FP_STAT 0x300
93 #define ARC_AUX_DPFP_1L 0x301
94 #define ARC_AUX_DPFP_1H 0x302
95 #define ARC_AUX_DPFP_2L 0x303
96 #define ARC_AUX_DPFP_2H 0x304
97 #define ARC_AUX_DPFP_STAT 0x305
102 ******************************************************************
103 * Inline ASM macros to read/write AUX Regs
104 * Essentially invocation of lr/sr insns from "C"
109 #define read_aux_reg(reg) __builtin_arc_lr(reg)
111 /* gcc builtin sr needs reg param to be long immediate */
112 #define write_aux_reg(reg_immed, val) \
113 __builtin_arc_sr((unsigned int)val, reg_immed)
117 #define read_aux_reg(reg) \
119 unsigned int __ret; \
120 __asm__ __volatile__( \
128 * Aux Reg address is specified as long immediate by caller
130 * write_aux_reg(0x69, some_val);
131 * This generates tightest code.
133 #define write_aux_reg(reg_imm, val) \
135 __asm__ __volatile__( \
138 : "ir"(val), "i"(reg_imm)); \
142 * Aux Reg address is specified in a variable
145 * write_aux_reg2(reg_num, some_val);
146 * This has to generate glue code to load the reg num from
147 * memory to a reg hence not recommended.
149 #define write_aux_reg2(reg_in_var, val) \
153 __asm__ __volatile__( \
154 " ld %0, [%2] \n\t" \
155 " sr %1, [%0] \n\t" \
157 : "r"(val), "memory"(®_in_var)); \
162 #define READ_BCR(reg, into) \
165 tmp = read_aux_reg(reg); \
166 if (sizeof(tmp) == sizeof(into)) { \
167 into = *((typeof(into) *)&tmp); \
169 extern void bogus_undefined(void); \
174 #define WRITE_BCR(reg, into) \
177 if (sizeof(tmp) == sizeof(into)) { \
178 tmp = (*(unsigned int *)(into)); \
179 write_aux_reg(reg, tmp); \
181 extern void bogus_undefined(void); \
187 #define TO_KB(bytes) ((bytes) >> 10)
188 #define TO_MB(bytes) (TO_KB(bytes) >> 10)
189 #define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10))
190 #define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10)
194 ***************************************************************
195 * Build Configuration Registers, with encoded hardware config
197 struct bcr_identity {
198 #ifdef CONFIG_CPU_BIG_ENDIAN
199 unsigned int chip_id:16, cpu_id:8, family:8;
201 unsigned int family:8, cpu_id:8, chip_id:16;
205 #define EXTN_SWAP_VALID 0x1
206 #define EXTN_NORM_VALID 0x2
207 #define EXTN_MINMAX_VALID 0x2
208 #define EXTN_BARREL_VALID 0x2
211 #ifdef CONFIG_CPU_BIG_ENDIAN
212 unsigned int pad:20, crc:1, ext_arith:2, mul:2, barrel:2, minmax:2,
215 unsigned int swap:1, norm:2, minmax:2, barrel:2, mul:2, ext_arith:2,
220 /* DSP Options Ref Manual */
221 struct bcr_extn_mac_mul {
222 #ifdef CONFIG_CPU_BIG_ENDIAN
223 unsigned int pad:16, type:8, ver:8;
225 unsigned int ver:8, type:8, pad:16;
229 struct bcr_extn_xymem {
230 #ifdef CONFIG_CPU_BIG_ENDIAN
231 unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
233 unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
238 #ifdef CONFIG_CPU_BIG_ENDIAN
239 unsigned int start:8, pad2:8, sz:8, pad:8;
241 unsigned int pad:8, sz:8, pad2:8, start:8;
245 #ifdef CONFIG_CPU_BIG_ENDIAN
246 unsigned int base:16, pad:5, sz:3, ver:8;
248 unsigned int ver:8, sz:3, pad:5, base:16;
252 /* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */
253 struct bcr_dccm_base {
254 #ifdef CONFIG_CPU_BIG_ENDIAN
255 unsigned int addr:24, ver:8;
257 unsigned int ver:8, addr:24;
261 /* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */
263 #ifdef CONFIG_CPU_BIG_ENDIAN
264 unsigned int res:21, sz:3, ver:8;
266 unsigned int ver:8, sz:3, res:21;
270 /* Both SP and DP FPU BCRs have same format */
272 #ifdef CONFIG_CPU_BIG_ENDIAN
273 unsigned int fast:1, ver:8;
275 unsigned int ver:8, fast:1;
280 *******************************************************************
281 * Generic structures to hold build configuration used at runtime
284 struct cpuinfo_arc_mmu {
285 unsigned int ver, pg_sz, sets, ways, u_dtlb, u_itlb, num_tlb;
288 struct cpuinfo_arc_cache {
289 unsigned int sz_k:8, line_len:8, assoc:4, ver:4, alias:1, vipt:1, pad:6;
292 struct cpuinfo_arc_ccm {
293 unsigned int base_addr, sz;
297 struct cpuinfo_arc_cache icache, dcache;
298 struct cpuinfo_arc_mmu mmu;
299 struct bcr_identity core;
301 unsigned int vec_base;
302 unsigned int uncached_base;
303 struct cpuinfo_arc_ccm iccm, dccm;
304 struct bcr_extn extn;
305 struct bcr_extn_xymem extn_xymem;
306 struct bcr_extn_mac_mul extn_mac_mul;
307 struct bcr_fp fp, dpfp;
310 extern struct cpuinfo_arc cpuinfo_arc700[];
312 #endif /* __ASEMBLY__ */
314 #endif /* _ASM_ARC_ARCREGS_H */