2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
12 #ifndef _LINUX_BITOPS_H
13 #error only <linux/bitops.h> can be included directly
18 #include <linux/types.h>
19 #include <linux/compiler.h>
20 #include <asm/barrier.h>
23 * Hardware assisted read-modify-write using ARC700 LLOCK/SCOND insns.
24 * The Kconfig glue ensures that in SMP, this is only set if the container
25 * SoC/platform has cross-core coherent LLOCK/SCOND
27 #if defined(CONFIG_ARC_HAS_LLSC)
29 static inline void set_bit(unsigned long nr, volatile unsigned long *m)
36 * ARC ISA micro-optimization:
38 * Instructions dealing with bitpos only consider lower 5 bits (0-31)
39 * e.g (x << 33) is handled like (x << 1) by ASL instruction
40 * (mem pointer still needs adjustment to point to next word)
42 * Hence the masking to clamp @nr arg can be elided in general.
44 * However if @nr is a constant (above assumed it in a register),
45 * and greater than 31, gcc can optimize away (x << 33) to 0,
46 * as overflow, given the 32-bit ISA. Thus masking needs to be done
47 * for constant @nr, but no code is generated due to const prop.
49 if (__builtin_constant_p(nr))
53 "1: llock %0, [%1] \n"
62 static inline void clear_bit(unsigned long nr, volatile unsigned long *m)
68 if (__builtin_constant_p(nr))
72 "1: llock %0, [%1] \n"
81 static inline void change_bit(unsigned long nr, volatile unsigned long *m)
87 if (__builtin_constant_p(nr))
91 "1: llock %0, [%1] \n"
104 * set it and return 0 (old value)
106 * return 1 (old value).
108 * Since ARC lacks a equivalent h/w primitive, the bit is set unconditionally
109 * and the old value of bit is returned
111 static inline int test_and_set_bit(unsigned long nr, volatile unsigned long *m)
113 unsigned long old, temp;
117 if (__builtin_constant_p(nr))
120 __asm__ __volatile__(
121 "1: llock %0, [%2] \n"
122 " bset %1, %0, %3 \n"
125 : "=&r"(old), "=&r"(temp)
129 return (old & (1 << nr)) != 0;
133 test_and_clear_bit(unsigned long nr, volatile unsigned long *m)
135 unsigned int old, temp;
139 if (__builtin_constant_p(nr))
142 __asm__ __volatile__(
143 "1: llock %0, [%2] \n"
144 " bclr %1, %0, %3 \n"
147 : "=&r"(old), "=&r"(temp)
151 return (old & (1 << nr)) != 0;
155 test_and_change_bit(unsigned long nr, volatile unsigned long *m)
157 unsigned int old, temp;
161 if (__builtin_constant_p(nr))
164 __asm__ __volatile__(
165 "1: llock %0, [%2] \n"
166 " bxor %1, %0, %3 \n"
169 : "=&r"(old), "=&r"(temp)
173 return (old & (1 << nr)) != 0;
176 #else /* !CONFIG_ARC_HAS_LLSC */
181 * Non hardware assisted Atomic-R-M-W
182 * Locking would change to irq-disabling only (UP) and spinlocks (SMP)
184 * There's "significant" micro-optimization in writing our own variants of
185 * bitops (over generic variants)
187 * (1) The generic APIs have "signed" @nr while we have it "unsigned"
188 * This avoids extra code to be generated for pointer arithmatic, since
189 * is "not sure" that index is NOT -ve
190 * (2) Utilize the fact that ARCompact bit fidding insn (BSET/BCLR/ASL) etc
191 * only consider bottom 5 bits of @nr, so NO need to mask them off.
192 * (GCC Quirk: however for constant @nr we still need to do the masking
196 static inline void set_bit(unsigned long nr, volatile unsigned long *m)
198 unsigned long temp, flags;
201 if (__builtin_constant_p(nr))
207 *m = temp | (1UL << nr);
209 bitops_unlock(flags);
212 static inline void clear_bit(unsigned long nr, volatile unsigned long *m)
214 unsigned long temp, flags;
217 if (__builtin_constant_p(nr))
223 *m = temp & ~(1UL << nr);
225 bitops_unlock(flags);
228 static inline void change_bit(unsigned long nr, volatile unsigned long *m)
230 unsigned long temp, flags;
233 if (__builtin_constant_p(nr))
239 *m = temp ^ (1UL << nr);
241 bitops_unlock(flags);
244 static inline int test_and_set_bit(unsigned long nr, volatile unsigned long *m)
246 unsigned long old, flags;
249 if (__builtin_constant_p(nr))
255 *m = old | (1 << nr);
257 bitops_unlock(flags);
259 return (old & (1 << nr)) != 0;
263 test_and_clear_bit(unsigned long nr, volatile unsigned long *m)
265 unsigned long old, flags;
268 if (__builtin_constant_p(nr))
274 *m = old & ~(1 << nr);
276 bitops_unlock(flags);
278 return (old & (1 << nr)) != 0;
282 test_and_change_bit(unsigned long nr, volatile unsigned long *m)
284 unsigned long old, flags;
287 if (__builtin_constant_p(nr))
293 *m = old ^ (1 << nr);
295 bitops_unlock(flags);
297 return (old & (1 << nr)) != 0;
300 #endif /* CONFIG_ARC_HAS_LLSC */
302 /***************************************
303 * Non atomic variants
304 **************************************/
306 static inline void __set_bit(unsigned long nr, volatile unsigned long *m)
311 if (__builtin_constant_p(nr))
315 *m = temp | (1UL << nr);
318 static inline void __clear_bit(unsigned long nr, volatile unsigned long *m)
323 if (__builtin_constant_p(nr))
327 *m = temp & ~(1UL << nr);
330 static inline void __change_bit(unsigned long nr, volatile unsigned long *m)
335 if (__builtin_constant_p(nr))
339 *m = temp ^ (1UL << nr);
343 __test_and_set_bit(unsigned long nr, volatile unsigned long *m)
348 if (__builtin_constant_p(nr))
352 *m = old | (1 << nr);
354 return (old & (1 << nr)) != 0;
358 __test_and_clear_bit(unsigned long nr, volatile unsigned long *m)
363 if (__builtin_constant_p(nr))
367 *m = old & ~(1 << nr);
369 return (old & (1 << nr)) != 0;
373 __test_and_change_bit(unsigned long nr, volatile unsigned long *m)
378 if (__builtin_constant_p(nr))
382 *m = old ^ (1 << nr);
384 return (old & (1 << nr)) != 0;
388 * This routine doesn't need to be atomic.
391 test_bit(unsigned int nr, const volatile unsigned long *addr)
397 if (__builtin_constant_p(nr))
402 return ((mask & *addr) != 0);
406 * Count the number of zeros, starting from MSB
407 * Helper for fls( ) friends
408 * This is a pure count, so (1-32) or (0-31) doesn't apply
409 * It could be 0 to 32, based on num of 0's in there
410 * clz(0x8000_0000) = 0, clz(0xFFFF_FFFF)=0, clz(0) = 32, clz(1) = 31
412 static inline __attribute__ ((const)) int clz(unsigned int x)
416 __asm__ __volatile__(
419 " add.p %0, %0, 1 \n"
427 static inline int constant_fls(int x)
433 if (!(x & 0xffff0000u)) {
437 if (!(x & 0xff000000u)) {
441 if (!(x & 0xf0000000u)) {
445 if (!(x & 0xc0000000u)) {
449 if (!(x & 0x80000000u)) {
457 * fls = Find Last Set in word
459 * fls(1) = 1, fls(0x80000000) = 32, fls(0) = 0
461 static inline __attribute__ ((const)) int fls(unsigned long x)
463 if (__builtin_constant_p(x))
464 return constant_fls(x);
470 * __fls: Similar to fls, but zero based (0-31)
472 static inline __attribute__ ((const)) int __fls(unsigned long x)
481 * ffs = Find First Set in word (LSB to MSB)
482 * @result: [1-32], 0 if all 0's
484 #define ffs(x) ({ unsigned long __t = (x); fls(__t & -__t); })
487 * __ffs: Similar to ffs, but zero based (0-31)
489 static inline __attribute__ ((const)) int __ffs(unsigned long word)
494 return ffs(word) - 1;
498 * ffz = Find First Zero in word.
499 * @return:[0-31], 32 if all 1's
501 #define ffz(x) __ffs(~(x))
503 #include <asm-generic/bitops/hweight.h>
504 #include <asm-generic/bitops/fls64.h>
505 #include <asm-generic/bitops/sched.h>
506 #include <asm-generic/bitops/lock.h>
508 #include <asm-generic/bitops/find.h>
509 #include <asm-generic/bitops/le.h>
510 #include <asm-generic/bitops/ext2-atomic-setbit.h>
512 #endif /* !__ASSEMBLY__ */