2 * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * Vineetg: March 2009 (Supporting 2 levels of Interrupts)
10 * Stack switching code can no longer reliably rely on the fact that
11 * if we are NOT in user mode, stack is switched to kernel mode.
12 * e.g. L2 IRQ interrupted a L1 ISR which had not yet completed
13 * it's prologue including stack switching from user mode
15 * Vineetg: Aug 28th 2008: Bug #94984
16 * -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
17 * Normally CPU does this automatically, however when doing FAKE rtie,
18 * we also need to explicitly do this. The problem in macros
19 * FAKE_RET_FROM_EXCPN and FAKE_RET_FROM_EXCPN_LOCK_IRQ was that this bit
20 * was being "CLEARED" rather then "SET". Actually "SET" clears ZOL context
22 * Vineetg: May 5th 2008
23 * -Modified CALLEE_REG save/restore macros to handle the fact that
24 * r25 contains the kernel current task ptr
25 * - Defined Stack Switching Macro to be reused in all intr/excp hdlrs
26 * - Shaved off 11 instructions from RESTORE_ALL_INT1 by using the
27 * address Write back load ld.ab instead of seperate ld/add instn
29 * Amit Bhor, Sameer Dhavale: Codito Technologies 2004
32 #ifndef __ASM_ARC_ENTRY_COMPACT_H
33 #define __ASM_ARC_ENTRY_COMPACT_H
35 #include <asm/asm-offsets.h>
36 #include <asm/thread_info.h> /* For THREAD_SIZE */
38 /*--------------------------------------------------------------
39 * Switch to Kernel Mode stack if SP points to User Mode stack
41 * Entry : r9 contains pre-IRQ/exception/trap status32
42 * Exit : SP is set to kernel mode stack pointer
43 * If CURR_IN_REG, r25 set to "current" task pointer
45 *-------------------------------------------------------------*/
47 .macro SWITCH_TO_KERNEL_STK
49 /* User Mode when this happened ? Yes: Proceed to switch stack */
50 bbit1 r9, STATUS_U_BIT, 88f
52 /* OK we were already in kernel mode when this event happened, thus can
53 * assume SP is kernel mode SP. _NO_ need to do any stack switching
56 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS
58 * If Level 2 Interrupts enabled, we may end up with a corner case:
59 * 1. User Task executing
60 * 2. L1 IRQ taken, ISR starts (CPU auto-switched to KERNEL mode)
61 * 3. But before it could switch SP from USER to KERNEL stack
62 * a L2 IRQ "Interrupts" L1
63 * Thay way although L2 IRQ happened in Kernel mode, stack is still
65 * To handle this, we may need to switch stack even if in kernel mode
66 * provided SP has values in range of USER mode stack ( < 0x7000_0000 )
68 brlo sp, VMALLOC_START, 88f
71 * We need to be a bit more cautious here. What if a kernel bug in
72 * L1 ISR, caused SP to go whaco (some small value which looks like
73 * USER stk) and then we take L2 ISR.
74 * Above brlo alone would treat it as a valid L1-L2 sceanrio
75 * instead of shouting alound
76 * The only feasible way is to make sure this L2 happened in
77 * L1 prelogue ONLY i.e. ilink2 is less than a pre-set marker in
78 * L1 ISR before it switches stack
83 /* Save Pre Intr/Exception KERNEL MODE SP on kernel stack
84 * safe-keeping not really needed, but it keeps the epilogue code
85 * (SP restore) simpler/uniform.
90 88: /*------Intr/Ecxp happened in user mode, "switch" stack ------ */
92 GET_CURR_TASK_ON_CPU r9
94 /* With current tsk in r9, get it's kernel mode stack base */
95 GET_TSK_STACK_BASE r9, r9
98 #ifdef CONFIG_ARC_CURR_IN_REG
100 * Treat r25 as scratch reg, save it on stack first
101 * Load it with current task pointer
104 GET_CURR_TASK_ON_CPU r25
107 /* Save Pre Intr/Exception User SP on kernel stack */
108 st.a sp, [r9, -16] ; Make room for orig_r0, ECR, user_r25
111 * SP should be set at the very end when we are done with everything
112 * In case of 2 levels of interrupt we depend on value of SP to assume
113 * that everything else is done (loading r25 etc)
116 /* set SP to point to kernel mode stack */
119 /* ----- Stack Switched to kernel Mode, Now save REG FILE ----- */
123 /*------------------------------------------------------------
124 * "FAKE" a rtie to return from CPU Exception context
125 * This is to re-enable Exceptions within exception
126 * Look at EV_ProtV to see how this is actually used
127 *-------------------------------------------------------------*/
129 .macro FAKE_RET_FROM_EXCPN
131 ld r9, [sp, PT_status32]
132 bic r9, r9, (STATUS_U_MASK|STATUS_DE_MASK)
133 bset r9, r9, STATUS_L_BIT
142 /*--------------------------------------------------------------
143 * For early Exception/ISR Prologue, a core reg is temporarily needed to
144 * code the rest of prolog (stack switching). This is done by stashing
145 * it to memory (non-SMP case) or SCRATCH0 Aux Reg (SMP).
147 * Before saving the full regfile - this reg is restored back, only
148 * to be saved again on kernel mode stack, as part of pt_regs.
149 *-------------------------------------------------------------*/
150 .macro PROLOG_FREEUP_REG reg, mem
152 sr \reg, [ARC_REG_SCRATCH_DATA0]
158 .macro PROLOG_RESTORE_REG reg, mem
160 lr \reg, [ARC_REG_SCRATCH_DATA0]
166 /*--------------------------------------------------------------
167 * Exception Entry prologue
168 * -Switches stack to K mode (if not already)
169 * -Saves the register file
171 * After this it is safe to call the "C" handlers
172 *-------------------------------------------------------------*/
173 .macro EXCEPTION_PROLOGUE
175 /* Need at least 1 reg to code the early exception prologue */
176 PROLOG_FREEUP_REG r9, @ex_saved_reg1
178 /* U/K mode at time of exception (stack not switched if already K) */
181 /* ARC700 doesn't provide auto-stack switching */
184 st r0, [sp, 4] /* orig_r0, needed only for sys calls */
186 /* Restore r9 used to code the early prologue */
187 PROLOG_RESTORE_REG r9, @ex_saved_reg1
201 st r9, [sp, PT_event] /* EV_Trap expects r9 to have ECR */
204 /*--------------------------------------------------------------
205 * Restore all registers used by system call or Exceptions
206 * SP should always be pointing to the next free stack element
207 * when entering this macro.
211 * It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
212 * for memory load operations. If used in that way interrupts are deffered
213 * by hardware and that is not good.
214 *-------------------------------------------------------------*/
215 .macro EXCEPTION_EPILOGUE
221 mov lp_count, r9 ;LD to lp_count is not allowed
230 ld sp, [sp] /* restore original sp */
231 /* orig_r0, ECR, user_r25 skipped automatically */
234 /* Dummy ECR values for Interrupts */
235 #define event_IRQ1 0x0031abcd
236 #define event_IRQ2 0x0032abcd
238 .macro INTERRUPT_PROLOGUE LVL
240 /* free up r9 as scratchpad */
241 PROLOG_FREEUP_REG r9, @int\LVL\()_saved_reg
243 /* Which mode (user/kernel) was the system in when intr occured */
244 lr r9, [status32_l\LVL\()]
248 /* restore original r9 */
249 PROLOG_RESTORE_REG r9, @int\LVL\()_saved_reg
251 /* now we are ready to save the remaining context */
252 st 0x003\LVL\()abcd, [sp, 8] /* Dummy ECR */
253 st 0, [sp, 4] /* orig_r0 , N/A for IRQ */
260 PUSHAX status32_l\LVL\()
267 /*--------------------------------------------------------------
268 * Restore all registers used by interrupt handlers.
272 * It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
273 * for memory load operations. If used in that way interrupts are deffered
274 * by hardware and that is not good.
275 *-------------------------------------------------------------*/
276 .macro INTERRUPT_EPILOGUE LVL
282 mov lp_count, r9 ;LD to lp_count is not allowed
284 POPAX status32_l\LVL\()
291 ld sp, [sp] /* restore original sp */
292 /* orig_r0, ECR, user_r25 skipped automatically */
295 /* Get thread_info of "current" tsk */
296 .macro GET_CURR_THR_INFO_FROM_SP reg
297 bic \reg, sp, (THREAD_SIZE - 1)
300 /* Get CPU-ID of this core */
301 .macro GET_CPU_ID reg
307 #endif /* __ASM_ARC_ENTRY_COMPACT_H */