2 * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/interrupt.h>
11 #include <linux/module.h>
13 #include <linux/irqdomain.h>
14 #include <linux/irqchip.h>
15 #include "../../drivers/irqchip/irqchip.h"
16 #include <asm/sections.h>
18 #include <asm/mach_desc.h>
21 * Early Hardware specific Interrupt setup
22 * -Platform independent, needed for each CPU (not foldable into init_IRQ)
23 * -Called very early (start_kernel -> setup_arch -> setup_processor)
26 * -Optionally, setup the High priority Interrupts as Level 2 IRQs
28 void arc_init_IRQ(void)
32 /* setup any high priority Interrupts (Level2 in ARCompact jargon) */
33 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ3_LV2) << 3;
34 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ5_LV2) << 5;
35 level_mask |= IS_ENABLED(CONFIG_ARC_IRQ6_LV2) << 6;
38 * Write to register, even if no LV2 IRQs configured to reset it
39 * in case bootloader had mucked with it
41 write_aux_reg(AUX_IRQ_LEV, level_mask);
44 pr_info("Level-2 interrupts bitset %x\n", level_mask);
48 * ARC700 core includes a simple on-chip intc supporting
49 * -per IRQ enable/disable
50 * -2 levels of interrupts (high/low)
51 * -all interrupts being level triggered
53 * To reduce platform code, we assume all IRQs directly hooked-up into intc.
54 * Platforms with external intc, hence cascaded IRQs, are free to over-ride
58 static void arc_mask_irq(struct irq_data *data)
60 arch_mask_irq(data->irq);
63 static void arc_unmask_irq(struct irq_data *data)
65 arch_unmask_irq(data->irq);
68 static struct irq_chip onchip_intc = {
69 .name = "ARC In-core Intc",
70 .irq_mask = arc_mask_irq,
71 .irq_unmask = arc_unmask_irq,
74 static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq,
77 if (irq == TIMER0_IRQ)
78 irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq);
80 irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq);
85 static const struct irq_domain_ops arc_intc_domain_ops = {
86 .xlate = irq_domain_xlate_onecell,
87 .map = arc_intc_domain_map,
90 static struct irq_domain *root_domain;
93 init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
96 panic("DeviceTree incore intc not a root irq controller\n");
98 root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0,
99 &arc_intc_domain_ops, NULL);
102 panic("root irq domain not avail\n");
104 /* with this we don't need to export root_domain */
105 irq_set_default_host(root_domain);
110 IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
113 * Late Interrupt system init called from start_kernel for Boot CPU only
115 * Since slab must already be initialized, platforms can start doing any
116 * needed request_irq( )s
118 void __init init_IRQ(void)
120 /* Any external intc can be setup here */
121 if (machine_desc->init_irq)
122 machine_desc->init_irq();
124 /* process the entire interrupt tree in one go */
128 /* Master CPU can initialize it's side of IPI */
129 if (machine_desc->init_smp)
130 machine_desc->init_smp(smp_processor_id());
135 * "C" Entry point for any ARC ISR, called from low level vector handler
136 * @irq is the vector number read from ICAUSE reg of on-chip intc
138 void arch_do_IRQ(unsigned int irq, struct pt_regs *regs)
140 struct pt_regs *old_regs = set_irq_regs(regs);
143 generic_handle_irq(irq);
145 set_irq_regs(old_regs);
148 void arc_request_percpu_irq(int irq, int cpu,
149 irqreturn_t (*isr)(int irq, void *dev),
153 /* Boot cpu calls request, all call enable */
158 * These 2 calls are essential to making percpu IRQ APIs work
159 * Ideally these details could be hidden in irq chip map function
160 * but the issue is IPIs IRQs being static (non-DT) and platform
161 * specific, so we can't identify them there.
163 irq_set_percpu_devid(irq);
164 irq_modify_status(irq, IRQ_NOAUTOEN, 0); /* @irq, @clr, @set */
166 rc = request_percpu_irq(irq, isr, irq_nm, percpu_dev);
168 panic("Percpu IRQ request failed for %d\n", irq);
171 enable_percpu_irq(irq, 0);
175 * arch_local_irq_enable - Enable interrupts.
177 * 1. Explicitly called to re-enable interrupts
178 * 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc
179 * which maybe in hard ISR itself
181 * Semantics of this function change depending on where it is called from:
183 * -If called from hard-ISR, it must not invert interrupt priorities
184 * e.g. suppose TIMER is high priority (Level 2) IRQ
185 * Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times.
186 * Here local_irq_enable( ) shd not re-enable lower priority interrupts
187 * -If called from soft-ISR, it must re-enable all interrupts
188 * soft ISR are low prioity jobs which can be very slow, thus all IRQs
189 * must be enabled while they run.
190 * Now hardware context wise we may still be in L2 ISR (not done rtie)
191 * still we must re-enable both L1 and L2 IRQs
192 * Another twist is prev scenario with flow being
193 * L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR
194 * here we must not re-enable Ll as prev Ll Interrupt's h/w context will get
195 * over-written (this is deficiency in ARC700 Interrupt mechanism)
198 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS /* Complex version for 2 IRQ levels */
200 void arch_local_irq_enable(void)
204 flags = arch_local_save_flags();
206 /* Allow both L1 and L2 at the onset */
207 flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
209 /* Called from hard ISR (between irq_enter and irq_exit) */
212 /* If in L2 ISR, don't re-enable any further IRQs as this can
213 * cause IRQ priorities to get upside down. e.g. it could allow
214 * L1 be taken while in L2 hard ISR which is wrong not only in
215 * theory, it can also cause the dreaded L1-L2-L1 scenario
217 if (flags & STATUS_A2_MASK)
218 flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK);
220 /* Even if in L1 ISR, allowe Higher prio L2 IRQs */
221 else if (flags & STATUS_A1_MASK)
222 flags &= ~(STATUS_E1_MASK);
225 /* called from soft IRQ, ideally we want to re-enable all levels */
227 else if (in_softirq()) {
229 /* However if this is case of L1 interrupted by L2,
230 * re-enabling both may cause whaco L1-L2-L1 scenario
231 * because ARC700 allows level 1 to interrupt an active L2 ISR
232 * Thus we disable both
233 * However some code, executing in soft ISR wants some IRQs
234 * to be enabled so we re-enable L2 only
236 * How do we determine L1 intr by L2
237 * -A2 is set (means in L2 ISR)
238 * -E1 is set in this ISR's pt_regs->status32 which is
239 * saved copy of status32_l2 when l2 ISR happened
241 struct pt_regs *pt = get_irq_regs();
242 if ((flags & STATUS_A2_MASK) && pt &&
243 (pt->status32 & STATUS_A1_MASK)) {
244 /*flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK); */
245 flags &= ~(STATUS_E1_MASK);
249 arch_local_irq_restore(flags);
252 #else /* ! CONFIG_ARC_COMPACT_IRQ_LEVELS */
255 * Simpler version for only 1 level of interrupt
256 * Here we only Worry about Level 1 Bits
258 void arch_local_irq_enable(void)
263 * ARC IDE Drivers tries to re-enable interrupts from hard-isr
264 * context which is simply wrong
267 WARN_ONCE(1, "IRQ enabled from hard-isr");
271 flags = arch_local_save_flags();
272 flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
273 arch_local_irq_restore(flags);
276 EXPORT_SYMBOL(arch_local_irq_enable);