2 * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/interrupt.h>
11 #include <linux/module.h>
13 #include <linux/irqdomain.h>
14 #include <linux/irqchip.h>
15 #include "../../drivers/irqchip/irqchip.h"
16 #include <asm/sections.h>
18 #include <asm/mach_desc.h>
21 * Early Hardware specific Interrupt setup
22 * -Called very early (start_kernel -> setup_arch -> setup_processor)
23 * -Platform Independent (must for any ARC700)
24 * -Needed for each CPU (hence not foldable into init_IRQ)
27 * -setup Vector Table Base Reg - in case Linux not linked at 0x8000_0000
28 * -Disable all IRQs (on CPU side)
29 * -Optionally, setup the High priority Interrupts as Level 2 IRQs
31 void __cpuinit arc_init_IRQ(void)
35 write_aux_reg(AUX_INTR_VEC_BASE, _int_vec_base_lds);
37 /* Disable all IRQs: enable them as devices request */
38 write_aux_reg(AUX_IENABLE, 0);
40 /* setup any high priority Interrupts (Level2 in ARCompact jargon) */
41 #ifdef CONFIG_ARC_IRQ3_LV2
42 level_mask |= (1 << 3);
44 #ifdef CONFIG_ARC_IRQ5_LV2
45 level_mask |= (1 << 5);
47 #ifdef CONFIG_ARC_IRQ6_LV2
48 level_mask |= (1 << 6);
52 pr_info("Level-2 interrupts bitset %x\n", level_mask);
53 write_aux_reg(AUX_IRQ_LEV, level_mask);
58 * ARC700 core includes a simple on-chip intc supporting
59 * -per IRQ enable/disable
60 * -2 levels of interrupts (high/low)
61 * -all interrupts being level triggered
63 * To reduce platform code, we assume all IRQs directly hooked-up into intc.
64 * Platforms with external intc, hence cascaded IRQs, are free to over-ride
68 static void arc_mask_irq(struct irq_data *data)
70 arch_mask_irq(data->irq);
73 static void arc_unmask_irq(struct irq_data *data)
75 arch_unmask_irq(data->irq);
78 static struct irq_chip onchip_intc = {
79 .name = "ARC In-core Intc",
80 .irq_mask = arc_mask_irq,
81 .irq_unmask = arc_unmask_irq,
84 static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq,
87 if (irq == TIMER0_IRQ)
88 irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq);
90 irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq);
95 static const struct irq_domain_ops arc_intc_domain_ops = {
96 .xlate = irq_domain_xlate_onecell,
97 .map = arc_intc_domain_map,
100 static struct irq_domain *root_domain;
103 init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
106 panic("DeviceTree incore intc not a root irq controller\n");
108 root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0,
109 &arc_intc_domain_ops, NULL);
112 panic("root irq domain not avail\n");
114 /* with this we don't need to export root_domain */
115 irq_set_default_host(root_domain);
120 IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
123 * Late Interrupt system init called from start_kernel for Boot CPU only
125 * Since slab must already be initialized, platforms can start doing any
126 * needed request_irq( )s
128 void __init init_IRQ(void)
130 /* Any external intc can be setup here */
131 if (machine_desc->init_irq)
132 machine_desc->init_irq();
134 /* process the entire interrupt tree in one go */
138 /* Master CPU can initialize it's side of IPI */
139 if (machine_desc->init_smp)
140 machine_desc->init_smp(smp_processor_id());
145 * "C" Entry point for any ARC ISR, called from low level vector handler
146 * @irq is the vector number read from ICAUSE reg of on-chip intc
148 void arch_do_IRQ(unsigned int irq, struct pt_regs *regs)
150 struct pt_regs *old_regs = set_irq_regs(regs);
153 generic_handle_irq(irq);
155 set_irq_regs(old_regs);
158 int __init get_hw_config_num_irq(void)
160 uint32_t val = read_aux_reg(ARC_REG_VECBASE_BCR);
162 switch (val & 0x03) {
177 * arch_local_irq_enable - Enable interrupts.
179 * 1. Explicitly called to re-enable interrupts
180 * 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc
181 * which maybe in hard ISR itself
183 * Semantics of this function change depending on where it is called from:
185 * -If called from hard-ISR, it must not invert interrupt priorities
186 * e.g. suppose TIMER is high priority (Level 2) IRQ
187 * Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times.
188 * Here local_irq_enable( ) shd not re-enable lower priority interrupts
189 * -If called from soft-ISR, it must re-enable all interrupts
190 * soft ISR are low prioity jobs which can be very slow, thus all IRQs
191 * must be enabled while they run.
192 * Now hardware context wise we may still be in L2 ISR (not done rtie)
193 * still we must re-enable both L1 and L2 IRQs
194 * Another twist is prev scenario with flow being
195 * L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR
196 * here we must not re-enable Ll as prev Ll Interrupt's h/w context will get
197 * over-written (this is deficiency in ARC700 Interrupt mechanism)
200 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS /* Complex version for 2 IRQ levels */
202 void arch_local_irq_enable(void)
206 flags = arch_local_save_flags();
208 /* Allow both L1 and L2 at the onset */
209 flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
211 /* Called from hard ISR (between irq_enter and irq_exit) */
214 /* If in L2 ISR, don't re-enable any further IRQs as this can
215 * cause IRQ priorities to get upside down. e.g. it could allow
216 * L1 be taken while in L2 hard ISR which is wrong not only in
217 * theory, it can also cause the dreaded L1-L2-L1 scenario
219 if (flags & STATUS_A2_MASK)
220 flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK);
222 /* Even if in L1 ISR, allowe Higher prio L2 IRQs */
223 else if (flags & STATUS_A1_MASK)
224 flags &= ~(STATUS_E1_MASK);
227 /* called from soft IRQ, ideally we want to re-enable all levels */
229 else if (in_softirq()) {
231 /* However if this is case of L1 interrupted by L2,
232 * re-enabling both may cause whaco L1-L2-L1 scenario
233 * because ARC700 allows level 1 to interrupt an active L2 ISR
234 * Thus we disable both
235 * However some code, executing in soft ISR wants some IRQs
236 * to be enabled so we re-enable L2 only
238 * How do we determine L1 intr by L2
239 * -A2 is set (means in L2 ISR)
240 * -E1 is set in this ISR's pt_regs->status32 which is
241 * saved copy of status32_l2 when l2 ISR happened
243 struct pt_regs *pt = get_irq_regs();
244 if ((flags & STATUS_A2_MASK) && pt &&
245 (pt->status32 & STATUS_A1_MASK)) {
246 /*flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK); */
247 flags &= ~(STATUS_E1_MASK);
251 arch_local_irq_restore(flags);
254 #else /* ! CONFIG_ARC_COMPACT_IRQ_LEVELS */
257 * Simpler version for only 1 level of interrupt
258 * Here we only Worry about Level 1 Bits
260 void arch_local_irq_enable(void)
265 * ARC IDE Drivers tries to re-enable interrupts from hard-isr
266 * context which is simply wrong
269 WARN_ONCE(1, "IRQ enabled from hard-isr");
273 flags = arch_local_save_flags();
274 flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
275 arch_local_irq_restore(flags);
278 EXPORT_SYMBOL(arch_local_irq_enable);