2 * Copyright (C) 2011-12 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/interrupt.h>
11 #include <linux/module.h>
13 #include <linux/irqdomain.h>
14 #include <linux/irqchip.h>
15 #include "../../drivers/irqchip/irqchip.h"
16 #include <asm/sections.h>
18 #include <asm/mach_desc.h>
21 * Early Hardware specific Interrupt setup
22 * -Called very early (start_kernel -> setup_arch -> setup_processor)
23 * -Platform Independent (must for any ARC700)
24 * -Needed for each CPU (hence not foldable into init_IRQ)
27 * -Disable all IRQs (on CPU side)
28 * -Optionally, setup the High priority Interrupts as Level 2 IRQs
30 void __cpuinit arc_init_IRQ(void)
34 /* Disable all IRQs: enable them as devices request */
35 write_aux_reg(AUX_IENABLE, 0);
37 /* setup any high priority Interrupts (Level2 in ARCompact jargon) */
38 #ifdef CONFIG_ARC_IRQ3_LV2
39 level_mask |= (1 << 3);
41 #ifdef CONFIG_ARC_IRQ5_LV2
42 level_mask |= (1 << 5);
44 #ifdef CONFIG_ARC_IRQ6_LV2
45 level_mask |= (1 << 6);
49 pr_info("Level-2 interrupts bitset %x\n", level_mask);
50 write_aux_reg(AUX_IRQ_LEV, level_mask);
55 * ARC700 core includes a simple on-chip intc supporting
56 * -per IRQ enable/disable
57 * -2 levels of interrupts (high/low)
58 * -all interrupts being level triggered
60 * To reduce platform code, we assume all IRQs directly hooked-up into intc.
61 * Platforms with external intc, hence cascaded IRQs, are free to over-ride
65 static void arc_mask_irq(struct irq_data *data)
67 arch_mask_irq(data->irq);
70 static void arc_unmask_irq(struct irq_data *data)
72 arch_unmask_irq(data->irq);
75 static struct irq_chip onchip_intc = {
76 .name = "ARC In-core Intc",
77 .irq_mask = arc_mask_irq,
78 .irq_unmask = arc_unmask_irq,
81 static int arc_intc_domain_map(struct irq_domain *d, unsigned int irq,
84 if (irq == TIMER0_IRQ)
85 irq_set_chip_and_handler(irq, &onchip_intc, handle_percpu_irq);
87 irq_set_chip_and_handler(irq, &onchip_intc, handle_level_irq);
92 static const struct irq_domain_ops arc_intc_domain_ops = {
93 .xlate = irq_domain_xlate_onecell,
94 .map = arc_intc_domain_map,
97 static struct irq_domain *root_domain;
100 init_onchip_IRQ(struct device_node *intc, struct device_node *parent)
103 panic("DeviceTree incore intc not a root irq controller\n");
105 root_domain = irq_domain_add_legacy(intc, NR_CPU_IRQS, 0, 0,
106 &arc_intc_domain_ops, NULL);
109 panic("root irq domain not avail\n");
111 /* with this we don't need to export root_domain */
112 irq_set_default_host(root_domain);
117 IRQCHIP_DECLARE(arc_intc, "snps,arc700-intc", init_onchip_IRQ);
120 * Late Interrupt system init called from start_kernel for Boot CPU only
122 * Since slab must already be initialized, platforms can start doing any
123 * needed request_irq( )s
125 void __init init_IRQ(void)
127 /* Any external intc can be setup here */
128 if (machine_desc->init_irq)
129 machine_desc->init_irq();
131 /* process the entire interrupt tree in one go */
135 /* Master CPU can initialize it's side of IPI */
136 if (machine_desc->init_smp)
137 machine_desc->init_smp(smp_processor_id());
142 * "C" Entry point for any ARC ISR, called from low level vector handler
143 * @irq is the vector number read from ICAUSE reg of on-chip intc
145 void arch_do_IRQ(unsigned int irq, struct pt_regs *regs)
147 struct pt_regs *old_regs = set_irq_regs(regs);
150 generic_handle_irq(irq);
152 set_irq_regs(old_regs);
155 int __init get_hw_config_num_irq(void)
157 uint32_t val = read_aux_reg(ARC_REG_VECBASE_BCR);
159 switch (val & 0x03) {
174 * arch_local_irq_enable - Enable interrupts.
176 * 1. Explicitly called to re-enable interrupts
177 * 2. Implicitly called from spin_unlock_irq, write_unlock_irq etc
178 * which maybe in hard ISR itself
180 * Semantics of this function change depending on where it is called from:
182 * -If called from hard-ISR, it must not invert interrupt priorities
183 * e.g. suppose TIMER is high priority (Level 2) IRQ
184 * Time hard-ISR, timer_interrupt( ) calls spin_unlock_irq several times.
185 * Here local_irq_enable( ) shd not re-enable lower priority interrupts
186 * -If called from soft-ISR, it must re-enable all interrupts
187 * soft ISR are low prioity jobs which can be very slow, thus all IRQs
188 * must be enabled while they run.
189 * Now hardware context wise we may still be in L2 ISR (not done rtie)
190 * still we must re-enable both L1 and L2 IRQs
191 * Another twist is prev scenario with flow being
192 * L1 ISR ==> interrupted by L2 ISR ==> L2 soft ISR
193 * here we must not re-enable Ll as prev Ll Interrupt's h/w context will get
194 * over-written (this is deficiency in ARC700 Interrupt mechanism)
197 #ifdef CONFIG_ARC_COMPACT_IRQ_LEVELS /* Complex version for 2 IRQ levels */
199 void arch_local_irq_enable(void)
203 flags = arch_local_save_flags();
205 /* Allow both L1 and L2 at the onset */
206 flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
208 /* Called from hard ISR (between irq_enter and irq_exit) */
211 /* If in L2 ISR, don't re-enable any further IRQs as this can
212 * cause IRQ priorities to get upside down. e.g. it could allow
213 * L1 be taken while in L2 hard ISR which is wrong not only in
214 * theory, it can also cause the dreaded L1-L2-L1 scenario
216 if (flags & STATUS_A2_MASK)
217 flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK);
219 /* Even if in L1 ISR, allowe Higher prio L2 IRQs */
220 else if (flags & STATUS_A1_MASK)
221 flags &= ~(STATUS_E1_MASK);
224 /* called from soft IRQ, ideally we want to re-enable all levels */
226 else if (in_softirq()) {
228 /* However if this is case of L1 interrupted by L2,
229 * re-enabling both may cause whaco L1-L2-L1 scenario
230 * because ARC700 allows level 1 to interrupt an active L2 ISR
231 * Thus we disable both
232 * However some code, executing in soft ISR wants some IRQs
233 * to be enabled so we re-enable L2 only
235 * How do we determine L1 intr by L2
236 * -A2 is set (means in L2 ISR)
237 * -E1 is set in this ISR's pt_regs->status32 which is
238 * saved copy of status32_l2 when l2 ISR happened
240 struct pt_regs *pt = get_irq_regs();
241 if ((flags & STATUS_A2_MASK) && pt &&
242 (pt->status32 & STATUS_A1_MASK)) {
243 /*flags &= ~(STATUS_E1_MASK | STATUS_E2_MASK); */
244 flags &= ~(STATUS_E1_MASK);
248 arch_local_irq_restore(flags);
251 #else /* ! CONFIG_ARC_COMPACT_IRQ_LEVELS */
254 * Simpler version for only 1 level of interrupt
255 * Here we only Worry about Level 1 Bits
257 void arch_local_irq_enable(void)
262 * ARC IDE Drivers tries to re-enable interrupts from hard-isr
263 * context which is simply wrong
266 WARN_ONCE(1, "IRQ enabled from hard-isr");
270 flags = arch_local_save_flags();
271 flags |= (STATUS_E1_MASK | STATUS_E2_MASK);
272 arch_local_irq_restore(flags);
275 EXPORT_SYMBOL(arch_local_irq_enable);