2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
9 * -sched_clock( ) no longer jiffies based. Uses the same clocksource
12 * Rajeshwarr/Vineetg: Mar 2008
13 * -Implemented CONFIG_GENERIC_TIME (rather deleted arch specific code)
14 * for arch independent gettimeofday()
15 * -Implemented CONFIG_GENERIC_CLOCKEVENTS as base for hrtimers
17 * Vineetg: Mar 2008: Forked off from time.c which now is time-jiff.c
20 /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1
21 * Each can programmed to go from @count to @limit and optionally
22 * interrupt when that happens.
23 * A write to Control Register clears the Interrupt
25 * We've designated TIMER0 for events (clockevents)
26 * while TIMER1 for free running (clocksource)
28 * Newer ARC700 cores have 64bit clk fetching RTSC insn, preferred over TIMER1
31 #include <linux/spinlock.h>
32 #include <linux/interrupt.h>
33 #include <linux/module.h>
34 #include <linux/sched.h>
35 #include <linux/kernel.h>
36 #include <linux/time.h>
37 #include <linux/init.h>
38 #include <linux/timex.h>
39 #include <linux/profile.h>
40 #include <linux/clocksource.h>
41 #include <linux/clockchips.h>
43 #include <asm/arcregs.h>
45 #include <asm/mach_desc.h>
47 /* Timer related Aux registers */
48 #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
49 #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
50 #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
51 #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
52 #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
53 #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
55 #define TIMER_CTRL_IE (1 << 0) /* Interupt when Count reachs limit */
56 #define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
58 #define ARC_TIMER_MAX 0xFFFFFFFF
60 /********** Clock Source Device *********/
62 #ifdef CONFIG_ARC_HAS_RTSC
64 int arc_counter_setup(void)
67 * For SMP this needs to be 0. However Kconfig glue doesn't
68 * enable this option for SMP configs
73 static cycle_t arc_counter_read(struct clocksource *cs)
77 #ifdef CONFIG_CPU_BIG_ENDIAN
78 struct { u32 high, low; };
80 struct { u32 low, high; };
85 flags = arch_local_irq_save();
88 " .extCoreRegister tsch, 58, r, cannot_shortcut \n"
91 : "=r" (stamp.low), "=r" (stamp.high));
93 arch_local_irq_restore(flags);
98 static struct clocksource arc_counter = {
101 .read = arc_counter_read,
102 .mask = CLOCKSOURCE_MASK(32),
103 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
106 #else /* !CONFIG_ARC_HAS_RTSC */
108 static bool is_usable_as_clocksource(void)
118 * set 32bit TIMER1 to keep counting monotonically and wraparound
120 int arc_counter_setup(void)
122 write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX);
123 write_aux_reg(ARC_REG_TIMER1_CNT, 0);
124 write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
126 return is_usable_as_clocksource();
129 static cycle_t arc_counter_read(struct clocksource *cs)
131 return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT);
134 static struct clocksource arc_counter = {
135 .name = "ARC Timer1",
137 .read = arc_counter_read,
138 .mask = CLOCKSOURCE_MASK(32),
139 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
144 /********** Clock Event Device *********/
147 * Arm the timer to interrupt after @limit cycles
148 * The distinction for oneshot/periodic is done in arc_event_timer_ack() below
150 static void arc_timer_event_setup(unsigned int limit)
152 write_aux_reg(ARC_REG_TIMER0_LIMIT, limit);
153 write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */
155 write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
159 static int arc_clkevent_set_next_event(unsigned long delta,
160 struct clock_event_device *dev)
162 arc_timer_event_setup(delta);
166 static void arc_clkevent_set_mode(enum clock_event_mode mode,
167 struct clock_event_device *dev)
170 case CLOCK_EVT_MODE_PERIODIC:
171 arc_timer_event_setup(arc_get_core_freq() / HZ);
173 case CLOCK_EVT_MODE_ONESHOT:
182 static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
183 .name = "ARC Timer0",
184 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
185 .mode = CLOCK_EVT_MODE_UNUSED,
187 .irq = TIMER0_IRQ, /* hardwired, no need for resources */
188 .set_next_event = arc_clkevent_set_next_event,
189 .set_mode = arc_clkevent_set_mode,
192 static irqreturn_t timer_irq_handler(int irq, void *dev_id)
195 * Note that generic IRQ core could have passed @evt for @dev_id if
196 * irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
198 struct clock_event_device *evt = this_cpu_ptr(&arc_clockevent_device);
199 int irq_reenable = evt->mode == CLOCK_EVT_MODE_PERIODIC;
202 * Any write to CTRL reg ACks the interrupt, we rewrite the
203 * Count when [N]ot [H]alted bit.
204 * And re-arm it if perioid by [I]nterrupt [E]nable bit
206 write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
208 evt->event_handler(evt);
213 static struct irqaction arc_timer_irq = {
214 .name = "Timer0 (clock-evt-dev)",
215 .flags = IRQF_TIMER | IRQF_PERCPU,
216 .handler = timer_irq_handler,
220 * Setup the local event timer for @cpu
222 void arc_local_timer_setup(unsigned int cpu)
224 struct clock_event_device *clk = &per_cpu(arc_clockevent_device, cpu);
226 clk->cpumask = cpumask_of(cpu);
227 clockevents_config_and_register(clk, arc_get_core_freq(),
231 * setup the per-cpu timer IRQ handler - for all cpus
232 * For non boot CPU explicitly unmask at intc
233 * setup_irq() -> .. -> irq_startup() already does this on boot-cpu
236 setup_irq(TIMER0_IRQ, &arc_timer_irq);
238 arch_unmask_irq(TIMER0_IRQ);
242 * Called from start_kernel() - boot CPU only
244 * -Sets up h/w timers as applicable on boot cpu
245 * -Also sets up any global state needed for timer subsystem:
246 * - for "counting" timer, registers a clocksource, usable across CPUs
247 * (provided that underlying counter h/w is synchronized across cores)
248 * - for "event" timer, sets up TIMER0 IRQ (as that is platform agnostic)
250 void __init time_init(void)
253 * sets up the timekeeping free-flowing counter which also returns
254 * whether the counter is usable as clocksource
256 if (arc_counter_setup())
258 * CLK upto 4.29 GHz can be safely represented in 32 bits
259 * because Max 32 bit number is 4,294,967,295
261 clocksource_register_hz(&arc_counter, arc_get_core_freq());
263 /* sets up the periodic event timer */
264 arc_local_timer_setup(smp_processor_id());
266 if (machine_desc->init_time)
267 machine_desc->init_time();