2 * ARC700 VIPT Cache Management
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * vineetg: May 2011: for Non-aliasing VIPT D-cache following can be NOPs
11 * -flush_cache_dup_mm (fork)
12 * -likewise for flush_cache_mm (exit/execve)
13 * -likewise for flush_cache_range,flush_cache_page (munmap, exit, COW-break)
16 * -Now that MMU can support larger pg sz (16K), the determiniation of
17 * aliasing shd not be based on assumption of 8k pg
20 * -optimised version of flush_icache_range( ) for making I/D coherent
21 * when vaddr is available (agnostic of num of aliases)
24 * -Added documentation about I-cache aliasing on ARC700 and the way it
25 * was handled up until MMU V2.
26 * -Spotted a three year old bug when killing the 4 aliases, which needs
27 * bottom 2 bits, so we need to do paddr | {0x00, 0x01, 0x02, 0x03}
28 * instead of paddr | {0x00, 0x01, 0x10, 0x11}
29 * (Rajesh you owe me one now)
32 * -Off-by-one error when computing num_of_lines to flush
33 * This broke signal handling with bionic which uses synthetic sigret stub
36 * -GCC can't generate ZOL for core cache flush loops.
37 * Conv them into iterations based as opposed to while (start < end) types
40 * -In I-cache flush routine we used to chk for aliasing for every line INV.
41 * Instead now we setup routines per cache geometry and invoke them
42 * via function pointers.
45 * -Cache Line flush routines used to flush an extra line beyond end addr
46 * because check was while (end >= start) instead of (end > start)
47 * =Some call sites had to work around by doing -1, -4 etc to end param
48 * =Some callers didnt care. This was spec bad in case of INV routines
49 * which would discard valid data (cause of the horrible ext2 bug
52 * vineetg: June 11th 2008: Fixed flush_icache_range( )
53 * -Since ARC700 caches are not coherent (I$ doesnt snoop D$) both need
54 * to be flushed, which it was not doing.
55 * -load_module( ) passes vmalloc addr (Kernel Virtual Addr) to the API,
56 * however ARC cache maintenance OPs require PHY addr. Thus need to do
58 * -Also added optimisation there, that for range > PAGE SIZE we flush the
59 * entire cache in one shot rather than line by line. For e.g. a module
60 * with Code sz 600k, old code flushed 600k worth of cache (line-by-line),
61 * while cache is only 16 or 32k.
64 #include <linux/module.h>
66 #include <linux/sched.h>
67 #include <linux/cache.h>
68 #include <linux/mmu_context.h>
69 #include <linux/syscalls.h>
70 #include <linux/uaccess.h>
71 #include <linux/pagemap.h>
72 #include <asm/cacheflush.h>
73 #include <asm/cachectl.h>
74 #include <asm/setup.h>
76 /* Instruction cache related Auxiliary registers */
77 #define ARC_REG_IC_BCR 0x77 /* Build Config reg */
78 #define ARC_REG_IC_IVIC 0x10
79 #define ARC_REG_IC_CTRL 0x11
80 #define ARC_REG_IC_IVIL 0x19
81 #if (CONFIG_ARC_MMU_VER > 2)
82 #define ARC_REG_IC_PTAG 0x1E
85 /* Bit val in IC_CTRL */
86 #define IC_CTRL_CACHE_DISABLE 0x1
88 /* Data cache related Auxiliary registers */
89 #define ARC_REG_DC_BCR 0x72 /* Build Config reg */
90 #define ARC_REG_DC_IVDC 0x47
91 #define ARC_REG_DC_CTRL 0x48
92 #define ARC_REG_DC_IVDL 0x4A
93 #define ARC_REG_DC_FLSH 0x4B
94 #define ARC_REG_DC_FLDL 0x4C
95 #if (CONFIG_ARC_MMU_VER > 2)
96 #define ARC_REG_DC_PTAG 0x5C
99 /* Bit val in DC_CTRL */
100 #define DC_CTRL_INV_MODE_FLUSH 0x40
101 #define DC_CTRL_FLUSH_STATUS 0x100
103 char *arc_cache_mumbojumbo(int c, char *buf, int len)
107 #define PR_CACHE(p, enb, str) \
110 n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \
112 n += scnprintf(buf + n, len - n, \
113 str"\t\t: (%uK) VIPT, %dway set-asc, %ub Line %s\n", \
114 TO_KB((p)->sz), (p)->assoc, (p)->line_len, \
115 enb ? "" : "DISABLED (kernel-build)"); \
118 PR_CACHE(&cpuinfo_arc700[c].icache, IS_ENABLED(CONFIG_ARC_HAS_ICACHE),
120 PR_CACHE(&cpuinfo_arc700[c].dcache, IS_ENABLED(CONFIG_ARC_HAS_DCACHE),
127 * Read the Cache Build Confuration Registers, Decode them and save into
128 * the cpuinfo structure for later use.
129 * No Validation done here, simply read/convert the BCRs
131 void read_decode_cache_bcr(void)
133 struct cpuinfo_arc_cache *p_ic, *p_dc;
134 unsigned int cpu = smp_processor_id();
136 #ifdef CONFIG_CPU_BIG_ENDIAN
137 unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
139 unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
143 p_ic = &cpuinfo_arc700[cpu].icache;
144 READ_BCR(ARC_REG_IC_BCR, ibcr);
146 BUG_ON(ibcr.config != 3);
147 p_ic->assoc = 2; /* Fixed to 2w set assoc */
148 p_ic->line_len = 8 << ibcr.line_len;
149 p_ic->sz = 0x200 << ibcr.sz;
150 p_ic->ver = ibcr.ver;
152 p_dc = &cpuinfo_arc700[cpu].dcache;
153 READ_BCR(ARC_REG_DC_BCR, dbcr);
155 BUG_ON(dbcr.config != 2);
156 p_dc->assoc = 4; /* Fixed to 4w set assoc */
157 p_dc->line_len = 16 << dbcr.line_len;
158 p_dc->sz = 0x200 << dbcr.sz;
159 p_dc->ver = dbcr.ver;
163 * 1. Validate the Cache Geomtery (compile time config matches hardware)
164 * 2. If I-cache suffers from aliasing, setup work arounds (difft flush rtn)
165 * (aliasing D-cache configurations are not supported YET)
166 * 3. Enable the Caches, setup default flush mode for D-Cache
167 * 3. Calculate the SHMLBA used by user space
169 void arc_cache_init(void)
171 unsigned int cpu = smp_processor_id();
172 struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
173 struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache;
174 unsigned int dcache_does_alias, temp;
177 printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
182 #ifdef CONFIG_ARC_HAS_ICACHE
183 /* 1. Confirm some of I-cache params which Linux assumes */
184 if (ic->line_len != L1_CACHE_BYTES)
185 panic("Cache H/W doesn't match kernel Config");
187 if (ic->ver != CONFIG_ARC_MMU_VER)
188 panic("Cache ver doesn't match MMU ver\n");
191 /* Enable/disable I-Cache */
192 temp = read_aux_reg(ARC_REG_IC_CTRL);
194 #ifdef CONFIG_ARC_HAS_ICACHE
195 temp &= ~IC_CTRL_CACHE_DISABLE;
197 temp |= IC_CTRL_CACHE_DISABLE;
200 write_aux_reg(ARC_REG_IC_CTRL, temp);
206 #ifdef CONFIG_ARC_HAS_DCACHE
207 if (dc->line_len != L1_CACHE_BYTES)
208 panic("Cache H/W doesn't match kernel Config");
210 /* check for D-Cache aliasing */
211 dcache_does_alias = (dc->sz / dc->assoc) > PAGE_SIZE;
213 if (dcache_does_alias && !cache_is_vipt_aliasing())
214 panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n");
215 else if (!dcache_does_alias && cache_is_vipt_aliasing())
216 panic("Don't need CONFIG_ARC_CACHE_VIPT_ALIASING\n");
219 /* Set the default Invalidate Mode to "simpy discard dirty lines"
220 * as this is more frequent then flush before invalidate
221 * Ofcourse we toggle this default behviour when desired
223 temp = read_aux_reg(ARC_REG_DC_CTRL);
224 temp &= ~DC_CTRL_INV_MODE_FLUSH;
226 #ifdef CONFIG_ARC_HAS_DCACHE
227 /* Enable D-Cache: Clear Bit 0 */
228 write_aux_reg(ARC_REG_DC_CTRL, temp & ~IC_CTRL_CACHE_DISABLE);
231 write_aux_reg(ARC_REG_DC_FLSH, 0x1);
232 /* Disable D cache */
233 write_aux_reg(ARC_REG_DC_CTRL, temp | IC_CTRL_CACHE_DISABLE);
241 #define OP_FLUSH_N_INV 0x3
242 #define OP_INV_IC 0x4
245 * Common Helper for Line Operations on {I,D}-Cache
247 static inline void __cache_line_loop(unsigned long paddr, unsigned long vaddr,
248 unsigned long sz, const int cacheop)
250 unsigned int aux_cmd, aux_tag;
252 const int full_page_op = __builtin_constant_p(sz) && sz == PAGE_SIZE;
254 if (cacheop == OP_INV_IC) {
255 aux_cmd = ARC_REG_IC_IVIL;
256 #if (CONFIG_ARC_MMU_VER > 2)
257 aux_tag = ARC_REG_IC_PTAG;
261 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
262 aux_cmd = cacheop & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL;
263 #if (CONFIG_ARC_MMU_VER > 2)
264 aux_tag = ARC_REG_DC_PTAG;
268 /* Ensure we properly floor/ceil the non-line aligned/sized requests
269 * and have @paddr - aligned to cache line and integral @num_lines.
270 * This however can be avoided for page sized since:
271 * -@paddr will be cache-line aligned already (being page aligned)
272 * -@sz will be integral multiple of line size (being page sized).
275 sz += paddr & ~CACHE_LINE_MASK;
276 paddr &= CACHE_LINE_MASK;
277 vaddr &= CACHE_LINE_MASK;
280 num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES);
282 #if (CONFIG_ARC_MMU_VER <= 2)
283 /* MMUv2 and before: paddr contains stuffed vaddrs bits */
284 paddr |= (vaddr >> PAGE_SHIFT) & 0x1F;
286 /* if V-P const for loop, PTAG can be written once outside loop */
288 write_aux_reg(aux_tag, paddr);
291 while (num_lines-- > 0) {
292 #if (CONFIG_ARC_MMU_VER > 2)
293 /* MMUv3, cache ops require paddr seperately */
295 write_aux_reg(aux_tag, paddr);
296 paddr += L1_CACHE_BYTES;
299 write_aux_reg(aux_cmd, vaddr);
300 vaddr += L1_CACHE_BYTES;
302 write_aux_reg(aux_cmd, paddr);
303 paddr += L1_CACHE_BYTES;
308 #ifdef CONFIG_ARC_HAS_DCACHE
310 /***************************************************************
311 * Machine specific helpers for Entire D-Cache or Per Line ops
314 static inline void wait_for_flush(void)
316 while (read_aux_reg(ARC_REG_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
321 * Operation on Entire D-Cache
322 * @cacheop = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV}
323 * Note that constant propagation ensures all the checks are gone
326 static inline void __dc_entire_op(const int cacheop)
328 unsigned int tmp = tmp;
331 if (cacheop == OP_FLUSH_N_INV) {
332 /* Dcache provides 2 cmd: FLUSH or INV
333 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
334 * flush-n-inv is achieved by INV cmd but with IM=1
335 * Default INV sub-mode is DISCARD, which needs to be toggled
337 tmp = read_aux_reg(ARC_REG_DC_CTRL);
338 write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH);
341 if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
342 aux = ARC_REG_DC_IVDC;
344 aux = ARC_REG_DC_FLSH;
346 write_aux_reg(aux, 0x1);
348 if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */
351 /* Switch back the DISCARD ONLY Invalidate mode */
352 if (cacheop == OP_FLUSH_N_INV)
353 write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH);
356 /* For kernel mappings cache operation: index is same as paddr */
357 #define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op)
360 * D-Cache : Per Line INV (discard or wback+discard) or FLUSH (wback)
362 static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr,
363 unsigned long sz, const int cacheop)
365 unsigned long flags, tmp = tmp;
367 local_irq_save(flags);
369 if (cacheop == OP_FLUSH_N_INV) {
371 * Dcache provides 2 cmd: FLUSH or INV
372 * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE
373 * flush-n-inv is achieved by INV cmd but with IM=1
374 * Default INV sub-mode is DISCARD, which needs to be toggled
376 tmp = read_aux_reg(ARC_REG_DC_CTRL);
377 write_aux_reg(ARC_REG_DC_CTRL, tmp | DC_CTRL_INV_MODE_FLUSH);
380 __cache_line_loop(paddr, vaddr, sz, cacheop);
382 if (cacheop & OP_FLUSH) /* flush / flush-n-inv both wait */
385 /* Switch back the DISCARD ONLY Invalidate mode */
386 if (cacheop == OP_FLUSH_N_INV)
387 write_aux_reg(ARC_REG_DC_CTRL, tmp & ~DC_CTRL_INV_MODE_FLUSH);
389 local_irq_restore(flags);
394 #define __dc_entire_op(cacheop)
395 #define __dc_line_op(paddr, vaddr, sz, cacheop)
396 #define __dc_line_op_k(paddr, sz, cacheop)
398 #endif /* CONFIG_ARC_HAS_DCACHE */
401 #ifdef CONFIG_ARC_HAS_ICACHE
404 * I-Cache Aliasing in ARC700 VIPT caches
406 * ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag.
407 * The orig Cache Management Module "CDU" only required paddr to invalidate a
408 * certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry.
409 * Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching
410 * the exact same line.
412 * However for larger Caches (way-size > page-size) - i.e. in Aliasing config,
413 * paddr alone could not be used to correctly index the cache.
416 * MMU v1/v2 (Fixed Page Size 8k)
418 * The solution was to provide CDU with these additonal vaddr bits. These
419 * would be bits [x:13], x would depend on cache-geometry, 13 comes from
420 * standard page size of 8k.
421 * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits
422 * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the
423 * orig 5 bits of paddr were anyways ignored by CDU line ops, as they
424 * represent the offset within cache-line. The adv of using this "clumsy"
425 * interface for additional info was no new reg was needed in CDU programming
428 * 17:13 represented the max num of bits passable, actual bits needed were
429 * fewer, based on the num-of-aliases possible.
430 * -for 2 alias possibility, only bit 13 needed (32K cache)
431 * -for 4 alias possibility, bits 14:13 needed (64K cache)
436 * This ver of MMU supports variable page sizes (1k-16k): although Linux will
437 * only support 8k (default), 16k and 4k.
438 * However from hardware perspective, smaller page sizes aggrevate aliasing
439 * meaning more vaddr bits needed to disambiguate the cache-line-op ;
440 * the existing scheme of piggybacking won't work for certain configurations.
441 * Two new registers IC_PTAG and DC_PTAG inttoduced.
442 * "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs
445 /***********************************************************
446 * Machine specific helper for per line I-Cache invalidate.
448 static void __ic_line_inv_vaddr(unsigned long paddr, unsigned long vaddr,
453 local_irq_save(flags);
454 __cache_line_loop(paddr, vaddr, sz, OP_INV_IC);
455 local_irq_restore(flags);
458 static inline void __ic_entire_inv(void)
460 write_aux_reg(ARC_REG_IC_IVIC, 1);
461 read_aux_reg(ARC_REG_IC_CTRL); /* blocks */
466 #define __ic_entire_inv()
467 #define __ic_line_inv_vaddr(pstart, vstart, sz)
469 #endif /* CONFIG_ARC_HAS_ICACHE */
472 /***********************************************************
477 * Handle cache congruency of kernel and userspace mappings of page when kernel
478 * writes-to/reads-from
480 * The idea is to defer flushing of kernel mapping after a WRITE, possible if:
481 * -dcache is NOT aliasing, hence any U/K-mappings of page are congruent
482 * -U-mapping doesn't exist yet for page (finalised in update_mmu_cache)
483 * -In SMP, if hardware caches are coherent
485 * There's a corollary case, where kernel READs from a userspace mapped page.
486 * If the U-mapping is not congruent to to K-mapping, former needs flushing.
488 void flush_dcache_page(struct page *page)
490 struct address_space *mapping;
492 if (!cache_is_vipt_aliasing()) {
493 clear_bit(PG_dc_clean, &page->flags);
497 /* don't handle anon pages here */
498 mapping = page_mapping(page);
503 * pagecache page, file not yet mapped to userspace
504 * Make a note that K-mapping is dirty
506 if (!mapping_mapped(mapping)) {
507 clear_bit(PG_dc_clean, &page->flags);
508 } else if (page_mapped(page)) {
510 /* kernel reading from page with U-mapping */
511 void *paddr = page_address(page);
512 unsigned long vaddr = page->index << PAGE_CACHE_SHIFT;
514 if (addr_not_cache_congruent(paddr, vaddr))
515 __flush_dcache_page(paddr, vaddr);
518 EXPORT_SYMBOL(flush_dcache_page);
521 void dma_cache_wback_inv(unsigned long start, unsigned long sz)
523 __dc_line_op_k(start, sz, OP_FLUSH_N_INV);
525 EXPORT_SYMBOL(dma_cache_wback_inv);
527 void dma_cache_inv(unsigned long start, unsigned long sz)
529 __dc_line_op_k(start, sz, OP_INV);
531 EXPORT_SYMBOL(dma_cache_inv);
533 void dma_cache_wback(unsigned long start, unsigned long sz)
535 __dc_line_op_k(start, sz, OP_FLUSH);
537 EXPORT_SYMBOL(dma_cache_wback);
540 * This is API for making I/D Caches consistent when modifying
541 * kernel code (loadable modules, kprobes, kgdb...)
542 * This is called on insmod, with kernel virtual address for CODE of
543 * the module. ARC cache maintenance ops require PHY address thus we
544 * need to convert vmalloc addr to PHY addr
546 void flush_icache_range(unsigned long kstart, unsigned long kend)
548 unsigned int tot_sz, off, sz;
549 unsigned long phy, pfn;
551 /* printk("Kernel Cache Cohenercy: %lx to %lx\n",kstart, kend); */
553 /* This is not the right API for user virtual address */
554 if (kstart < TASK_SIZE) {
555 BUG_ON("Flush icache range for user virtual addr space");
559 /* Shortcut for bigger flush ranges.
560 * Here we don't care if this was kernel virtual or phy addr
562 tot_sz = kend - kstart;
563 if (tot_sz > PAGE_SIZE) {
568 /* Case: Kernel Phy addr (0x8000_0000 onwards) */
569 if (likely(kstart > PAGE_OFFSET)) {
571 * The 2nd arg despite being paddr will be used to index icache
572 * This is OK since no alternate virtual mappings will exist
573 * given the callers for this case: kprobe/kgdb in built-in
576 __sync_icache_dcache(kstart, kstart, kend - kstart);
581 * Case: Kernel Vaddr (0x7000_0000 to 0x7fff_ffff)
582 * (1) ARC Cache Maintenance ops only take Phy addr, hence special
583 * handling of kernel vaddr.
585 * (2) Despite @tot_sz being < PAGE_SIZE (bigger cases handled already),
586 * it still needs to handle a 2 page scenario, where the range
587 * straddles across 2 virtual pages and hence need for loop
590 off = kstart % PAGE_SIZE;
591 pfn = vmalloc_to_pfn((void *)kstart);
592 phy = (pfn << PAGE_SHIFT) + off;
593 sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off);
594 __sync_icache_dcache(phy, kstart, sz);
601 * General purpose helper to make I and D cache lines consistent.
602 * @paddr is phy addr of region
603 * @vaddr is typically user vaddr (breakpoint) or kernel vaddr (vmalloc)
604 * However in one instance, when called by kprobe (for a breakpt in
605 * builtin kernel code) @vaddr will be paddr only, meaning CDU operation will
606 * use a paddr to index the cache (despite VIPT). This is fine since since a
607 * builtin kernel page will not have any virtual mappings.
608 * kprobe on loadable module will be kernel vaddr.
610 void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len)
614 local_irq_save(flags);
615 __ic_line_inv_vaddr(paddr, vaddr, len);
616 __dc_line_op(paddr, vaddr, len, OP_FLUSH_N_INV);
617 local_irq_restore(flags);
620 /* wrapper to compile time eliminate alignment checks in flush loop */
621 void __inv_icache_page(unsigned long paddr, unsigned long vaddr)
623 __ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE);
627 * wrapper to clearout kernel or userspace mappings of a page
628 * For kernel mappings @vaddr == @paddr
630 void ___flush_dcache_page(unsigned long paddr, unsigned long vaddr)
632 __dc_line_op(paddr, vaddr & PAGE_MASK, PAGE_SIZE, OP_FLUSH_N_INV);
635 noinline void flush_cache_all(void)
639 local_irq_save(flags);
642 __dc_entire_op(OP_FLUSH_N_INV);
644 local_irq_restore(flags);
648 #ifdef CONFIG_ARC_CACHE_VIPT_ALIASING
650 void flush_cache_mm(struct mm_struct *mm)
655 void flush_cache_page(struct vm_area_struct *vma, unsigned long u_vaddr,
658 unsigned int paddr = pfn << PAGE_SHIFT;
660 u_vaddr &= PAGE_MASK;
662 ___flush_dcache_page(paddr, u_vaddr);
664 if (vma->vm_flags & VM_EXEC)
665 __inv_icache_page(paddr, u_vaddr);
668 void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
674 void flush_anon_page(struct vm_area_struct *vma, struct page *page,
675 unsigned long u_vaddr)
677 /* TBD: do we really need to clear the kernel mapping */
678 __flush_dcache_page(page_address(page), u_vaddr);
679 __flush_dcache_page(page_address(page), page_address(page));
685 void copy_user_highpage(struct page *to, struct page *from,
686 unsigned long u_vaddr, struct vm_area_struct *vma)
688 void *kfrom = page_address(from);
689 void *kto = page_address(to);
690 int clean_src_k_mappings = 0;
693 * If SRC page was already mapped in userspace AND it's U-mapping is
694 * not congruent with K-mapping, sync former to physical page so that
695 * K-mapping in memcpy below, sees the right data
697 * Note that while @u_vaddr refers to DST page's userspace vaddr, it is
698 * equally valid for SRC page as well
700 if (page_mapped(from) && addr_not_cache_congruent(kfrom, u_vaddr)) {
701 __flush_dcache_page(kfrom, u_vaddr);
702 clean_src_k_mappings = 1;
705 copy_page(kto, kfrom);
708 * Mark DST page K-mapping as dirty for a later finalization by
709 * update_mmu_cache(). Although the finalization could have been done
710 * here as well (given that both vaddr/paddr are available).
711 * But update_mmu_cache() already has code to do that for other
712 * non copied user pages (e.g. read faults which wire in pagecache page
715 clear_bit(PG_dc_clean, &to->flags);
718 * if SRC was already usermapped and non-congruent to kernel mapping
719 * sync the kernel mapping back to physical page
721 if (clean_src_k_mappings) {
722 __flush_dcache_page(kfrom, kfrom);
723 set_bit(PG_dc_clean, &from->flags);
725 clear_bit(PG_dc_clean, &from->flags);
729 void clear_user_page(void *to, unsigned long u_vaddr, struct page *page)
732 clear_bit(PG_dc_clean, &page->flags);
736 /**********************************************************************
737 * Explicit Cache flush request from user space via syscall
738 * Needed for JITs which generate code on the fly
740 SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags)
742 /* TBD: optimize this */