2 # Copyright (C) 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4 # This program is free software; you can redistribute it and/or modify
5 # it under the terms of the GNU General Public License version 2 as
6 # published by the Free Software Foundation.
9 if ARC_PLAT_FPGA_LEGACY
13 config ARC_BOARD_ANGEL4
15 select ISS_SMP_EXTN if SMP
17 ARC Angel4 FPGA Ref Platform (Xilinx Virtex Based)
19 config ARC_BOARD_ML509
22 ARC ML509 FPGA Ref Platform (Xilinx Virtex-5 Based)
25 bool "ARC SMP Extensions (ISS Models only)"
28 select ARC_HAS_COH_RTSC
30 SMP Extensions to ARC700, in a "simulation only" Model, supported in
31 ARC ISS (Instruction Set Simulator).
32 The SMP extensions include:
33 -IDU (Interrupt Distribution Unit)
34 -XTL (To enable CPU start/stop/set-PC for another CPU)
35 It doesn't provide coherent Caches and/or Atomic Ops (LLOCK/SCOND)
39 config ARC_SERIAL_BAUD
42 depends on SERIAL_ARC || SERIAL_ARC_CONSOLE
44 Baud rate for the ARC UART
46 menuconfig ARC_HAS_BVCI_LAT_UNIT
47 bool "BVCI Bus Latency Unit"
48 depends on ARC_BOARD_ML509 || ARC_BOARD_ANGEL4
50 IP to add artifical latency to BVCI Bus Based FPGA builds.
51 The default latency (even worst case) for FPGA is non-realistic
52 (~10 SDRAM, ~5 SSRAM).
55 hex "Latency Unit(s) Bitmap"
57 depends on ARC_HAS_BVCI_LAT_UNIT
59 There are multiple Latency Units corresponding to the many
60 interfaces of the system bus arbiter (both CPU side as well as
62 To add latency to ALL memory transaction, choose Unit 0, otherwise
63 for finer grainer - interface wise latency, specify a bitmap (1 bit
64 per unit) of all units. e.g. 1,2,12 will be 0x1003
66 Unit 0 - System Arb and Mem Controller
67 Unit 1 - I$ and System Bus
68 Unit 2 - D$ and System Bus
70 Unit 12 - IDE Disk controller and System Bus
72 config BVCI_LAT_CYCLES
73 int "Latency Value in cycles"
76 depends on ARC_HAS_BVCI_LAT_UNIT