4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_STRNCPY_FROM_USER
19 select GENERIC_STRNLEN_USER
20 select HARDIRQS_SW_RESEND
22 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
24 select HAVE_ARCH_SECCOMP_FILTER
25 select HAVE_ARCH_TRACEHOOK
27 select HAVE_C_RECORDMCOUNT
28 select HAVE_DEBUG_KMEMLEAK
29 select HAVE_DMA_API_DEBUG
31 select HAVE_DMA_CONTIGUOUS if MMU
32 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
33 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
34 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
35 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
36 select HAVE_GENERIC_DMA_COHERENT
37 select HAVE_GENERIC_HARDIRQS
38 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
39 select HAVE_IDE if PCI || ISA || PCMCIA
40 select HAVE_KERNEL_GZIP
41 select HAVE_KERNEL_LZMA
42 select HAVE_KERNEL_LZO
44 select HAVE_KPROBES if !XIP_KERNEL
45 select HAVE_KRETPROBES if (HAVE_KPROBES)
47 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
48 select HAVE_PERF_EVENTS
49 select HAVE_REGS_AND_STACK_ACCESS_API
50 select HAVE_SYSCALL_TRACEPOINTS
53 select PERF_USE_VMALLOC
55 select SYS_SUPPORTS_APM_EMULATION
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select MODULES_USE_ELF_REL
58 select CLONE_BACKWARDS
59 select OLD_SIGSUSPEND3
62 The ARM series is a line of low-power-consumption RISC chip designs
63 licensed by ARM Ltd and targeted at embedded applications and
64 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
65 manufactured, but legacy ARM-based PC hardware remains popular in
66 Europe. There is an ARM Linux project with a web page at
67 <http://www.arm.linux.org.uk/>.
69 config ARM_HAS_SG_CHAIN
72 config NEED_SG_DMA_LENGTH
75 config ARM_DMA_USE_IOMMU
77 select ARM_HAS_SG_CHAIN
78 select NEED_SG_DMA_LENGTH
82 config ARM_DMA_IOMMU_ALIGNMENT
83 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
87 DMA mapping framework by default aligns all buffers to the smallest
88 PAGE_SIZE order which is greater than or equal to the requested buffer
89 size. This works well for buffers up to a few hundreds kilobytes, but
90 for larger buffers it just a waste of address space. Drivers which has
91 relatively small addressing window (like 64Mib) might run out of
92 virtual space with just a few allocations.
94 With this parameter you can specify the maximum PAGE_SIZE order for
95 DMA IOMMU buffers. Larger buffers will be aligned only to this
96 specified order. The order is expressed as a power of two multiplied
104 config MIGHT_HAVE_PCI
107 config SYS_SUPPORTS_APM_EMULATION
115 select GENERIC_ALLOCATOR
126 The Extended Industry Standard Architecture (EISA) bus was
127 developed as an open alternative to the IBM MicroChannel bus.
129 The EISA bus provided some of the features of the IBM MicroChannel
130 bus while maintaining backward compatibility with cards made for
131 the older ISA bus. The EISA bus saw limited use between 1988 and
132 1995 when it was made obsolete by the PCI bus.
134 Say Y here if you are building a kernel for an EISA-based machine.
141 config STACKTRACE_SUPPORT
145 config HAVE_LATENCYTOP_SUPPORT
150 config LOCKDEP_SUPPORT
154 config TRACE_IRQFLAGS_SUPPORT
158 config RWSEM_GENERIC_SPINLOCK
162 config RWSEM_XCHGADD_ALGORITHM
165 config ARCH_HAS_ILOG2_U32
168 config ARCH_HAS_ILOG2_U64
171 config ARCH_HAS_CPUFREQ
174 Internal node to signify that the ARCH has CPUFREQ support
175 and that the relevant menu configurations are displayed for
178 config GENERIC_HWEIGHT
182 config GENERIC_CALIBRATE_DELAY
186 config ARCH_MAY_HAVE_PC_FDC
192 config NEED_DMA_MAP_STATE
195 config ARCH_HAS_DMA_SET_COHERENT_MASK
198 config GENERIC_ISA_DMA
204 config NEED_RET_TO_USER
212 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
213 default DRAM_BASE if REMAP_VECTORS_TO_RAM
216 The base address of exception vectors.
218 config ARM_PATCH_PHYS_VIRT
219 bool "Patch physical to virtual translations at runtime" if EMBEDDED
221 depends on !XIP_KERNEL && MMU
222 depends on !ARCH_REALVIEW || !SPARSEMEM
224 Patch phys-to-virt and virt-to-phys translation functions at
225 boot and module load time according to the position of the
226 kernel in system memory.
228 This can only be used with non-XIP MMU kernels where the base
229 of physical memory is at a 16MB boundary.
231 Only disable this option if you know that you do not require
232 this feature (eg, building a kernel for a single machine) and
233 you need to shrink the kernel to the minimal size.
235 config NEED_MACH_GPIO_H
238 Select this when mach/gpio.h is required to provide special
239 definitions for this platform. The need for mach/gpio.h should
240 be avoided when possible.
242 config NEED_MACH_IO_H
245 Select this when mach/io.h is required to provide special
246 definitions for this platform. The need for mach/io.h should
247 be avoided when possible.
249 config NEED_MACH_MEMORY_H
252 Select this when mach/memory.h is required to provide special
253 definitions for this platform. The need for mach/memory.h should
254 be avoided when possible.
257 hex "Physical address of main memory" if MMU
258 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
259 default DRAM_BASE if !MMU
261 Please provide the physical address corresponding to the
262 location of main memory in your system.
268 source "init/Kconfig"
270 source "kernel/Kconfig.freezer"
275 bool "MMU-based Paged Memory Management Support"
278 Select if you want MMU-based virtualised addressing space
279 support by paged memory management. If unsure, say 'Y'.
282 # The "ARM system type" choice list is ordered alphabetically by option
283 # text. Please add new entries in the option alphabetic order.
286 prompt "ARM system type"
287 default ARCH_VERSATILE if !MMU
288 default ARCH_MULTIPLATFORM if MMU
290 config ARCH_MULTIPLATFORM
291 bool "Allow multiple platforms to be selected"
293 select ARM_PATCH_PHYS_VIRT
296 select MULTI_IRQ_HANDLER
300 config ARCH_INTEGRATOR
301 bool "ARM Ltd. Integrator family"
302 select ARCH_HAS_CPUFREQ
305 select COMMON_CLK_VERSATILE
306 select GENERIC_CLOCKEVENTS
309 select MULTI_IRQ_HANDLER
310 select NEED_MACH_MEMORY_H
311 select PLAT_VERSATILE
313 select VERSATILE_FPGA_IRQ
315 Support for ARM's Integrator platform.
318 bool "ARM Ltd. RealView family"
319 select ARCH_WANT_OPTIONAL_GPIOLIB
321 select ARM_TIMER_SP804
323 select COMMON_CLK_VERSATILE
324 select GENERIC_CLOCKEVENTS
325 select GPIO_PL061 if GPIOLIB
327 select NEED_MACH_MEMORY_H
328 select PLAT_VERSATILE
329 select PLAT_VERSATILE_CLCD
331 This enables support for ARM Ltd RealView boards.
333 config ARCH_VERSATILE
334 bool "ARM Ltd. Versatile family"
335 select ARCH_WANT_OPTIONAL_GPIOLIB
337 select ARM_TIMER_SP804
340 select GENERIC_CLOCKEVENTS
341 select HAVE_MACH_CLKDEV
343 select PLAT_VERSATILE
344 select PLAT_VERSATILE_CLCD
345 select PLAT_VERSATILE_CLOCK
346 select VERSATILE_FPGA_IRQ
348 This enables support for ARM Ltd Versatile board.
352 select ARCH_REQUIRE_GPIOLIB
356 select NEED_MACH_GPIO_H
357 select NEED_MACH_IO_H if PCCARD
359 select PINCTRL_AT91 if USE_OF
361 This enables support for systems based on Atmel
362 AT91RM9200 and AT91SAM9* processors.
365 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
366 select ARCH_REQUIRE_GPIOLIB
371 select GENERIC_CLOCKEVENTS
372 select MULTI_IRQ_HANDLER
373 select NEED_MACH_MEMORY_H
376 Support for Cirrus Logic 711x/721x/731x based boards.
379 bool "Cortina Systems Gemini"
380 select ARCH_REQUIRE_GPIOLIB
381 select ARCH_USES_GETTIMEOFFSET
384 Support for the Cortina Systems Gemini family SoCs
388 select ARCH_USES_GETTIMEOFFSET
391 select NEED_MACH_IO_H
392 select NEED_MACH_MEMORY_H
395 This is an evaluation board for the StrongARM processor available
396 from Digital. It has limited hardware on-board, including an
397 Ethernet interface, two PCMCIA sockets, two serial ports and a
402 select ARCH_HAS_HOLES_MEMORYMODEL
403 select ARCH_REQUIRE_GPIOLIB
404 select ARCH_USES_GETTIMEOFFSET
409 select NEED_MACH_MEMORY_H
411 This enables support for the Cirrus EP93xx series of CPUs.
413 config ARCH_FOOTBRIDGE
417 select GENERIC_CLOCKEVENTS
419 select NEED_MACH_IO_H if !MMU
420 select NEED_MACH_MEMORY_H
422 Support for systems based on the DC21285 companion chip
423 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
426 bool "Freescale MXS-based"
427 select ARCH_REQUIRE_GPIOLIB
431 select GENERIC_CLOCKEVENTS
432 select HAVE_CLK_PREPARE
433 select MULTI_IRQ_HANDLER
438 Support for Freescale MXS-based family of processors
441 bool "Hilscher NetX based"
445 select GENERIC_CLOCKEVENTS
447 This enables support for systems based on the Hilscher NetX Soc
450 bool "Hynix HMS720x-based"
451 select ARCH_USES_GETTIMEOFFSET
455 This enables support for systems based on the Hynix HMS720x
460 select ARCH_SUPPORTS_MSI
462 select NEED_MACH_MEMORY_H
463 select NEED_RET_TO_USER
468 Support for Intel's IOP13XX (XScale) family of processors.
473 select ARCH_REQUIRE_GPIOLIB
475 select NEED_MACH_GPIO_H
476 select NEED_RET_TO_USER
480 Support for Intel's 80219 and IOP32X (XScale) family of
486 select ARCH_REQUIRE_GPIOLIB
488 select NEED_MACH_GPIO_H
489 select NEED_RET_TO_USER
493 Support for Intel's IOP33X (XScale) family of processors.
498 select ARCH_HAS_DMA_SET_COHERENT_MASK
499 select ARCH_REQUIRE_GPIOLIB
502 select DMABOUNCE if PCI
503 select GENERIC_CLOCKEVENTS
504 select MIGHT_HAVE_PCI
505 select NEED_MACH_IO_H
507 Support for Intel's IXP4XX (XScale) family of processors.
511 select ARCH_REQUIRE_GPIOLIB
513 select GENERIC_CLOCKEVENTS
514 select MIGHT_HAVE_PCI
517 select PLAT_ORION_LEGACY
518 select USB_ARCH_HAS_EHCI
520 Support for the Marvell Dove SoC 88AP510
523 bool "Marvell Kirkwood"
524 select ARCH_REQUIRE_GPIOLIB
526 select GENERIC_CLOCKEVENTS
530 select PINCTRL_KIRKWOOD
531 select PLAT_ORION_LEGACY
533 Support for the following Marvell Kirkwood series SoCs:
534 88F6180, 88F6192 and 88F6281.
537 bool "Marvell MV78xx0"
538 select ARCH_REQUIRE_GPIOLIB
540 select GENERIC_CLOCKEVENTS
542 select PLAT_ORION_LEGACY
544 Support for the following Marvell MV78xx0 series SoCs:
550 select ARCH_REQUIRE_GPIOLIB
552 select GENERIC_CLOCKEVENTS
554 select PLAT_ORION_LEGACY
556 Support for the following Marvell Orion 5x series SoCs:
557 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
558 Orion-2 (5281), Orion-1-90 (6183).
561 bool "Marvell PXA168/910/MMP2"
563 select ARCH_REQUIRE_GPIOLIB
565 select GENERIC_ALLOCATOR
566 select GENERIC_CLOCKEVENTS
569 select NEED_MACH_GPIO_H
574 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
577 bool "Micrel/Kendin KS8695"
578 select ARCH_REQUIRE_GPIOLIB
581 select GENERIC_CLOCKEVENTS
582 select NEED_MACH_MEMORY_H
584 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
585 System-on-Chip devices.
588 bool "Nuvoton W90X900 CPU"
589 select ARCH_REQUIRE_GPIOLIB
593 select GENERIC_CLOCKEVENTS
595 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
596 At present, the w90x900 has been renamed nuc900, regarding
597 the ARM series product line, you can login the following
598 link address to know more.
600 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
601 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
605 select ARCH_REQUIRE_GPIOLIB
610 select GENERIC_CLOCKEVENTS
613 select USB_ARCH_HAS_OHCI
616 Support for the NXP LPC32XX family of processors
620 select ARCH_HAS_CPUFREQ
621 select ARCH_REQUIRE_GPIOLIB
626 select GENERIC_CLOCKEVENTS
629 select MIGHT_HAVE_CACHE_L2X0
633 This enables support for NVIDIA Tegra based systems (Tegra APX,
634 Tegra 6xx and Tegra 2 series).
637 bool "PXA2xx/PXA3xx-based"
639 select ARCH_HAS_CPUFREQ
641 select ARCH_REQUIRE_GPIOLIB
642 select ARM_CPU_SUSPEND if PM
646 select GENERIC_CLOCKEVENTS
649 select MULTI_IRQ_HANDLER
650 select NEED_MACH_GPIO_H
654 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
658 select ARCH_REQUIRE_GPIOLIB
660 select GENERIC_CLOCKEVENTS
663 Support for Qualcomm MSM/QSD based systems. This runs on the
664 apps processor of the MSM/QSD and depends on a shared memory
665 interface to the modem processor which runs the baseband
666 stack and controls some vital subsystems
667 (clock and power control, etc).
670 bool "Renesas SH-Mobile / R-Mobile"
672 select GENERIC_CLOCKEVENTS
674 select HAVE_MACH_CLKDEV
676 select MIGHT_HAVE_CACHE_L2X0
677 select MULTI_IRQ_HANDLER
678 select NEED_MACH_MEMORY_H
681 select PM_GENERIC_DOMAINS if PM
684 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
689 select ARCH_MAY_HAVE_PC_FDC
690 select ARCH_SPARSEMEM_ENABLE
691 select ARCH_USES_GETTIMEOFFSET
694 select HAVE_PATA_PLATFORM
696 select NEED_MACH_IO_H
697 select NEED_MACH_MEMORY_H
700 On the Acorn Risc-PC, Linux can support the internal IDE disk and
701 CD-ROM interface, serial and parallel port, and the floppy drive.
705 select ARCH_HAS_CPUFREQ
707 select ARCH_REQUIRE_GPIOLIB
708 select ARCH_SPARSEMEM_ENABLE
713 select GENERIC_CLOCKEVENTS
716 select NEED_MACH_GPIO_H
717 select NEED_MACH_MEMORY_H
720 Support for StrongARM 11x0 based boards.
723 bool "Samsung S3C24XX SoCs"
724 select ARCH_HAS_CPUFREQ
725 select ARCH_USES_GETTIMEOFFSET
728 select HAVE_S3C2410_I2C if I2C
729 select HAVE_S3C2410_WATCHDOG if WATCHDOG
730 select HAVE_S3C_RTC if RTC_CLASS
731 select NEED_MACH_GPIO_H
732 select NEED_MACH_IO_H
734 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
735 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
736 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
737 Samsung SMDK2410 development board (and derivatives).
740 bool "Samsung S3C64XX"
741 select ARCH_HAS_CPUFREQ
742 select ARCH_REQUIRE_GPIOLIB
743 select ARCH_USES_GETTIMEOFFSET
748 select HAVE_S3C2410_I2C if I2C
749 select HAVE_S3C2410_WATCHDOG if WATCHDOG
751 select NEED_MACH_GPIO_H
755 select S3C_GPIO_TRACK
756 select SAMSUNG_CLKSRC
757 select SAMSUNG_GPIOLIB_4BIT
758 select SAMSUNG_IRQ_VIC_TIMER
759 select USB_ARCH_HAS_OHCI
761 Samsung S3C64XX series based systems
764 bool "Samsung S5P6440 S5P6450"
768 select GENERIC_CLOCKEVENTS
770 select HAVE_S3C2410_I2C if I2C
771 select HAVE_S3C2410_WATCHDOG if WATCHDOG
772 select HAVE_S3C_RTC if RTC_CLASS
773 select NEED_MACH_GPIO_H
775 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
779 bool "Samsung S5PC100"
780 select ARCH_USES_GETTIMEOFFSET
784 select HAVE_S3C2410_I2C if I2C
785 select HAVE_S3C2410_WATCHDOG if WATCHDOG
786 select HAVE_S3C_RTC if RTC_CLASS
787 select NEED_MACH_GPIO_H
789 Samsung S5PC100 series based systems
792 bool "Samsung S5PV210/S5PC110"
793 select ARCH_HAS_CPUFREQ
794 select ARCH_HAS_HOLES_MEMORYMODEL
795 select ARCH_SPARSEMEM_ENABLE
799 select GENERIC_CLOCKEVENTS
801 select HAVE_S3C2410_I2C if I2C
802 select HAVE_S3C2410_WATCHDOG if WATCHDOG
803 select HAVE_S3C_RTC if RTC_CLASS
804 select NEED_MACH_GPIO_H
805 select NEED_MACH_MEMORY_H
807 Samsung S5PV210/S5PC110 series based systems
810 bool "Samsung EXYNOS"
811 select ARCH_HAS_CPUFREQ
812 select ARCH_HAS_HOLES_MEMORYMODEL
813 select ARCH_SPARSEMEM_ENABLE
816 select GENERIC_CLOCKEVENTS
818 select HAVE_S3C2410_I2C if I2C
819 select HAVE_S3C2410_WATCHDOG if WATCHDOG
820 select HAVE_S3C_RTC if RTC_CLASS
821 select NEED_MACH_GPIO_H
822 select NEED_MACH_MEMORY_H
824 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
828 select ARCH_USES_GETTIMEOFFSET
832 select NEED_MACH_MEMORY_H
836 Support for the StrongARM based Digital DNARD machine, also known
837 as "Shark" (<http://www.shark-linux.de/shark.html>).
840 bool "ST-Ericsson U300 Series"
842 select ARCH_REQUIRE_GPIOLIB
844 select ARM_PATCH_PHYS_VIRT
850 select GENERIC_CLOCKEVENTS
854 Support for ST-Ericsson U300 series mobile platforms.
857 bool "ST-Ericsson U8500 Series"
859 select ARCH_HAS_CPUFREQ
860 select ARCH_REQUIRE_GPIOLIB
864 select GENERIC_CLOCKEVENTS
866 select MIGHT_HAVE_CACHE_L2X0
869 Support for ST-Ericsson's Ux500 architecture
874 select ARCH_HAS_HOLES_MEMORYMODEL
875 select ARCH_REQUIRE_GPIOLIB
877 select GENERIC_ALLOCATOR
878 select GENERIC_CLOCKEVENTS
879 select GENERIC_IRQ_CHIP
881 select NEED_MACH_GPIO_H
885 Support for TI's DaVinci platform.
890 select ARCH_HAS_CPUFREQ
891 select ARCH_HAS_HOLES_MEMORYMODEL
893 select ARCH_REQUIRE_GPIOLIB
896 select GENERIC_CLOCKEVENTS
897 select GENERIC_IRQ_CHIP
901 select NEED_MACH_IO_H if PCCARD
902 select NEED_MACH_MEMORY_H
904 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
908 menu "Multiple platform selection"
909 depends on ARCH_MULTIPLATFORM
911 comment "CPU Core family selection"
914 bool "ARMv4 based platforms (FA526, StrongARM)"
915 depends on !ARCH_MULTI_V6_V7
916 select ARCH_MULTI_V4_V5
918 config ARCH_MULTI_V4T
919 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
920 depends on !ARCH_MULTI_V6_V7
921 select ARCH_MULTI_V4_V5
924 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
925 depends on !ARCH_MULTI_V6_V7
926 select ARCH_MULTI_V4_V5
928 config ARCH_MULTI_V4_V5
932 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
933 select ARCH_MULTI_V6_V7
937 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
939 select ARCH_MULTI_V6_V7
943 config ARCH_MULTI_V6_V7
946 config ARCH_MULTI_CPU_AUTO
947 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
953 # This is sorted alphabetically by mach-* pathname. However, plat-*
954 # Kconfigs may be included either alphabetically (according to the
955 # plat- suffix) or along side the corresponding mach-* source.
957 source "arch/arm/mach-mvebu/Kconfig"
959 source "arch/arm/mach-at91/Kconfig"
961 source "arch/arm/mach-bcm/Kconfig"
963 source "arch/arm/mach-bcm2835/Kconfig"
965 source "arch/arm/mach-clps711x/Kconfig"
967 source "arch/arm/mach-cns3xxx/Kconfig"
969 source "arch/arm/mach-davinci/Kconfig"
971 source "arch/arm/mach-dove/Kconfig"
973 source "arch/arm/mach-ep93xx/Kconfig"
975 source "arch/arm/mach-footbridge/Kconfig"
977 source "arch/arm/mach-gemini/Kconfig"
979 source "arch/arm/mach-h720x/Kconfig"
981 source "arch/arm/mach-highbank/Kconfig"
983 source "arch/arm/mach-integrator/Kconfig"
985 source "arch/arm/mach-iop32x/Kconfig"
987 source "arch/arm/mach-iop33x/Kconfig"
989 source "arch/arm/mach-iop13xx/Kconfig"
991 source "arch/arm/mach-ixp4xx/Kconfig"
993 source "arch/arm/mach-kirkwood/Kconfig"
995 source "arch/arm/mach-ks8695/Kconfig"
997 source "arch/arm/mach-msm/Kconfig"
999 source "arch/arm/mach-mv78xx0/Kconfig"
1001 source "arch/arm/mach-imx/Kconfig"
1003 source "arch/arm/mach-mxs/Kconfig"
1005 source "arch/arm/mach-netx/Kconfig"
1007 source "arch/arm/mach-nomadik/Kconfig"
1009 source "arch/arm/plat-omap/Kconfig"
1011 source "arch/arm/mach-omap1/Kconfig"
1013 source "arch/arm/mach-omap2/Kconfig"
1015 source "arch/arm/mach-orion5x/Kconfig"
1017 source "arch/arm/mach-picoxcell/Kconfig"
1019 source "arch/arm/mach-pxa/Kconfig"
1020 source "arch/arm/plat-pxa/Kconfig"
1022 source "arch/arm/mach-mmp/Kconfig"
1024 source "arch/arm/mach-realview/Kconfig"
1026 source "arch/arm/mach-sa1100/Kconfig"
1028 source "arch/arm/plat-samsung/Kconfig"
1030 source "arch/arm/mach-socfpga/Kconfig"
1032 source "arch/arm/mach-spear/Kconfig"
1034 source "arch/arm/mach-s3c24xx/Kconfig"
1037 source "arch/arm/mach-s3c64xx/Kconfig"
1040 source "arch/arm/mach-s5p64x0/Kconfig"
1042 source "arch/arm/mach-s5pc100/Kconfig"
1044 source "arch/arm/mach-s5pv210/Kconfig"
1046 source "arch/arm/mach-exynos/Kconfig"
1048 source "arch/arm/mach-shmobile/Kconfig"
1050 source "arch/arm/mach-sunxi/Kconfig"
1052 source "arch/arm/mach-prima2/Kconfig"
1054 source "arch/arm/mach-tegra/Kconfig"
1056 source "arch/arm/mach-u300/Kconfig"
1058 source "arch/arm/mach-ux500/Kconfig"
1060 source "arch/arm/mach-versatile/Kconfig"
1062 source "arch/arm/mach-vexpress/Kconfig"
1063 source "arch/arm/plat-versatile/Kconfig"
1065 source "arch/arm/mach-virt/Kconfig"
1067 source "arch/arm/mach-vt8500/Kconfig"
1069 source "arch/arm/mach-w90x900/Kconfig"
1071 source "arch/arm/mach-zynq/Kconfig"
1073 # Definitions to make life easier
1079 select GENERIC_CLOCKEVENTS
1085 select GENERIC_IRQ_CHIP
1088 config PLAT_ORION_LEGACY
1095 config PLAT_VERSATILE
1098 config ARM_TIMER_SP804
1101 select HAVE_SCHED_CLOCK
1103 source arch/arm/mm/Kconfig
1107 default 16 if ARCH_EP93XX
1111 bool "Enable iWMMXt support"
1112 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1113 default y if PXA27x || PXA3xx || ARCH_MMP
1115 Enable support for iWMMXt context switching at run time if
1116 running on a CPU that supports it.
1120 depends on CPU_XSCALE
1123 config MULTI_IRQ_HANDLER
1126 Allow each machine to specify it's own IRQ handler at run time.
1129 source "arch/arm/Kconfig-nommu"
1132 config ARM_ERRATA_326103
1133 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1136 Executing a SWP instruction to read-only memory does not set bit 11
1137 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1138 treat the access as a read, preventing a COW from occurring and
1139 causing the faulting task to livelock.
1141 config ARM_ERRATA_411920
1142 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1143 depends on CPU_V6 || CPU_V6K
1145 Invalidation of the Instruction Cache operation can
1146 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1147 It does not affect the MPCore. This option enables the ARM Ltd.
1148 recommended workaround.
1150 config ARM_ERRATA_430973
1151 bool "ARM errata: Stale prediction on replaced interworking branch"
1154 This option enables the workaround for the 430973 Cortex-A8
1155 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1156 interworking branch is replaced with another code sequence at the
1157 same virtual address, whether due to self-modifying code or virtual
1158 to physical address re-mapping, Cortex-A8 does not recover from the
1159 stale interworking branch prediction. This results in Cortex-A8
1160 executing the new code sequence in the incorrect ARM or Thumb state.
1161 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1162 and also flushes the branch target cache at every context switch.
1163 Note that setting specific bits in the ACTLR register may not be
1164 available in non-secure mode.
1166 config ARM_ERRATA_458693
1167 bool "ARM errata: Processor deadlock when a false hazard is created"
1169 depends on !ARCH_MULTIPLATFORM
1171 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1172 erratum. For very specific sequences of memory operations, it is
1173 possible for a hazard condition intended for a cache line to instead
1174 be incorrectly associated with a different cache line. This false
1175 hazard might then cause a processor deadlock. The workaround enables
1176 the L1 caching of the NEON accesses and disables the PLD instruction
1177 in the ACTLR register. Note that setting specific bits in the ACTLR
1178 register may not be available in non-secure mode.
1180 config ARM_ERRATA_460075
1181 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1183 depends on !ARCH_MULTIPLATFORM
1185 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1186 erratum. Any asynchronous access to the L2 cache may encounter a
1187 situation in which recent store transactions to the L2 cache are lost
1188 and overwritten with stale memory contents from external memory. The
1189 workaround disables the write-allocate mode for the L2 cache via the
1190 ACTLR register. Note that setting specific bits in the ACTLR register
1191 may not be available in non-secure mode.
1193 config ARM_ERRATA_742230
1194 bool "ARM errata: DMB operation may be faulty"
1195 depends on CPU_V7 && SMP
1196 depends on !ARCH_MULTIPLATFORM
1198 This option enables the workaround for the 742230 Cortex-A9
1199 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1200 between two write operations may not ensure the correct visibility
1201 ordering of the two writes. This workaround sets a specific bit in
1202 the diagnostic register of the Cortex-A9 which causes the DMB
1203 instruction to behave as a DSB, ensuring the correct behaviour of
1206 config ARM_ERRATA_742231
1207 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1208 depends on CPU_V7 && SMP
1209 depends on !ARCH_MULTIPLATFORM
1211 This option enables the workaround for the 742231 Cortex-A9
1212 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1213 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1214 accessing some data located in the same cache line, may get corrupted
1215 data due to bad handling of the address hazard when the line gets
1216 replaced from one of the CPUs at the same time as another CPU is
1217 accessing it. This workaround sets specific bits in the diagnostic
1218 register of the Cortex-A9 which reduces the linefill issuing
1219 capabilities of the processor.
1221 config PL310_ERRATA_588369
1222 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1223 depends on CACHE_L2X0
1225 The PL310 L2 cache controller implements three types of Clean &
1226 Invalidate maintenance operations: by Physical Address
1227 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1228 They are architecturally defined to behave as the execution of a
1229 clean operation followed immediately by an invalidate operation,
1230 both performing to the same memory location. This functionality
1231 is not correctly implemented in PL310 as clean lines are not
1232 invalidated as a result of these operations.
1234 config ARM_ERRATA_720789
1235 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1238 This option enables the workaround for the 720789 Cortex-A9 (prior to
1239 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1240 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1241 As a consequence of this erratum, some TLB entries which should be
1242 invalidated are not, resulting in an incoherency in the system page
1243 tables. The workaround changes the TLB flushing routines to invalidate
1244 entries regardless of the ASID.
1246 config PL310_ERRATA_727915
1247 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1248 depends on CACHE_L2X0
1250 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1251 operation (offset 0x7FC). This operation runs in background so that
1252 PL310 can handle normal accesses while it is in progress. Under very
1253 rare circumstances, due to this erratum, write data can be lost when
1254 PL310 treats a cacheable write transaction during a Clean &
1255 Invalidate by Way operation.
1257 config ARM_ERRATA_743622
1258 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1260 depends on !ARCH_MULTIPLATFORM
1262 This option enables the workaround for the 743622 Cortex-A9
1263 (r2p*) erratum. Under very rare conditions, a faulty
1264 optimisation in the Cortex-A9 Store Buffer may lead to data
1265 corruption. This workaround sets a specific bit in the diagnostic
1266 register of the Cortex-A9 which disables the Store Buffer
1267 optimisation, preventing the defect from occurring. This has no
1268 visible impact on the overall performance or power consumption of the
1271 config ARM_ERRATA_751472
1272 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1274 depends on !ARCH_MULTIPLATFORM
1276 This option enables the workaround for the 751472 Cortex-A9 (prior
1277 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1278 completion of a following broadcasted operation if the second
1279 operation is received by a CPU before the ICIALLUIS has completed,
1280 potentially leading to corrupted entries in the cache or TLB.
1282 config PL310_ERRATA_753970
1283 bool "PL310 errata: cache sync operation may be faulty"
1284 depends on CACHE_PL310
1286 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1288 Under some condition the effect of cache sync operation on
1289 the store buffer still remains when the operation completes.
1290 This means that the store buffer is always asked to drain and
1291 this prevents it from merging any further writes. The workaround
1292 is to replace the normal offset of cache sync operation (0x730)
1293 by another offset targeting an unmapped PL310 register 0x740.
1294 This has the same effect as the cache sync operation: store buffer
1295 drain and waiting for all buffers empty.
1297 config ARM_ERRATA_754322
1298 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1301 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1302 r3p*) erratum. A speculative memory access may cause a page table walk
1303 which starts prior to an ASID switch but completes afterwards. This
1304 can populate the micro-TLB with a stale entry which may be hit with
1305 the new ASID. This workaround places two dsb instructions in the mm
1306 switching code so that no page table walks can cross the ASID switch.
1308 config ARM_ERRATA_754327
1309 bool "ARM errata: no automatic Store Buffer drain"
1310 depends on CPU_V7 && SMP
1312 This option enables the workaround for the 754327 Cortex-A9 (prior to
1313 r2p0) erratum. The Store Buffer does not have any automatic draining
1314 mechanism and therefore a livelock may occur if an external agent
1315 continuously polls a memory location waiting to observe an update.
1316 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1317 written polling loops from denying visibility of updates to memory.
1319 config ARM_ERRATA_364296
1320 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1321 depends on CPU_V6 && !SMP
1323 This options enables the workaround for the 364296 ARM1136
1324 r0p2 erratum (possible cache data corruption with
1325 hit-under-miss enabled). It sets the undocumented bit 31 in
1326 the auxiliary control register and the FI bit in the control
1327 register, thus disabling hit-under-miss without putting the
1328 processor into full low interrupt latency mode. ARM11MPCore
1331 config ARM_ERRATA_764369
1332 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1333 depends on CPU_V7 && SMP
1335 This option enables the workaround for erratum 764369
1336 affecting Cortex-A9 MPCore with two or more processors (all
1337 current revisions). Under certain timing circumstances, a data
1338 cache line maintenance operation by MVA targeting an Inner
1339 Shareable memory region may fail to proceed up to either the
1340 Point of Coherency or to the Point of Unification of the
1341 system. This workaround adds a DSB instruction before the
1342 relevant cache maintenance functions and sets a specific bit
1343 in the diagnostic control register of the SCU.
1345 config PL310_ERRATA_769419
1346 bool "PL310 errata: no automatic Store Buffer drain"
1347 depends on CACHE_L2X0
1349 On revisions of the PL310 prior to r3p2, the Store Buffer does
1350 not automatically drain. This can cause normal, non-cacheable
1351 writes to be retained when the memory system is idle, leading
1352 to suboptimal I/O performance for drivers using coherent DMA.
1353 This option adds a write barrier to the cpu_idle loop so that,
1354 on systems with an outer cache, the store buffer is drained
1357 config ARM_ERRATA_775420
1358 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1361 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1362 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1363 operation aborts with MMU exception, it might cause the processor
1364 to deadlock. This workaround puts DSB before executing ISB if
1365 an abort may occur on cache maintenance.
1369 source "arch/arm/common/Kconfig"
1379 Find out whether you have ISA slots on your motherboard. ISA is the
1380 name of a bus system, i.e. the way the CPU talks to the other stuff
1381 inside your box. Other bus systems are PCI, EISA, MicroChannel
1382 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1383 newer boards don't support it. If you have ISA, say Y, otherwise N.
1385 # Select ISA DMA controller support
1390 config ARCH_NO_VIRT_TO_BUS
1392 depends on !ARCH_RPC && !ARCH_NETWINDER && !ARCH_SHARK
1394 # Select ISA DMA interface
1399 bool "PCI support" if MIGHT_HAVE_PCI
1401 Find out whether you have a PCI motherboard. PCI is the name of a
1402 bus system, i.e. the way the CPU talks to the other stuff inside
1403 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1404 VESA. If you have PCI, say Y, otherwise N.
1410 config PCI_NANOENGINE
1411 bool "BSE nanoEngine PCI support"
1412 depends on SA1100_NANOENGINE
1414 Enable PCI on the BSE nanoEngine board.
1419 # Select the host bridge type
1420 config PCI_HOST_VIA82C505
1422 depends on PCI && ARCH_SHARK
1425 config PCI_HOST_ITE8152
1427 depends on PCI && MACH_ARMCORE
1431 source "drivers/pci/Kconfig"
1433 source "drivers/pcmcia/Kconfig"
1437 menu "Kernel Features"
1442 This option should be selected by machines which have an SMP-
1445 The only effect of this option is to make the SMP-related
1446 options available to the user for configuration.
1449 bool "Symmetric Multi-Processing"
1450 depends on CPU_V6K || CPU_V7
1451 depends on GENERIC_CLOCKEVENTS
1454 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1455 select USE_GENERIC_SMP_HELPERS
1457 This enables support for systems with more than one CPU. If you have
1458 a system with only one CPU, like most personal computers, say N. If
1459 you have a system with more than one CPU, say Y.
1461 If you say N here, the kernel will run on single and multiprocessor
1462 machines, but will use only one CPU of a multiprocessor machine. If
1463 you say Y here, the kernel will run on many, but not all, single
1464 processor machines. On a single processor machine, the kernel will
1465 run faster if you say N here.
1467 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1468 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1469 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1471 If you don't know what to do here, say N.
1474 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1475 depends on SMP && !XIP_KERNEL
1478 SMP kernels contain instructions which fail on non-SMP processors.
1479 Enabling this option allows the kernel to modify itself to make
1480 these instructions safe. Disabling it allows about 1K of space
1483 If you don't know what to do here, say Y.
1485 config ARM_CPU_TOPOLOGY
1486 bool "Support cpu topology definition"
1487 depends on SMP && CPU_V7
1490 Support ARM cpu topology definition. The MPIDR register defines
1491 affinity between processors which is then used to describe the cpu
1492 topology of an ARM System.
1495 bool "Multi-core scheduler support"
1496 depends on ARM_CPU_TOPOLOGY
1498 Multi-core scheduler support improves the CPU scheduler's decision
1499 making when dealing with multi-core CPU chips at a cost of slightly
1500 increased overhead in some places. If unsure say N here.
1503 bool "SMT scheduler support"
1504 depends on ARM_CPU_TOPOLOGY
1506 Improves the CPU scheduler's decision making when dealing with
1507 MultiThreading at a cost of slightly increased overhead in some
1508 places. If unsure say N here.
1513 This option enables support for the ARM system coherency unit
1515 config HAVE_ARM_ARCH_TIMER
1516 bool "Architected timer support"
1518 select ARM_ARCH_TIMER
1520 This option enables support for the ARM architected timer
1525 select CLKSRC_OF if OF
1527 This options enables support for the ARM timer and watchdog unit
1530 prompt "Memory split"
1533 Select the desired split between kernel and user memory.
1535 If you are not absolutely sure what you are doing, leave this
1539 bool "3G/1G user/kernel split"
1541 bool "2G/2G user/kernel split"
1543 bool "1G/3G user/kernel split"
1548 default 0x40000000 if VMSPLIT_1G
1549 default 0x80000000 if VMSPLIT_2G
1553 int "Maximum number of CPUs (2-32)"
1559 bool "Support for hot-pluggable CPUs"
1560 depends on SMP && HOTPLUG
1562 Say Y here to experiment with turning CPUs off and on. CPUs
1563 can be controlled through /sys/devices/system/cpu.
1566 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1569 Say Y here if you want Linux to communicate with system firmware
1570 implementing the PSCI specification for CPU-centric power
1571 management operations described in ARM document number ARM DEN
1572 0022A ("Power State Coordination Interface System Software on
1576 bool "Use local timer interrupts"
1579 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1581 Enable support for local timers on SMP platforms, rather then the
1582 legacy IPI broadcast method. Local timers allows the system
1583 accounting to be spread across the timer interval, preventing a
1584 "thundering herd" at every timer tick.
1586 # The GPIO number here must be sorted by descending number. In case of
1587 # a multiplatform kernel, we just want the highest value required by the
1588 # selected platforms.
1591 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1592 default 512 if SOC_OMAP5
1593 default 355 if ARCH_U8500
1594 default 288 if ARCH_VT8500 || ARCH_SUNXI
1595 default 264 if MACH_H4700
1598 Maximum number of GPIOs in the system.
1600 If unsure, leave the default value.
1602 source kernel/Kconfig.preempt
1606 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1607 ARCH_S5PV210 || ARCH_EXYNOS4
1608 default AT91_TIMER_HZ if ARCH_AT91
1609 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1613 def_bool HIGH_RES_TIMERS
1615 config THUMB2_KERNEL
1616 bool "Compile the kernel in Thumb-2 mode"
1617 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1619 select ARM_ASM_UNIFIED
1622 By enabling this option, the kernel will be compiled in
1623 Thumb-2 mode. A compiler/assembler that understand the unified
1624 ARM-Thumb syntax is needed.
1628 config THUMB2_AVOID_R_ARM_THM_JUMP11
1629 bool "Work around buggy Thumb-2 short branch relocations in gas"
1630 depends on THUMB2_KERNEL && MODULES
1633 Various binutils versions can resolve Thumb-2 branches to
1634 locally-defined, preemptible global symbols as short-range "b.n"
1635 branch instructions.
1637 This is a problem, because there's no guarantee the final
1638 destination of the symbol, or any candidate locations for a
1639 trampoline, are within range of the branch. For this reason, the
1640 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1641 relocation in modules at all, and it makes little sense to add
1644 The symptom is that the kernel fails with an "unsupported
1645 relocation" error when loading some modules.
1647 Until fixed tools are available, passing
1648 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1649 code which hits this problem, at the cost of a bit of extra runtime
1650 stack usage in some cases.
1652 The problem is described in more detail at:
1653 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1655 Only Thumb-2 kernels are affected.
1657 Unless you are sure your tools don't have this problem, say Y.
1659 config ARM_ASM_UNIFIED
1663 bool "Use the ARM EABI to compile the kernel"
1665 This option allows for the kernel to be compiled using the latest
1666 ARM ABI (aka EABI). This is only useful if you are using a user
1667 space environment that is also compiled with EABI.
1669 Since there are major incompatibilities between the legacy ABI and
1670 EABI, especially with regard to structure member alignment, this
1671 option also changes the kernel syscall calling convention to
1672 disambiguate both ABIs and allow for backward compatibility support
1673 (selected with CONFIG_OABI_COMPAT).
1675 To use this you need GCC version 4.0.0 or later.
1678 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1679 depends on AEABI && !THUMB2_KERNEL
1682 This option preserves the old syscall interface along with the
1683 new (ARM EABI) one. It also provides a compatibility layer to
1684 intercept syscalls that have structure arguments which layout
1685 in memory differs between the legacy ABI and the new ARM EABI
1686 (only for non "thumb" binaries). This option adds a tiny
1687 overhead to all syscalls and produces a slightly larger kernel.
1688 If you know you'll be using only pure EABI user space then you
1689 can say N here. If this option is not selected and you attempt
1690 to execute a legacy ABI binary then the result will be
1691 UNPREDICTABLE (in fact it can be predicted that it won't work
1692 at all). If in doubt say Y.
1694 config ARCH_HAS_HOLES_MEMORYMODEL
1697 config ARCH_SPARSEMEM_ENABLE
1700 config ARCH_SPARSEMEM_DEFAULT
1701 def_bool ARCH_SPARSEMEM_ENABLE
1703 config ARCH_SELECT_MEMORY_MODEL
1704 def_bool ARCH_SPARSEMEM_ENABLE
1706 config HAVE_ARCH_PFN_VALID
1707 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1710 bool "High Memory Support"
1713 The address space of ARM processors is only 4 Gigabytes large
1714 and it has to accommodate user address space, kernel address
1715 space as well as some memory mapped IO. That means that, if you
1716 have a large amount of physical memory and/or IO, not all of the
1717 memory can be "permanently mapped" by the kernel. The physical
1718 memory that is not permanently mapped is called "high memory".
1720 Depending on the selected kernel/user memory split, minimum
1721 vmalloc space and actual amount of RAM, you may not need this
1722 option which should result in a slightly faster kernel.
1727 bool "Allocate 2nd-level pagetables from highmem"
1730 config HW_PERF_EVENTS
1731 bool "Enable hardware performance counter support for perf events"
1732 depends on PERF_EVENTS
1735 Enable hardware performance counter support for perf events. If
1736 disabled, perf events will use software events only.
1740 config FORCE_MAX_ZONEORDER
1741 int "Maximum zone order" if ARCH_SHMOBILE
1742 range 11 64 if ARCH_SHMOBILE
1743 default "12" if SOC_AM33XX
1744 default "9" if SA1111
1747 The kernel memory allocator divides physically contiguous memory
1748 blocks into "zones", where each zone is a power of two number of
1749 pages. This option selects the largest power of two that the kernel
1750 keeps in the memory allocator. If you need to allocate very large
1751 blocks of physically contiguous memory, then you may need to
1752 increase this value.
1754 This config option is actually maximum order plus one. For example,
1755 a value of 11 means that the largest free memory block is 2^10 pages.
1757 config ALIGNMENT_TRAP
1759 depends on CPU_CP15_MMU
1760 default y if !ARCH_EBSA110
1761 select HAVE_PROC_CPU if PROC_FS
1763 ARM processors cannot fetch/store information which is not
1764 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1765 address divisible by 4. On 32-bit ARM processors, these non-aligned
1766 fetch/store instructions will be emulated in software if you say
1767 here, which has a severe performance impact. This is necessary for
1768 correct operation of some network protocols. With an IP-only
1769 configuration it is safe to say N, otherwise say Y.
1771 config UACCESS_WITH_MEMCPY
1772 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1774 default y if CPU_FEROCEON
1776 Implement faster copy_to_user and clear_user methods for CPU
1777 cores where a 8-word STM instruction give significantly higher
1778 memory write throughput than a sequence of individual 32bit stores.
1780 A possible side effect is a slight increase in scheduling latency
1781 between threads sharing the same address space if they invoke
1782 such copy operations with large buffers.
1784 However, if the CPU data cache is using a write-allocate mode,
1785 this option is unlikely to provide any performance gain.
1789 prompt "Enable seccomp to safely compute untrusted bytecode"
1791 This kernel feature is useful for number crunching applications
1792 that may need to compute untrusted bytecode during their
1793 execution. By using pipes or other transports made available to
1794 the process as file descriptors supporting the read/write
1795 syscalls, it's possible to isolate those applications in
1796 their own address space using seccomp. Once seccomp is
1797 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1798 and the task is only allowed to execute a few safe syscalls
1799 defined by each seccomp mode.
1801 config CC_STACKPROTECTOR
1802 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1804 This option turns on the -fstack-protector GCC feature. This
1805 feature puts, at the beginning of functions, a canary value on
1806 the stack just before the return address, and validates
1807 the value just before actually returning. Stack based buffer
1808 overflows (that need to overwrite this return address) now also
1809 overwrite the canary, which gets detected and the attack is then
1810 neutralized via a kernel panic.
1811 This feature requires gcc version 4.2 or above.
1818 bool "Xen guest support on ARM (EXPERIMENTAL)"
1819 depends on ARM && AEABI && OF
1820 depends on CPU_V7 && !CPU_V6
1821 depends on !GENERIC_ATOMIC64
1823 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1830 bool "Flattened Device Tree support"
1833 select OF_EARLY_FLATTREE
1835 Include support for flattened device tree machine descriptions.
1838 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1841 This is the traditional way of passing data to the kernel at boot
1842 time. If you are solely relying on the flattened device tree (or
1843 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1844 to remove ATAGS support from your kernel binary. If unsure,
1847 config DEPRECATED_PARAM_STRUCT
1848 bool "Provide old way to pass kernel parameters"
1851 This was deprecated in 2001 and announced to live on for 5 years.
1852 Some old boot loaders still use this way.
1854 # Compressed boot loader in ROM. Yes, we really want to ask about
1855 # TEXT and BSS so we preserve their values in the config files.
1856 config ZBOOT_ROM_TEXT
1857 hex "Compressed ROM boot loader base address"
1860 The physical address at which the ROM-able zImage is to be
1861 placed in the target. Platforms which normally make use of
1862 ROM-able zImage formats normally set this to a suitable
1863 value in their defconfig file.
1865 If ZBOOT_ROM is not enabled, this has no effect.
1867 config ZBOOT_ROM_BSS
1868 hex "Compressed ROM boot loader BSS address"
1871 The base address of an area of read/write memory in the target
1872 for the ROM-able zImage which must be available while the
1873 decompressor is running. It must be large enough to hold the
1874 entire decompressed kernel plus an additional 128 KiB.
1875 Platforms which normally make use of ROM-able zImage formats
1876 normally set this to a suitable value in their defconfig file.
1878 If ZBOOT_ROM is not enabled, this has no effect.
1881 bool "Compressed boot loader in ROM/flash"
1882 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1884 Say Y here if you intend to execute your compressed kernel image
1885 (zImage) directly from ROM or flash. If unsure, say N.
1888 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1889 depends on ZBOOT_ROM && ARCH_SH7372
1890 default ZBOOT_ROM_NONE
1892 Include experimental SD/MMC loading code in the ROM-able zImage.
1893 With this enabled it is possible to write the ROM-able zImage
1894 kernel image to an MMC or SD card and boot the kernel straight
1895 from the reset vector. At reset the processor Mask ROM will load
1896 the first part of the ROM-able zImage which in turn loads the
1897 rest the kernel image to RAM.
1899 config ZBOOT_ROM_NONE
1900 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1902 Do not load image from SD or MMC
1904 config ZBOOT_ROM_MMCIF
1905 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1907 Load image from MMCIF hardware block.
1909 config ZBOOT_ROM_SH_MOBILE_SDHI
1910 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1912 Load image from SDHI hardware block
1916 config ARM_APPENDED_DTB
1917 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1918 depends on OF && !ZBOOT_ROM
1920 With this option, the boot code will look for a device tree binary
1921 (DTB) appended to zImage
1922 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1924 This is meant as a backward compatibility convenience for those
1925 systems with a bootloader that can't be upgraded to accommodate
1926 the documented boot protocol using a device tree.
1928 Beware that there is very little in terms of protection against
1929 this option being confused by leftover garbage in memory that might
1930 look like a DTB header after a reboot if no actual DTB is appended
1931 to zImage. Do not leave this option active in a production kernel
1932 if you don't intend to always append a DTB. Proper passing of the
1933 location into r2 of a bootloader provided DTB is always preferable
1936 config ARM_ATAG_DTB_COMPAT
1937 bool "Supplement the appended DTB with traditional ATAG information"
1938 depends on ARM_APPENDED_DTB
1940 Some old bootloaders can't be updated to a DTB capable one, yet
1941 they provide ATAGs with memory configuration, the ramdisk address,
1942 the kernel cmdline string, etc. Such information is dynamically
1943 provided by the bootloader and can't always be stored in a static
1944 DTB. To allow a device tree enabled kernel to be used with such
1945 bootloaders, this option allows zImage to extract the information
1946 from the ATAG list and store it at run time into the appended DTB.
1949 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1950 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1952 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1953 bool "Use bootloader kernel arguments if available"
1955 Uses the command-line options passed by the boot loader instead of
1956 the device tree bootargs property. If the boot loader doesn't provide
1957 any, the device tree bootargs property will be used.
1959 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1960 bool "Extend with bootloader kernel arguments"
1962 The command-line arguments provided by the boot loader will be
1963 appended to the the device tree bootargs property.
1968 string "Default kernel command string"
1971 On some architectures (EBSA110 and CATS), there is currently no way
1972 for the boot loader to pass arguments to the kernel. For these
1973 architectures, you should supply some command-line options at build
1974 time by entering them here. As a minimum, you should specify the
1975 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1978 prompt "Kernel command line type" if CMDLINE != ""
1979 default CMDLINE_FROM_BOOTLOADER
1982 config CMDLINE_FROM_BOOTLOADER
1983 bool "Use bootloader kernel arguments if available"
1985 Uses the command-line options passed by the boot loader. If
1986 the boot loader doesn't provide any, the default kernel command
1987 string provided in CMDLINE will be used.
1989 config CMDLINE_EXTEND
1990 bool "Extend bootloader kernel arguments"
1992 The command-line arguments provided by the boot loader will be
1993 appended to the default kernel command string.
1995 config CMDLINE_FORCE
1996 bool "Always use the default kernel command string"
1998 Always use the default kernel command string, even if the boot
1999 loader passes other arguments to the kernel.
2000 This is useful if you cannot or don't want to change the
2001 command-line options your boot loader passes to the kernel.
2005 bool "Kernel Execute-In-Place from ROM"
2006 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2008 Execute-In-Place allows the kernel to run from non-volatile storage
2009 directly addressable by the CPU, such as NOR flash. This saves RAM
2010 space since the text section of the kernel is not loaded from flash
2011 to RAM. Read-write sections, such as the data section and stack,
2012 are still copied to RAM. The XIP kernel is not compressed since
2013 it has to run directly from flash, so it will take more space to
2014 store it. The flash address used to link the kernel object files,
2015 and for storing it, is configuration dependent. Therefore, if you
2016 say Y here, you must know the proper physical address where to
2017 store the kernel image depending on your own flash memory usage.
2019 Also note that the make target becomes "make xipImage" rather than
2020 "make zImage" or "make Image". The final kernel binary to put in
2021 ROM memory will be arch/arm/boot/xipImage.
2025 config XIP_PHYS_ADDR
2026 hex "XIP Kernel Physical Location"
2027 depends on XIP_KERNEL
2028 default "0x00080000"
2030 This is the physical address in your flash memory the kernel will
2031 be linked for and stored to. This address is dependent on your
2035 bool "Kexec system call (EXPERIMENTAL)"
2036 depends on (!SMP || HOTPLUG_CPU)
2038 kexec is a system call that implements the ability to shutdown your
2039 current kernel, and to start another kernel. It is like a reboot
2040 but it is independent of the system firmware. And like a reboot
2041 you can start any kernel with it, not just Linux.
2043 It is an ongoing process to be certain the hardware in a machine
2044 is properly shutdown, so do not be surprised if this code does not
2045 initially work for you. It may help to enable device hotplugging
2049 bool "Export atags in procfs"
2050 depends on ATAGS && KEXEC
2053 Should the atags used to boot the kernel be exported in an "atags"
2054 file in procfs. Useful with kexec.
2057 bool "Build kdump crash kernel (EXPERIMENTAL)"
2059 Generate crash dump after being started by kexec. This should
2060 be normally only set in special crash dump kernels which are
2061 loaded in the main kernel with kexec-tools into a specially
2062 reserved region and then later executed after a crash by
2063 kdump/kexec. The crash dump kernel must be compiled to a
2064 memory address not used by the main kernel
2066 For more details see Documentation/kdump/kdump.txt
2068 config AUTO_ZRELADDR
2069 bool "Auto calculation of the decompressed kernel image address"
2070 depends on !ZBOOT_ROM && !ARCH_U300
2072 ZRELADDR is the physical address where the decompressed kernel
2073 image will be placed. If AUTO_ZRELADDR is selected, the address
2074 will be determined at run-time by masking the current IP with
2075 0xf8000000. This assumes the zImage being placed in the first 128MB
2076 from start of memory.
2080 menu "CPU Power Management"
2084 source "drivers/cpufreq/Kconfig"
2087 tristate "CPUfreq driver for i.MX CPUs"
2088 depends on ARCH_MXC && CPU_FREQ
2089 select CPU_FREQ_TABLE
2091 This enables the CPUfreq driver for i.MX CPUs.
2093 config CPU_FREQ_SA1100
2096 config CPU_FREQ_SA1110
2099 config CPU_FREQ_INTEGRATOR
2100 tristate "CPUfreq driver for ARM Integrator CPUs"
2101 depends on ARCH_INTEGRATOR && CPU_FREQ
2104 This enables the CPUfreq driver for ARM Integrator CPUs.
2106 For details, take a look at <file:Documentation/cpu-freq>.
2112 depends on CPU_FREQ && ARCH_PXA && PXA25x
2114 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2115 select CPU_FREQ_TABLE
2120 Internal configuration node for common cpufreq on Samsung SoC
2122 config CPU_FREQ_S3C24XX
2123 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2124 depends on ARCH_S3C24XX && CPU_FREQ
2127 This enables the CPUfreq driver for the Samsung S3C24XX family
2130 For details, take a look at <file:Documentation/cpu-freq>.
2134 config CPU_FREQ_S3C24XX_PLL
2135 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2136 depends on CPU_FREQ_S3C24XX
2138 Compile in support for changing the PLL frequency from the
2139 S3C24XX series CPUfreq driver. The PLL takes time to settle
2140 after a frequency change, so by default it is not enabled.
2142 This also means that the PLL tables for the selected CPU(s) will
2143 be built which may increase the size of the kernel image.
2145 config CPU_FREQ_S3C24XX_DEBUG
2146 bool "Debug CPUfreq Samsung driver core"
2147 depends on CPU_FREQ_S3C24XX
2149 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2151 config CPU_FREQ_S3C24XX_IODEBUG
2152 bool "Debug CPUfreq Samsung driver IO timing"
2153 depends on CPU_FREQ_S3C24XX
2155 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2157 config CPU_FREQ_S3C24XX_DEBUGFS
2158 bool "Export debugfs for CPUFreq"
2159 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2161 Export status information via debugfs.
2165 source "drivers/cpuidle/Kconfig"
2169 menu "Floating point emulation"
2171 comment "At least one emulation must be selected"
2174 bool "NWFPE math emulation"
2175 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2177 Say Y to include the NWFPE floating point emulator in the kernel.
2178 This is necessary to run most binaries. Linux does not currently
2179 support floating point hardware so you need to say Y here even if
2180 your machine has an FPA or floating point co-processor podule.
2182 You may say N here if you are going to load the Acorn FPEmulator
2183 early in the bootup.
2186 bool "Support extended precision"
2187 depends on FPE_NWFPE
2189 Say Y to include 80-bit support in the kernel floating-point
2190 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2191 Note that gcc does not generate 80-bit operations by default,
2192 so in most cases this option only enlarges the size of the
2193 floating point emulator without any good reason.
2195 You almost surely want to say N here.
2198 bool "FastFPE math emulation (EXPERIMENTAL)"
2199 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2201 Say Y here to include the FAST floating point emulator in the kernel.
2202 This is an experimental much faster emulator which now also has full
2203 precision for the mantissa. It does not support any exceptions.
2204 It is very simple, and approximately 3-6 times faster than NWFPE.
2206 It should be sufficient for most programs. It may be not suitable
2207 for scientific calculations, but you have to check this for yourself.
2208 If you do not feel you need a faster FP emulation you should better
2212 bool "VFP-format floating point maths"
2213 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2215 Say Y to include VFP support code in the kernel. This is needed
2216 if your hardware includes a VFP unit.
2218 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2219 release notes and additional status information.
2221 Say N if your target does not have VFP hardware.
2229 bool "Advanced SIMD (NEON) Extension support"
2230 depends on VFPv3 && CPU_V7
2232 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2237 menu "Userspace binary formats"
2239 source "fs/Kconfig.binfmt"
2242 tristate "RISC OS personality"
2245 Say Y here to include the kernel code necessary if you want to run
2246 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2247 experimental; if this sounds frightening, say N and sleep in peace.
2248 You can also say M here to compile this support as a module (which
2249 will be called arthur).
2253 menu "Power management options"
2255 source "kernel/power/Kconfig"
2257 config ARCH_SUSPEND_POSSIBLE
2258 depends on !ARCH_S5PC100
2259 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2260 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2263 config ARM_CPU_SUSPEND
2268 source "net/Kconfig"
2270 source "drivers/Kconfig"
2274 source "arch/arm/Kconfig.debug"
2276 source "security/Kconfig"
2278 source "crypto/Kconfig"
2280 source "lib/Kconfig"
2282 source "arch/arm/kvm/Kconfig"