5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if (!XIP_KERNEL && !THUMB2_KERNEL)
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
47 config SYS_SUPPORTS_APM_EMULATION
50 config HAVE_SCHED_CLOCK
56 config ARCH_USES_GETTIMEOFFSET
60 config GENERIC_CLOCKEVENTS
63 config GENERIC_CLOCKEVENTS_BROADCAST
65 depends on GENERIC_CLOCKEVENTS
74 select GENERIC_ALLOCATOR
85 The Extended Industry Standard Architecture (EISA) bus was
86 developed as an open alternative to the IBM MicroChannel bus.
88 The EISA bus provided some of the features of the IBM MicroChannel
89 bus while maintaining backward compatibility with cards made for
90 the older ISA bus. The EISA bus saw limited use between 1988 and
91 1995 when it was made obsolete by the PCI bus.
93 Say Y here if you are building a kernel for an EISA-based machine.
103 MicroChannel Architecture is found in some IBM PS/2 machines and
104 laptops. It is a bus system similar to PCI or ISA. See
105 <file:Documentation/mca.txt> (and especially the web page given
106 there) before attempting to build an MCA bus kernel.
108 config STACKTRACE_SUPPORT
112 config HAVE_LATENCYTOP_SUPPORT
117 config LOCKDEP_SUPPORT
121 config TRACE_IRQFLAGS_SUPPORT
125 config HARDIRQS_SW_RESEND
129 config GENERIC_IRQ_PROBE
133 config GENERIC_LOCKBREAK
136 depends on SMP && PREEMPT
138 config RWSEM_GENERIC_SPINLOCK
142 config RWSEM_XCHGADD_ALGORITHM
145 config ARCH_HAS_ILOG2_U32
148 config ARCH_HAS_ILOG2_U64
151 config ARCH_HAS_CPUFREQ
154 Internal node to signify that the ARCH has CPUFREQ support
155 and that the relevant menu configurations are displayed for
158 config ARCH_HAS_CPU_IDLE_WAIT
161 config GENERIC_HWEIGHT
165 config GENERIC_CALIBRATE_DELAY
169 config ARCH_MAY_HAVE_PC_FDC
175 config NEED_DMA_MAP_STATE
178 config GENERIC_ISA_DMA
189 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
190 default DRAM_BASE if REMAP_VECTORS_TO_RAM
193 The base address of exception vectors.
195 config ARM_PATCH_PHYS_VIRT
196 bool "Patch physical to virtual translations at runtime (EXPERIMENTAL)"
197 depends on EXPERIMENTAL
198 depends on !XIP_KERNEL && MMU
199 depends on !ARCH_REALVIEW || !SPARSEMEM
201 Patch phys-to-virt and virt-to-phys translation functions at
202 boot and module load time according to the position of the
203 kernel in system memory.
205 This can only be used with non-XIP MMU kernels where the base
206 of physical memory is at a 16MB boundary, or theoretically 64K
207 for the MSM machine class.
209 config ARM_PATCH_PHYS_VIRT_16BIT
211 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
213 This option extends the physical to virtual translation patching
214 to allow physical memory down to a theoretical minimum of 64K
217 source "init/Kconfig"
219 source "kernel/Kconfig.freezer"
224 bool "MMU-based Paged Memory Management Support"
227 Select if you want MMU-based virtualised addressing space
228 support by paged memory management. If unsure, say 'Y'.
231 # The "ARM system type" choice list is ordered alphabetically by option
232 # text. Please add new entries in the option alphabetic order.
235 prompt "ARM system type"
236 default ARCH_VERSATILE
238 config ARCH_INTEGRATOR
239 bool "ARM Ltd. Integrator family"
241 select ARCH_HAS_CPUFREQ
244 select GENERIC_CLOCKEVENTS
245 select PLAT_VERSATILE
246 select PLAT_VERSATILE_FPGA_IRQ
248 Support for ARM's Integrator platform.
251 bool "ARM Ltd. RealView family"
255 select GENERIC_CLOCKEVENTS
256 select ARCH_WANT_OPTIONAL_GPIOLIB
257 select PLAT_VERSATILE
258 select PLAT_VERSATILE_CLCD
259 select ARM_TIMER_SP804
260 select GPIO_PL061 if GPIOLIB
262 This enables support for ARM Ltd RealView boards.
264 config ARCH_VERSATILE
265 bool "ARM Ltd. Versatile family"
270 select GENERIC_CLOCKEVENTS
271 select ARCH_WANT_OPTIONAL_GPIOLIB
272 select PLAT_VERSATILE
273 select PLAT_VERSATILE_CLCD
274 select PLAT_VERSATILE_FPGA_IRQ
275 select ARM_TIMER_SP804
277 This enables support for ARM Ltd Versatile board.
280 bool "ARM Ltd. Versatile Express family"
281 select ARCH_WANT_OPTIONAL_GPIOLIB
283 select ARM_TIMER_SP804
285 select GENERIC_CLOCKEVENTS
287 select HAVE_PATA_PLATFORM
289 select PLAT_VERSATILE
290 select PLAT_VERSATILE_CLCD
292 This enables support for the ARM Ltd Versatile Express boards.
296 select ARCH_REQUIRE_GPIOLIB
299 select ARM_PATCH_PHYS_VIRT if MMU
301 This enables support for systems based on the Atmel AT91RM9200,
302 AT91SAM9 and AT91CAP9 processors.
305 bool "Broadcom BCMRING"
309 select ARM_TIMER_SP804
311 select GENERIC_CLOCKEVENTS
312 select ARCH_WANT_OPTIONAL_GPIOLIB
314 Support for Broadcom's BCMRing platform.
317 bool "Cirrus Logic CLPS711x/EP721x-based"
319 select ARCH_USES_GETTIMEOFFSET
321 Support for Cirrus Logic 711x/721x based boards.
324 bool "Cavium Networks CNS3XXX family"
326 select GENERIC_CLOCKEVENTS
328 select MIGHT_HAVE_PCI
329 select PCI_DOMAINS if PCI
331 Support for Cavium Networks CNS3XXX platform.
334 bool "Cortina Systems Gemini"
336 select ARCH_REQUIRE_GPIOLIB
337 select ARCH_USES_GETTIMEOFFSET
339 Support for the Cortina Systems Gemini family SoCs
346 select ARCH_USES_GETTIMEOFFSET
348 This is an evaluation board for the StrongARM processor available
349 from Digital. It has limited hardware on-board, including an
350 Ethernet interface, two PCMCIA sockets, two serial ports and a
359 select ARCH_REQUIRE_GPIOLIB
360 select ARCH_HAS_HOLES_MEMORYMODEL
361 select ARCH_USES_GETTIMEOFFSET
363 This enables support for the Cirrus EP93xx series of CPUs.
365 config ARCH_FOOTBRIDGE
369 select GENERIC_CLOCKEVENTS
371 Support for systems based on the DC21285 companion chip
372 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
375 bool "Freescale MXC/iMX-based"
376 select GENERIC_CLOCKEVENTS
377 select ARCH_REQUIRE_GPIOLIB
380 select HAVE_SCHED_CLOCK
382 Support for Freescale MXC/iMX-based family of processors
385 bool "Freescale MXS-based"
386 select GENERIC_CLOCKEVENTS
387 select ARCH_REQUIRE_GPIOLIB
391 Support for Freescale MXS-based family of processors
394 bool "Hilscher NetX based"
398 select GENERIC_CLOCKEVENTS
400 This enables support for systems based on the Hilscher NetX Soc
403 bool "Hynix HMS720x-based"
406 select ARCH_USES_GETTIMEOFFSET
408 This enables support for systems based on the Hynix HMS720x
416 select ARCH_SUPPORTS_MSI
419 Support for Intel's IOP13XX (XScale) family of processors.
427 select ARCH_REQUIRE_GPIOLIB
429 Support for Intel's 80219 and IOP32X (XScale) family of
438 select ARCH_REQUIRE_GPIOLIB
440 Support for Intel's IOP33X (XScale) family of processors.
447 select ARCH_USES_GETTIMEOFFSET
449 Support for Intel's IXP23xx (XScale) family of processors.
452 bool "IXP2400/2800-based"
456 select ARCH_USES_GETTIMEOFFSET
458 Support for Intel's IXP2400/2800 (XScale) family of processors.
466 select GENERIC_CLOCKEVENTS
467 select HAVE_SCHED_CLOCK
468 select MIGHT_HAVE_PCI
469 select DMABOUNCE if PCI
471 Support for Intel's IXP4XX (XScale) family of processors.
477 select ARCH_REQUIRE_GPIOLIB
478 select GENERIC_CLOCKEVENTS
481 Support for the Marvell Dove SoC 88AP510
484 bool "Marvell Kirkwood"
487 select ARCH_REQUIRE_GPIOLIB
488 select GENERIC_CLOCKEVENTS
491 Support for the following Marvell Kirkwood series SoCs:
492 88F6180, 88F6192 and 88F6281.
495 bool "Marvell Loki (88RC8480)"
497 select GENERIC_CLOCKEVENTS
500 Support for the Marvell Loki (88RC8480) SoC.
506 select ARCH_REQUIRE_GPIOLIB
509 select USB_ARCH_HAS_OHCI
512 select GENERIC_CLOCKEVENTS
514 Support for the NXP LPC32XX family of processors
517 bool "Marvell MV78xx0"
520 select ARCH_REQUIRE_GPIOLIB
521 select GENERIC_CLOCKEVENTS
524 Support for the following Marvell MV78xx0 series SoCs:
532 select ARCH_REQUIRE_GPIOLIB
533 select GENERIC_CLOCKEVENTS
536 Support for the following Marvell Orion 5x series SoCs:
537 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
538 Orion-2 (5281), Orion-1-90 (6183).
541 bool "Marvell PXA168/910/MMP2"
543 select ARCH_REQUIRE_GPIOLIB
545 select GENERIC_CLOCKEVENTS
546 select HAVE_SCHED_CLOCK
551 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
554 bool "Micrel/Kendin KS8695"
556 select ARCH_REQUIRE_GPIOLIB
557 select ARCH_USES_GETTIMEOFFSET
559 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
560 System-on-Chip devices.
563 bool "Nuvoton W90X900 CPU"
565 select ARCH_REQUIRE_GPIOLIB
568 select GENERIC_CLOCKEVENTS
570 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
571 At present, the w90x900 has been renamed nuc900, regarding
572 the ARM series product line, you can login the following
573 link address to know more.
575 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
576 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
579 bool "Nuvoton NUC93X CPU"
583 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
584 low-power and high performance MPEG-4/JPEG multimedia controller chip.
591 select GENERIC_CLOCKEVENTS
594 select HAVE_SCHED_CLOCK
595 select ARCH_HAS_BARRIERS if CACHE_L2X0
596 select ARCH_HAS_CPUFREQ
598 This enables support for NVIDIA Tegra based systems (Tegra APX,
599 Tegra 6xx and Tegra 2 series).
602 bool "Philips Nexperia PNX4008 Mobile"
605 select ARCH_USES_GETTIMEOFFSET
607 This enables support for Philips PNX4008 mobile platform.
610 bool "PXA2xx/PXA3xx-based"
613 select ARCH_HAS_CPUFREQ
616 select ARCH_REQUIRE_GPIOLIB
617 select GENERIC_CLOCKEVENTS
618 select HAVE_SCHED_CLOCK
623 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
628 select GENERIC_CLOCKEVENTS
629 select ARCH_REQUIRE_GPIOLIB
632 Support for Qualcomm MSM/QSD based systems. This runs on the
633 apps processor of the MSM/QSD and depends on a shared memory
634 interface to the modem processor which runs the baseband
635 stack and controls some vital subsystems
636 (clock and power control, etc).
639 bool "Renesas SH-Mobile / R-Mobile"
642 select GENERIC_CLOCKEVENTS
645 select MULTI_IRQ_HANDLER
647 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
654 select ARCH_MAY_HAVE_PC_FDC
655 select HAVE_PATA_PLATFORM
658 select ARCH_SPARSEMEM_ENABLE
659 select ARCH_USES_GETTIMEOFFSET
661 On the Acorn Risc-PC, Linux can support the internal IDE disk and
662 CD-ROM interface, serial and parallel port, and the floppy drive.
669 select ARCH_SPARSEMEM_ENABLE
671 select ARCH_HAS_CPUFREQ
673 select GENERIC_CLOCKEVENTS
675 select HAVE_SCHED_CLOCK
677 select ARCH_REQUIRE_GPIOLIB
679 Support for StrongARM 11x0 based boards.
682 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
684 select ARCH_HAS_CPUFREQ
686 select ARCH_USES_GETTIMEOFFSET
687 select HAVE_S3C2410_I2C if I2C
689 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
690 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
691 the Samsung SMDK2410 development board (and derivatives).
693 Note, the S3C2416 and the S3C2450 are so close that they even share
694 the same SoC ID code. This means that there is no separate machine
695 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
698 bool "Samsung S3C64XX"
704 select ARCH_USES_GETTIMEOFFSET
705 select ARCH_HAS_CPUFREQ
706 select ARCH_REQUIRE_GPIOLIB
707 select SAMSUNG_CLKSRC
708 select SAMSUNG_IRQ_VIC_TIMER
709 select SAMSUNG_IRQ_UART
710 select S3C_GPIO_TRACK
711 select S3C_GPIO_PULL_UPDOWN
712 select S3C_GPIO_CFG_S3C24XX
713 select S3C_GPIO_CFG_S3C64XX
715 select USB_ARCH_HAS_OHCI
716 select SAMSUNG_GPIOLIB_4BIT
717 select HAVE_S3C2410_I2C if I2C
718 select HAVE_S3C2410_WATCHDOG if WATCHDOG
720 Samsung S3C64XX series based systems
723 bool "Samsung S5P6440 S5P6450"
727 select HAVE_S3C2410_WATCHDOG if WATCHDOG
728 select GENERIC_CLOCKEVENTS
729 select HAVE_SCHED_CLOCK
730 select HAVE_S3C2410_I2C if I2C
731 select HAVE_S3C_RTC if RTC_CLASS
733 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
737 bool "Samsung S5PC100"
741 select ARM_L1_CACHE_SHIFT_6
742 select ARCH_USES_GETTIMEOFFSET
743 select HAVE_S3C2410_I2C if I2C
744 select HAVE_S3C_RTC if RTC_CLASS
745 select HAVE_S3C2410_WATCHDOG if WATCHDOG
747 Samsung S5PC100 series based systems
750 bool "Samsung S5PV210/S5PC110"
752 select ARCH_SPARSEMEM_ENABLE
755 select ARM_L1_CACHE_SHIFT_6
756 select ARCH_HAS_CPUFREQ
757 select GENERIC_CLOCKEVENTS
758 select HAVE_SCHED_CLOCK
759 select HAVE_S3C2410_I2C if I2C
760 select HAVE_S3C_RTC if RTC_CLASS
761 select HAVE_S3C2410_WATCHDOG if WATCHDOG
763 Samsung S5PV210/S5PC110 series based systems
766 bool "Samsung EXYNOS4"
768 select ARCH_SPARSEMEM_ENABLE
771 select ARCH_HAS_CPUFREQ
772 select GENERIC_CLOCKEVENTS
773 select HAVE_S3C_RTC if RTC_CLASS
774 select HAVE_S3C2410_I2C if I2C
775 select HAVE_S3C2410_WATCHDOG if WATCHDOG
777 Samsung EXYNOS4 series based systems
786 select ARCH_USES_GETTIMEOFFSET
788 Support for the StrongARM based Digital DNARD machine, also known
789 as "Shark" (<http://www.shark-linux.de/shark.html>).
792 bool "Telechips TCC ARM926-based systems"
797 select GENERIC_CLOCKEVENTS
799 Support for Telechips TCC ARM926-based systems.
802 bool "ST-Ericsson U300 Series"
806 select HAVE_SCHED_CLOCK
810 select GENERIC_CLOCKEVENTS
814 Support for ST-Ericsson U300 series mobile platforms.
817 bool "ST-Ericsson U8500 Series"
820 select GENERIC_CLOCKEVENTS
822 select ARCH_REQUIRE_GPIOLIB
823 select ARCH_HAS_CPUFREQ
825 Support for ST-Ericsson's Ux500 architecture
828 bool "STMicroelectronics Nomadik"
833 select GENERIC_CLOCKEVENTS
834 select ARCH_REQUIRE_GPIOLIB
836 Support for the Nomadik platform by ST-Ericsson
840 select GENERIC_CLOCKEVENTS
841 select ARCH_REQUIRE_GPIOLIB
845 select GENERIC_ALLOCATOR
846 select GENERIC_IRQ_CHIP
847 select ARCH_HAS_HOLES_MEMORYMODEL
849 Support for TI's DaVinci platform.
854 select ARCH_REQUIRE_GPIOLIB
855 select ARCH_HAS_CPUFREQ
856 select GENERIC_CLOCKEVENTS
857 select HAVE_SCHED_CLOCK
858 select ARCH_HAS_HOLES_MEMORYMODEL
860 Support for TI's OMAP platform (OMAP1/2/3/4).
863 bool "Rockchip RK29xx"
870 select ARM_L1_CACHE_SHIFT_6
872 Support for Rockchip's RK29xx SoCs.
875 bool "Rockchip RK2928"
880 select MIGHT_HAVE_CACHE_L2X0
881 select ARM_ERRATA_754322
882 select ARM_ERRATA_775420
884 Support for Rockchip's RK2928 SoCs.
887 bool "Rockchip RK3026/RK3028A"
893 select HAVE_ARM_TWD if LOCAL_TIMERS
895 select MIGHT_HAVE_CACHE_L2X0
896 select ARM_ERRATA_754322
897 select ARM_ERRATA_764369
899 Support for Rockchip's RK3026/RK3028A SoCs.
902 bool "Rockchip RK30xx/RK3108/RK3168"
908 select MIGHT_HAVE_CACHE_L2X0
909 select ARM_ERRATA_764369
910 select ARM_ERRATA_754322
911 select ARM_ERRATA_775420
913 Support for Rockchip's RK30xx/RK3108/RK3168 SoCs.
916 bool "Rockchip RK3188"
923 select MIGHT_HAVE_CACHE_L2X0
924 select ARM_ERRATA_761320
925 select ARM_ERRATA_764369
926 select ARM_ERRATA_754322
927 select ARM_ERRATA_775420
929 Support for Rockchip's RK3188 SoCs.
934 select ARCH_REQUIRE_GPIOLIB
937 select GENERIC_CLOCKEVENTS
940 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
943 bool "VIA/WonderMedia 85xx"
946 select ARCH_HAS_CPUFREQ
947 select GENERIC_CLOCKEVENTS
948 select ARCH_REQUIRE_GPIOLIB
951 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
955 # This is sorted alphabetically by mach-* pathname. However, plat-*
956 # Kconfigs may be included either alphabetically (according to the
957 # plat- suffix) or along side the corresponding mach-* source.
959 source "arch/arm/mach-at91/Kconfig"
961 source "arch/arm/mach-bcmring/Kconfig"
963 source "arch/arm/mach-clps711x/Kconfig"
965 source "arch/arm/mach-cns3xxx/Kconfig"
967 source "arch/arm/mach-davinci/Kconfig"
969 source "arch/arm/mach-dove/Kconfig"
971 source "arch/arm/mach-ep93xx/Kconfig"
973 source "arch/arm/mach-footbridge/Kconfig"
975 source "arch/arm/mach-gemini/Kconfig"
977 source "arch/arm/mach-h720x/Kconfig"
979 source "arch/arm/mach-integrator/Kconfig"
981 source "arch/arm/mach-iop32x/Kconfig"
983 source "arch/arm/mach-iop33x/Kconfig"
985 source "arch/arm/mach-iop13xx/Kconfig"
987 source "arch/arm/mach-ixp4xx/Kconfig"
989 source "arch/arm/mach-ixp2000/Kconfig"
991 source "arch/arm/mach-ixp23xx/Kconfig"
993 source "arch/arm/mach-kirkwood/Kconfig"
995 source "arch/arm/mach-ks8695/Kconfig"
997 source "arch/arm/mach-loki/Kconfig"
999 source "arch/arm/mach-lpc32xx/Kconfig"
1001 source "arch/arm/mach-msm/Kconfig"
1003 source "arch/arm/mach-mv78xx0/Kconfig"
1005 source "arch/arm/plat-mxc/Kconfig"
1007 source "arch/arm/mach-mxs/Kconfig"
1009 source "arch/arm/mach-netx/Kconfig"
1011 source "arch/arm/mach-nomadik/Kconfig"
1012 source "arch/arm/plat-nomadik/Kconfig"
1014 source "arch/arm/mach-nuc93x/Kconfig"
1016 source "arch/arm/plat-omap/Kconfig"
1018 source "arch/arm/mach-omap1/Kconfig"
1020 source "arch/arm/mach-omap2/Kconfig"
1022 source "arch/arm/mach-orion5x/Kconfig"
1024 source "arch/arm/mach-pxa/Kconfig"
1025 source "arch/arm/plat-pxa/Kconfig"
1027 source "arch/arm/mach-mmp/Kconfig"
1029 source "arch/arm/mach-realview/Kconfig"
1031 source "arch/arm/plat-rk/Kconfig"
1032 source "arch/arm/mach-rk29/Kconfig"
1033 source "arch/arm/mach-rk2928/Kconfig"
1034 source "arch/arm/mach-rk3026/Kconfig"
1035 source "arch/arm/mach-rk30/Kconfig"
1036 source "arch/arm/mach-rk3188/Kconfig"
1038 source "arch/arm/mach-sa1100/Kconfig"
1040 source "arch/arm/plat-samsung/Kconfig"
1041 source "arch/arm/plat-s3c24xx/Kconfig"
1042 source "arch/arm/plat-s5p/Kconfig"
1044 source "arch/arm/plat-spear/Kconfig"
1046 source "arch/arm/plat-tcc/Kconfig"
1049 source "arch/arm/mach-s3c2400/Kconfig"
1050 source "arch/arm/mach-s3c2410/Kconfig"
1051 source "arch/arm/mach-s3c2412/Kconfig"
1052 source "arch/arm/mach-s3c2416/Kconfig"
1053 source "arch/arm/mach-s3c2440/Kconfig"
1054 source "arch/arm/mach-s3c2443/Kconfig"
1058 source "arch/arm/mach-s3c64xx/Kconfig"
1061 source "arch/arm/mach-s5p64x0/Kconfig"
1063 source "arch/arm/mach-s5pc100/Kconfig"
1065 source "arch/arm/mach-s5pv210/Kconfig"
1067 source "arch/arm/mach-exynos4/Kconfig"
1069 source "arch/arm/mach-shmobile/Kconfig"
1071 source "arch/arm/mach-tegra/Kconfig"
1073 source "arch/arm/mach-u300/Kconfig"
1075 source "arch/arm/mach-ux500/Kconfig"
1077 source "arch/arm/mach-versatile/Kconfig"
1079 source "arch/arm/mach-vexpress/Kconfig"
1080 source "arch/arm/plat-versatile/Kconfig"
1082 source "arch/arm/mach-vt8500/Kconfig"
1084 source "arch/arm/mach-w90x900/Kconfig"
1086 # Definitions to make life easier
1092 select GENERIC_CLOCKEVENTS
1093 select HAVE_SCHED_CLOCK
1098 select GENERIC_IRQ_CHIP
1099 select HAVE_SCHED_CLOCK
1106 select CLKDEV_LOOKUP
1107 select HAVE_SCHED_CLOCK
1108 select ARCH_HAS_CPUFREQ
1109 select GENERIC_CLOCKEVENTS
1110 select ARCH_REQUIRE_GPIOLIB
1115 config PLAT_VERSATILE
1118 config ARM_TIMER_SP804
1122 source arch/arm/mm/Kconfig
1125 bool "Enable iWMMXt support"
1126 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1127 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1129 Enable support for iWMMXt context switching at run time if
1130 running on a CPU that supports it.
1132 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1135 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1139 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1140 (!ARCH_OMAP3 || OMAP3_EMU)
1144 config MULTI_IRQ_HANDLER
1147 Allow each machine to specify it's own IRQ handler at run time.
1150 source "arch/arm/Kconfig-nommu"
1153 config ARM_ERRATA_411920
1154 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1155 depends on CPU_V6 || CPU_V6K
1157 Invalidation of the Instruction Cache operation can
1158 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1159 It does not affect the MPCore. This option enables the ARM Ltd.
1160 recommended workaround.
1162 config ARM_ERRATA_430973
1163 bool "ARM errata: Stale prediction on replaced interworking branch"
1166 This option enables the workaround for the 430973 Cortex-A8
1167 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1168 interworking branch is replaced with another code sequence at the
1169 same virtual address, whether due to self-modifying code or virtual
1170 to physical address re-mapping, Cortex-A8 does not recover from the
1171 stale interworking branch prediction. This results in Cortex-A8
1172 executing the new code sequence in the incorrect ARM or Thumb state.
1173 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1174 and also flushes the branch target cache at every context switch.
1175 Note that setting specific bits in the ACTLR register may not be
1176 available in non-secure mode.
1178 config ARM_ERRATA_458693
1179 bool "ARM errata: Processor deadlock when a false hazard is created"
1182 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1183 erratum. For very specific sequences of memory operations, it is
1184 possible for a hazard condition intended for a cache line to instead
1185 be incorrectly associated with a different cache line. This false
1186 hazard might then cause a processor deadlock. The workaround enables
1187 the L1 caching of the NEON accesses and disables the PLD instruction
1188 in the ACTLR register. Note that setting specific bits in the ACTLR
1189 register may not be available in non-secure mode.
1191 config ARM_ERRATA_460075
1192 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1195 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1196 erratum. Any asynchronous access to the L2 cache may encounter a
1197 situation in which recent store transactions to the L2 cache are lost
1198 and overwritten with stale memory contents from external memory. The
1199 workaround disables the write-allocate mode for the L2 cache via the
1200 ACTLR register. Note that setting specific bits in the ACTLR register
1201 may not be available in non-secure mode.
1203 config ARM_ERRATA_742230
1204 bool "ARM errata: DMB operation may be faulty"
1205 depends on CPU_V7 && SMP
1207 This option enables the workaround for the 742230 Cortex-A9
1208 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1209 between two write operations may not ensure the correct visibility
1210 ordering of the two writes. This workaround sets a specific bit in
1211 the diagnostic register of the Cortex-A9 which causes the DMB
1212 instruction to behave as a DSB, ensuring the correct behaviour of
1215 config ARM_ERRATA_742231
1216 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1217 depends on CPU_V7 && SMP
1219 This option enables the workaround for the 742231 Cortex-A9
1220 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1221 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1222 accessing some data located in the same cache line, may get corrupted
1223 data due to bad handling of the address hazard when the line gets
1224 replaced from one of the CPUs at the same time as another CPU is
1225 accessing it. This workaround sets specific bits in the diagnostic
1226 register of the Cortex-A9 which reduces the linefill issuing
1227 capabilities of the processor.
1229 config PL310_ERRATA_588369
1230 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1231 depends on CACHE_L2X0
1233 The PL310 L2 cache controller implements three types of Clean &
1234 Invalidate maintenance operations: by Physical Address
1235 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1236 They are architecturally defined to behave as the execution of a
1237 clean operation followed immediately by an invalidate operation,
1238 both performing to the same memory location. This functionality
1239 is not correctly implemented in PL310 as clean lines are not
1240 invalidated as a result of these operations.
1242 config ARM_ERRATA_720789
1243 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1244 depends on CPU_V7 && SMP
1246 This option enables the workaround for the 720789 Cortex-A9 (prior to
1247 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1248 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1249 As a consequence of this erratum, some TLB entries which should be
1250 invalidated are not, resulting in an incoherency in the system page
1251 tables. The workaround changes the TLB flushing routines to invalidate
1252 entries regardless of the ASID.
1254 config PL310_ERRATA_727915
1255 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1256 depends on CACHE_L2X0
1258 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1259 operation (offset 0x7FC). This operation runs in background so that
1260 PL310 can handle normal accesses while it is in progress. Under very
1261 rare circumstances, due to this erratum, write data can be lost when
1262 PL310 treats a cacheable write transaction during a Clean &
1263 Invalidate by Way operation.
1265 config ARM_ERRATA_743622
1266 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1269 This option enables the workaround for the 743622 Cortex-A9
1270 (r2p*) erratum. Under very rare conditions, a faulty
1271 optimisation in the Cortex-A9 Store Buffer may lead to data
1272 corruption. This workaround sets a specific bit in the diagnostic
1273 register of the Cortex-A9 which disables the Store Buffer
1274 optimisation, preventing the defect from occurring. This has no
1275 visible impact on the overall performance or power consumption of the
1278 config ARM_ERRATA_751472
1279 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1280 depends on CPU_V7 && SMP
1282 This option enables the workaround for the 751472 Cortex-A9 (prior
1283 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1284 completion of a following broadcasted operation if the second
1285 operation is received by a CPU before the ICIALLUIS has completed,
1286 potentially leading to corrupted entries in the cache or TLB.
1288 config ARM_ERRATA_753970
1289 bool "ARM errata: cache sync operation may be faulty"
1290 depends on CACHE_PL310
1292 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1294 Under some condition the effect of cache sync operation on
1295 the store buffer still remains when the operation completes.
1296 This means that the store buffer is always asked to drain and
1297 this prevents it from merging any further writes. The workaround
1298 is to replace the normal offset of cache sync operation (0x730)
1299 by another offset targeting an unmapped PL310 register 0x740.
1300 This has the same effect as the cache sync operation: store buffer
1301 drain and waiting for all buffers empty.
1303 config ARM_ERRATA_754322
1304 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1307 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1308 r3p*) erratum. A speculative memory access may cause a page table walk
1309 which starts prior to an ASID switch but completes afterwards. This
1310 can populate the micro-TLB with a stale entry which may be hit with
1311 the new ASID. This workaround places two dsb instructions in the mm
1312 switching code so that no page table walks can cross the ASID switch.
1314 config ARM_ERRATA_754327
1315 bool "ARM errata: no automatic Store Buffer drain"
1316 depends on CPU_V7 && SMP
1318 This option enables the workaround for the 754327 Cortex-A9 (prior to
1319 r2p0) erratum. The Store Buffer does not have any automatic draining
1320 mechanism and therefore a livelock may occur if an external agent
1321 continuously polls a memory location waiting to observe an update.
1322 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1323 written polling loops from denying visibility of updates to memory.
1325 config ARM_ERRATA_761320
1326 bool "ARM errata: no direct eviction"
1327 depends on CPU_V7 && SMP
1329 This option enables the workaround for the 761320 Cortex-A9 erratum.
1331 config ARM_ERRATA_764369
1332 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1333 depends on CPU_V7 && SMP
1335 This option enables the workaround for erratum 764369
1336 affecting Cortex-A9 MPCore with two or more processors (all
1337 current revisions). Under certain timing circumstances, a data
1338 cache line maintenance operation by MVA targeting an Inner
1339 Shareable memory region may fail to proceed up to either the
1340 Point of Coherency or to the Point of Unification of the
1341 system. This workaround adds a DSB instruction before the
1342 relevant cache maintenance functions and sets a specific bit
1343 in the diagnostic control register of the SCU.
1345 config PL310_ERRATA_769419
1346 bool "PL310 errata: no automatic Store Buffer drain"
1347 depends on CACHE_L2X0
1349 On revisions of the PL310 prior to r3p2, the Store Buffer does
1350 not automatically drain. This can cause normal, non-cacheable
1351 writes to be retained when the memory system is idle, leading
1352 to suboptimal I/O performance for drivers using coherent DMA.
1353 This option adds a write barrier to the cpu_idle loop so that,
1354 on systems with an outer cache, the store buffer is drained
1357 config ARM_ERRATA_775420
1358 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1361 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1362 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1363 operation aborts with MMU exception, it might cause the processor
1364 to deadlock. This workaround puts DSB before executing ISB if
1365 an abort may occur on cache maintenance.
1369 source "arch/arm/common/Kconfig"
1379 Find out whether you have ISA slots on your motherboard. ISA is the
1380 name of a bus system, i.e. the way the CPU talks to the other stuff
1381 inside your box. Other bus systems are PCI, EISA, MicroChannel
1382 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1383 newer boards don't support it. If you have ISA, say Y, otherwise N.
1385 # Select ISA DMA controller support
1390 # Select ISA DMA interface
1395 bool "PCI support" if MIGHT_HAVE_PCI
1397 Find out whether you have a PCI motherboard. PCI is the name of a
1398 bus system, i.e. the way the CPU talks to the other stuff inside
1399 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1400 VESA. If you have PCI, say Y, otherwise N.
1406 config PCI_NANOENGINE
1407 bool "BSE nanoEngine PCI support"
1408 depends on SA1100_NANOENGINE
1410 Enable PCI on the BSE nanoEngine board.
1415 # Select the host bridge type
1416 config PCI_HOST_VIA82C505
1418 depends on PCI && ARCH_SHARK
1421 config PCI_HOST_ITE8152
1423 depends on PCI && MACH_ARMCORE
1427 source "drivers/pci/Kconfig"
1429 source "drivers/pcmcia/Kconfig"
1433 menu "Kernel Features"
1435 source "kernel/time/Kconfig"
1440 This option should be selected by machines which have an SMP-
1443 The only effect of this option is to make the SMP-related
1444 options available to the user for configuration.
1447 bool "Symmetric Multi-Processing"
1448 depends on CPU_V6K || CPU_V7
1449 depends on GENERIC_CLOCKEVENTS
1452 select USE_GENERIC_SMP_HELPERS
1453 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1455 This enables support for systems with more than one CPU. If you have
1456 a system with only one CPU, like most personal computers, say N. If
1457 you have a system with more than one CPU, say Y.
1459 If you say N here, the kernel will run on single and multiprocessor
1460 machines, but will use only one CPU of a multiprocessor machine. If
1461 you say Y here, the kernel will run on many, but not all, single
1462 processor machines. On a single processor machine, the kernel will
1463 run faster if you say N here.
1465 See also <file:Documentation/i386/IO-APIC.txt>,
1466 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1467 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1469 If you don't know what to do here, say N.
1472 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1473 depends on EXPERIMENTAL
1474 depends on SMP && !XIP_KERNEL
1477 SMP kernels contain instructions which fail on non-SMP processors.
1478 Enabling this option allows the kernel to modify itself to make
1479 these instructions safe. Disabling it allows about 1K of space
1482 If you don't know what to do here, say Y.
1488 This option enables support for the ARM system coherency unit
1495 This options enables support for the ARM timer and watchdog unit
1498 prompt "Memory split"
1501 Select the desired split between kernel and user memory.
1503 If you are not absolutely sure what you are doing, leave this
1507 bool "3G/1G user/kernel split"
1509 bool "2G/2G user/kernel split"
1511 bool "1G/3G user/kernel split"
1516 default 0x40000000 if VMSPLIT_1G
1517 default 0x80000000 if VMSPLIT_2G
1521 int "Maximum number of CPUs (2-32)"
1527 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1528 depends on SMP && HOTPLUG && EXPERIMENTAL
1530 Say Y here to experiment with turning CPUs off and on. CPUs
1531 can be controlled through /sys/devices/system/cpu.
1534 bool "Use local timer interrupts"
1537 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT && !RK_TIMER)
1539 Enable support for local timers on SMP platforms, rather then the
1540 legacy IPI broadcast method. Local timers allows the system
1541 accounting to be spread across the timer interval, preventing a
1542 "thundering herd" at every timer tick.
1544 source kernel/Kconfig.preempt
1548 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1549 ARCH_S5PV210 || ARCH_EXYNOS4
1550 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1551 default AT91_TIMER_HZ if ARCH_AT91
1552 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1555 config THUMB2_KERNEL
1556 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1557 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1559 select ARM_ASM_UNIFIED
1561 By enabling this option, the kernel will be compiled in
1562 Thumb-2 mode. A compiler/assembler that understand the unified
1563 ARM-Thumb syntax is needed.
1567 config THUMB2_AVOID_R_ARM_THM_JUMP11
1568 bool "Work around buggy Thumb-2 short branch relocations in gas"
1569 depends on THUMB2_KERNEL && MODULES
1572 Various binutils versions can resolve Thumb-2 branches to
1573 locally-defined, preemptible global symbols as short-range "b.n"
1574 branch instructions.
1576 This is a problem, because there's no guarantee the final
1577 destination of the symbol, or any candidate locations for a
1578 trampoline, are within range of the branch. For this reason, the
1579 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1580 relocation in modules at all, and it makes little sense to add
1583 The symptom is that the kernel fails with an "unsupported
1584 relocation" error when loading some modules.
1586 Until fixed tools are available, passing
1587 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1588 code which hits this problem, at the cost of a bit of extra runtime
1589 stack usage in some cases.
1591 The problem is described in more detail at:
1592 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1594 Only Thumb-2 kernels are affected.
1596 Unless you are sure your tools don't have this problem, say Y.
1598 config ARM_ASM_UNIFIED
1602 bool "Use the ARM EABI to compile the kernel"
1604 This option allows for the kernel to be compiled using the latest
1605 ARM ABI (aka EABI). This is only useful if you are using a user
1606 space environment that is also compiled with EABI.
1608 Since there are major incompatibilities between the legacy ABI and
1609 EABI, especially with regard to structure member alignment, this
1610 option also changes the kernel syscall calling convention to
1611 disambiguate both ABIs and allow for backward compatibility support
1612 (selected with CONFIG_OABI_COMPAT).
1614 To use this you need GCC version 4.0.0 or later.
1617 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1618 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1621 This option preserves the old syscall interface along with the
1622 new (ARM EABI) one. It also provides a compatibility layer to
1623 intercept syscalls that have structure arguments which layout
1624 in memory differs between the legacy ABI and the new ARM EABI
1625 (only for non "thumb" binaries). This option adds a tiny
1626 overhead to all syscalls and produces a slightly larger kernel.
1627 If you know you'll be using only pure EABI user space then you
1628 can say N here. If this option is not selected and you attempt
1629 to execute a legacy ABI binary then the result will be
1630 UNPREDICTABLE (in fact it can be predicted that it won't work
1631 at all). If in doubt say Y.
1633 config ARCH_HAS_HOLES_MEMORYMODEL
1636 config ARCH_SPARSEMEM_ENABLE
1639 config ARCH_SPARSEMEM_DEFAULT
1640 def_bool ARCH_SPARSEMEM_ENABLE
1642 config ARCH_SELECT_MEMORY_MODEL
1643 def_bool ARCH_SPARSEMEM_ENABLE
1645 config HAVE_ARCH_PFN_VALID
1646 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1649 bool "High Memory Support"
1652 The address space of ARM processors is only 4 Gigabytes large
1653 and it has to accommodate user address space, kernel address
1654 space as well as some memory mapped IO. That means that, if you
1655 have a large amount of physical memory and/or IO, not all of the
1656 memory can be "permanently mapped" by the kernel. The physical
1657 memory that is not permanently mapped is called "high memory".
1659 Depending on the selected kernel/user memory split, minimum
1660 vmalloc space and actual amount of RAM, you may not need this
1661 option which should result in a slightly faster kernel.
1666 bool "Allocate 2nd-level pagetables from highmem"
1669 config HW_PERF_EVENTS
1670 bool "Enable hardware performance counter support for perf events"
1671 depends on PERF_EVENTS && CPU_HAS_PMU
1674 Enable hardware performance counter support for perf events. If
1675 disabled, perf events will use software events only.
1679 config FORCE_MAX_ZONEORDER
1680 int "Maximum zone order" if ARCH_SHMOBILE
1681 range 11 64 if ARCH_SHMOBILE
1682 default "9" if SA1111
1685 The kernel memory allocator divides physically contiguous memory
1686 blocks into "zones", where each zone is a power of two number of
1687 pages. This option selects the largest power of two that the kernel
1688 keeps in the memory allocator. If you need to allocate very large
1689 blocks of physically contiguous memory, then you may need to
1690 increase this value.
1692 This config option is actually maximum order plus one. For example,
1693 a value of 11 means that the largest free memory block is 2^10 pages.
1696 bool "Timer and CPU usage LEDs"
1697 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1698 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1699 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1700 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1701 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1702 ARCH_AT91 || ARCH_DAVINCI || \
1703 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1705 If you say Y here, the LEDs on your machine will be used
1706 to provide useful information about your current system status.
1708 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1709 be able to select which LEDs are active using the options below. If
1710 you are compiling a kernel for the EBSA-110 or the LART however, the
1711 red LED will simply flash regularly to indicate that the system is
1712 still functional. It is safe to say Y here if you have a CATS
1713 system, but the driver will do nothing.
1716 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1717 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1718 || MACH_OMAP_PERSEUS2
1720 depends on !GENERIC_CLOCKEVENTS
1721 default y if ARCH_EBSA110
1723 If you say Y here, one of the system LEDs (the green one on the
1724 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1725 will flash regularly to indicate that the system is still
1726 operational. This is mainly useful to kernel hackers who are
1727 debugging unstable kernels.
1729 The LART uses the same LED for both Timer LED and CPU usage LED
1730 functions. You may choose to use both, but the Timer LED function
1731 will overrule the CPU usage LED.
1734 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1736 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1737 || MACH_OMAP_PERSEUS2
1740 If you say Y here, the red LED will be used to give a good real
1741 time indication of CPU usage, by lighting whenever the idle task
1742 is not currently executing.
1744 The LART uses the same LED for both Timer LED and CPU usage LED
1745 functions. You may choose to use both, but the Timer LED function
1746 will overrule the CPU usage LED.
1748 config ALIGNMENT_TRAP
1750 depends on CPU_CP15_MMU
1751 default y if !ARCH_EBSA110
1752 select HAVE_PROC_CPU if PROC_FS
1754 ARM processors cannot fetch/store information which is not
1755 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1756 address divisible by 4. On 32-bit ARM processors, these non-aligned
1757 fetch/store instructions will be emulated in software if you say
1758 here, which has a severe performance impact. This is necessary for
1759 correct operation of some network protocols. With an IP-only
1760 configuration it is safe to say N, otherwise say Y.
1762 config UACCESS_WITH_MEMCPY
1763 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1764 depends on MMU && EXPERIMENTAL
1765 default y if CPU_FEROCEON
1767 Implement faster copy_to_user and clear_user methods for CPU
1768 cores where a 8-word STM instruction give significantly higher
1769 memory write throughput than a sequence of individual 32bit stores.
1771 A possible side effect is a slight increase in scheduling latency
1772 between threads sharing the same address space if they invoke
1773 such copy operations with large buffers.
1775 However, if the CPU data cache is using a write-allocate mode,
1776 this option is unlikely to provide any performance gain.
1780 prompt "Enable seccomp to safely compute untrusted bytecode"
1782 This kernel feature is useful for number crunching applications
1783 that may need to compute untrusted bytecode during their
1784 execution. By using pipes or other transports made available to
1785 the process as file descriptors supporting the read/write
1786 syscalls, it's possible to isolate those applications in
1787 their own address space using seccomp. Once seccomp is
1788 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1789 and the task is only allowed to execute a few safe syscalls
1790 defined by each seccomp mode.
1792 config CC_STACKPROTECTOR
1793 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1794 depends on EXPERIMENTAL
1796 This option turns on the -fstack-protector GCC feature. This
1797 feature puts, at the beginning of functions, a canary value on
1798 the stack just before the return address, and validates
1799 the value just before actually returning. Stack based buffer
1800 overflows (that need to overwrite this return address) now also
1801 overwrite the canary, which gets detected and the attack is then
1802 neutralized via a kernel panic.
1803 This feature requires gcc version 4.2 or above.
1805 config DEPRECATED_PARAM_STRUCT
1806 bool "Provide old way to pass kernel parameters"
1808 This was deprecated in 2001 and announced to live on for 5 years.
1809 Some old boot loaders still use this way.
1811 config ARM_FLUSH_CONSOLE_ON_RESTART
1812 bool "Force flush the console on restart"
1814 If the console is locked while the system is rebooted, the messages
1815 in the temporary logbuffer would not have propogated to all the
1816 console drivers. This option forces the console lock to be
1817 released if it failed to be acquired, which will cause all the
1818 pending messages to be flushed.
1825 bool "Flattened Device Tree support"
1827 select OF_EARLY_FLATTREE
1829 Include support for flattened device tree machine descriptions.
1831 # Compressed boot loader in ROM. Yes, we really want to ask about
1832 # TEXT and BSS so we preserve their values in the config files.
1833 config ZBOOT_ROM_TEXT
1834 hex "Compressed ROM boot loader base address"
1837 The physical address at which the ROM-able zImage is to be
1838 placed in the target. Platforms which normally make use of
1839 ROM-able zImage formats normally set this to a suitable
1840 value in their defconfig file.
1842 If ZBOOT_ROM is not enabled, this has no effect.
1844 config ZBOOT_ROM_BSS
1845 hex "Compressed ROM boot loader BSS address"
1848 The base address of an area of read/write memory in the target
1849 for the ROM-able zImage which must be available while the
1850 decompressor is running. It must be large enough to hold the
1851 entire decompressed kernel plus an additional 128 KiB.
1852 Platforms which normally make use of ROM-able zImage formats
1853 normally set this to a suitable value in their defconfig file.
1855 If ZBOOT_ROM is not enabled, this has no effect.
1858 bool "Compressed boot loader in ROM/flash"
1859 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1861 Say Y here if you intend to execute your compressed kernel image
1862 (zImage) directly from ROM or flash. If unsure, say N.
1864 config ZBOOT_ROM_MMCIF
1865 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1866 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1868 Say Y here to include experimental MMCIF loading code in the
1869 ROM-able zImage. With this enabled it is possible to write the
1870 the ROM-able zImage kernel image to an MMC card and boot the
1871 kernel straight from the reset vector. At reset the processor
1872 Mask ROM will load the first part of the the ROM-able zImage
1873 which in turn loads the rest the kernel image to RAM using the
1874 MMCIF hardware block.
1877 string "Default kernel command string"
1880 On some architectures (EBSA110 and CATS), there is currently no way
1881 for the boot loader to pass arguments to the kernel. For these
1882 architectures, you should supply some command-line options at build
1883 time by entering them here. As a minimum, you should specify the
1884 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1887 prompt "Kernel command line type" if CMDLINE != ""
1888 default CMDLINE_FROM_BOOTLOADER
1890 config CMDLINE_FROM_BOOTLOADER
1891 bool "Use bootloader kernel arguments if available"
1893 Uses the command-line options passed by the boot loader. If
1894 the boot loader doesn't provide any, the default kernel command
1895 string provided in CMDLINE will be used.
1897 config CMDLINE_EXTEND
1898 bool "Extend bootloader kernel arguments"
1900 The command-line arguments provided by the boot loader will be
1901 appended to the default kernel command string.
1903 config CMDLINE_FORCE
1904 bool "Always use the default kernel command string"
1906 Always use the default kernel command string, even if the boot
1907 loader passes other arguments to the kernel.
1908 This is useful if you cannot or don't want to change the
1909 command-line options your boot loader passes to the kernel.
1913 bool "Kernel Execute-In-Place from ROM"
1914 depends on !ZBOOT_ROM
1916 Execute-In-Place allows the kernel to run from non-volatile storage
1917 directly addressable by the CPU, such as NOR flash. This saves RAM
1918 space since the text section of the kernel is not loaded from flash
1919 to RAM. Read-write sections, such as the data section and stack,
1920 are still copied to RAM. The XIP kernel is not compressed since
1921 it has to run directly from flash, so it will take more space to
1922 store it. The flash address used to link the kernel object files,
1923 and for storing it, is configuration dependent. Therefore, if you
1924 say Y here, you must know the proper physical address where to
1925 store the kernel image depending on your own flash memory usage.
1927 Also note that the make target becomes "make xipImage" rather than
1928 "make zImage" or "make Image". The final kernel binary to put in
1929 ROM memory will be arch/arm/boot/xipImage.
1933 config XIP_PHYS_ADDR
1934 hex "XIP Kernel Physical Location"
1935 depends on XIP_KERNEL
1936 default "0x00080000"
1938 This is the physical address in your flash memory the kernel will
1939 be linked for and stored to. This address is dependent on your
1943 bool "Kexec system call (EXPERIMENTAL)"
1944 depends on EXPERIMENTAL
1946 kexec is a system call that implements the ability to shutdown your
1947 current kernel, and to start another kernel. It is like a reboot
1948 but it is independent of the system firmware. And like a reboot
1949 you can start any kernel with it, not just Linux.
1951 It is an ongoing process to be certain the hardware in a machine
1952 is properly shutdown, so do not be surprised if this code does not
1953 initially work for you. It may help to enable device hotplugging
1957 bool "Export atags in procfs"
1961 Should the atags used to boot the kernel be exported in an "atags"
1962 file in procfs. Useful with kexec.
1965 bool "Build kdump crash kernel (EXPERIMENTAL)"
1966 depends on EXPERIMENTAL
1968 Generate crash dump after being started by kexec. This should
1969 be normally only set in special crash dump kernels which are
1970 loaded in the main kernel with kexec-tools into a specially
1971 reserved region and then later executed after a crash by
1972 kdump/kexec. The crash dump kernel must be compiled to a
1973 memory address not used by the main kernel
1975 For more details see Documentation/kdump/kdump.txt
1977 config AUTO_ZRELADDR
1978 bool "Auto calculation of the decompressed kernel image address"
1979 depends on !ZBOOT_ROM && !ARCH_U300
1981 ZRELADDR is the physical address where the decompressed kernel
1982 image will be placed. If AUTO_ZRELADDR is selected, the address
1983 will be determined at run-time by masking the current IP with
1984 0xf8000000. This assumes the zImage being placed in the first 128MB
1985 from start of memory.
1989 menu "CPU Power Management"
1993 source "drivers/cpufreq/Kconfig"
1996 tristate "CPUfreq driver for i.MX CPUs"
1997 depends on ARCH_MXC && CPU_FREQ
1998 select CPU_FREQ_TABLE
2000 This enables the CPUfreq driver for i.MX CPUs.
2002 config CPU_FREQ_SA1100
2005 config CPU_FREQ_SA1110
2008 config CPU_FREQ_INTEGRATOR
2009 tristate "CPUfreq driver for ARM Integrator CPUs"
2010 depends on ARCH_INTEGRATOR && CPU_FREQ
2013 This enables the CPUfreq driver for ARM Integrator CPUs.
2015 For details, take a look at <file:Documentation/cpu-freq>.
2021 depends on CPU_FREQ && ARCH_PXA && PXA25x
2023 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2025 config CPU_FREQ_S3C64XX
2026 bool "CPUfreq support for Samsung S3C64XX CPUs"
2027 depends on CPU_FREQ && CPU_S3C6410
2032 Internal configuration node for common cpufreq on Samsung SoC
2034 config CPU_FREQ_S3C24XX
2035 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2036 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2039 This enables the CPUfreq driver for the Samsung S3C24XX family
2042 For details, take a look at <file:Documentation/cpu-freq>.
2046 config CPU_FREQ_S3C24XX_PLL
2047 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2048 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2050 Compile in support for changing the PLL frequency from the
2051 S3C24XX series CPUfreq driver. The PLL takes time to settle
2052 after a frequency change, so by default it is not enabled.
2054 This also means that the PLL tables for the selected CPU(s) will
2055 be built which may increase the size of the kernel image.
2057 config CPU_FREQ_S3C24XX_DEBUG
2058 bool "Debug CPUfreq Samsung driver core"
2059 depends on CPU_FREQ_S3C24XX
2061 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2063 config CPU_FREQ_S3C24XX_IODEBUG
2064 bool "Debug CPUfreq Samsung driver IO timing"
2065 depends on CPU_FREQ_S3C24XX
2067 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2069 config CPU_FREQ_S3C24XX_DEBUGFS
2070 bool "Export debugfs for CPUFreq"
2071 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2073 Export status information via debugfs.
2077 source "drivers/cpuidle/Kconfig"
2081 menu "Floating point emulation"
2083 comment "At least one emulation must be selected"
2086 bool "NWFPE math emulation"
2087 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2089 Say Y to include the NWFPE floating point emulator in the kernel.
2090 This is necessary to run most binaries. Linux does not currently
2091 support floating point hardware so you need to say Y here even if
2092 your machine has an FPA or floating point co-processor podule.
2094 You may say N here if you are going to load the Acorn FPEmulator
2095 early in the bootup.
2098 bool "Support extended precision"
2099 depends on FPE_NWFPE
2101 Say Y to include 80-bit support in the kernel floating-point
2102 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2103 Note that gcc does not generate 80-bit operations by default,
2104 so in most cases this option only enlarges the size of the
2105 floating point emulator without any good reason.
2107 You almost surely want to say N here.
2110 bool "FastFPE math emulation (EXPERIMENTAL)"
2111 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2113 Say Y here to include the FAST floating point emulator in the kernel.
2114 This is an experimental much faster emulator which now also has full
2115 precision for the mantissa. It does not support any exceptions.
2116 It is very simple, and approximately 3-6 times faster than NWFPE.
2118 It should be sufficient for most programs. It may be not suitable
2119 for scientific calculations, but you have to check this for yourself.
2120 If you do not feel you need a faster FP emulation you should better
2124 bool "VFP-format floating point maths"
2125 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2127 Say Y to include VFP support code in the kernel. This is needed
2128 if your hardware includes a VFP unit.
2130 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2131 release notes and additional status information.
2133 Say N if your target does not have VFP hardware.
2141 bool "Advanced SIMD (NEON) Extension support"
2142 depends on VFPv3 && CPU_V7
2144 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2149 menu "Userspace binary formats"
2151 source "fs/Kconfig.binfmt"
2154 tristate "RISC OS personality"
2157 Say Y here to include the kernel code necessary if you want to run
2158 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2159 experimental; if this sounds frightening, say N and sleep in peace.
2160 You can also say M here to compile this support as a module (which
2161 will be called arthur).
2165 menu "Power management options"
2167 source "kernel/power/Kconfig"
2169 config ARCH_SUSPEND_POSSIBLE
2170 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2171 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2172 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2177 source "net/Kconfig"
2179 source "drivers/Kconfig"
2183 source "arch/arm/Kconfig.debug"
2185 source "security/Kconfig"
2187 source "crypto/Kconfig"
2189 source "lib/Kconfig"