5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
41 config ARM_HAS_SG_CHAIN
50 config SYS_SUPPORTS_APM_EMULATION
53 config HAVE_SCHED_CLOCK
59 config ARCH_USES_GETTIMEOFFSET
63 config GENERIC_CLOCKEVENTS
66 config GENERIC_CLOCKEVENTS_BROADCAST
68 depends on GENERIC_CLOCKEVENTS
77 select GENERIC_ALLOCATOR
88 The Extended Industry Standard Architecture (EISA) bus was
89 developed as an open alternative to the IBM MicroChannel bus.
91 The EISA bus provided some of the features of the IBM MicroChannel
92 bus while maintaining backward compatibility with cards made for
93 the older ISA bus. The EISA bus saw limited use between 1988 and
94 1995 when it was made obsolete by the PCI bus.
96 Say Y here if you are building a kernel for an EISA-based machine.
106 MicroChannel Architecture is found in some IBM PS/2 machines and
107 laptops. It is a bus system similar to PCI or ISA. See
108 <file:Documentation/mca.txt> (and especially the web page given
109 there) before attempting to build an MCA bus kernel.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config HARDIRQS_SW_RESEND
132 config GENERIC_IRQ_PROBE
136 config GENERIC_LOCKBREAK
139 depends on SMP && PREEMPT
141 config RWSEM_GENERIC_SPINLOCK
145 config RWSEM_XCHGADD_ALGORITHM
148 config ARCH_HAS_ILOG2_U32
151 config ARCH_HAS_ILOG2_U64
154 config ARCH_HAS_CPUFREQ
157 Internal node to signify that the ARCH has CPUFREQ support
158 and that the relevant menu configurations are displayed for
161 config ARCH_HAS_CPU_IDLE_WAIT
164 config GENERIC_HWEIGHT
168 config GENERIC_CALIBRATE_DELAY
172 config ARCH_MAY_HAVE_PC_FDC
178 config NEED_DMA_MAP_STATE
181 config GENERIC_ISA_DMA
192 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
193 default DRAM_BASE if REMAP_VECTORS_TO_RAM
196 The base address of exception vectors.
198 config ARM_PATCH_PHYS_VIRT
199 bool "Patch physical to virtual translations at runtime" if EMBEDDED
201 depends on !XIP_KERNEL && MMU
202 depends on !ARCH_REALVIEW || !SPARSEMEM
204 Patch phys-to-virt and virt-to-phys translation functions at
205 boot and module load time according to the position of the
206 kernel in system memory.
208 This can only be used with non-XIP MMU kernels where the base
209 of physical memory is at a 16MB boundary.
211 Only disable this option if you know that you do not require
212 this feature (eg, building a kernel for a single machine) and
213 you need to shrink the kernel to the minimal size.
215 config NEED_MACH_MEMORY_H
218 Select this when mach/memory.h is required to provide special
219 definitions for this platform. The need for mach/memory.h should
220 be avoided when possible.
223 hex "Physical address of main memory"
224 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
226 Please provide the physical address corresponding to the
227 location of main memory in your system.
233 source "init/Kconfig"
235 source "kernel/Kconfig.freezer"
240 bool "MMU-based Paged Memory Management Support"
243 Select if you want MMU-based virtualised addressing space
244 support by paged memory management. If unsure, say 'Y'.
247 # The "ARM system type" choice list is ordered alphabetically by option
248 # text. Please add new entries in the option alphabetic order.
251 prompt "ARM system type"
252 default ARCH_VERSATILE
254 config ARCH_INTEGRATOR
255 bool "ARM Ltd. Integrator family"
257 select ARCH_HAS_CPUFREQ
259 select HAVE_MACH_CLKDEV
261 select GENERIC_CLOCKEVENTS
262 select PLAT_VERSATILE
263 select PLAT_VERSATILE_FPGA_IRQ
264 select NEED_MACH_MEMORY_H
266 Support for ARM's Integrator platform.
269 bool "ARM Ltd. RealView family"
272 select HAVE_MACH_CLKDEV
274 select GENERIC_CLOCKEVENTS
275 select ARCH_WANT_OPTIONAL_GPIOLIB
276 select PLAT_VERSATILE
277 select PLAT_VERSATILE_CLCD
278 select ARM_TIMER_SP804
279 select GPIO_PL061 if GPIOLIB
280 select NEED_MACH_MEMORY_H
282 This enables support for ARM Ltd RealView boards.
284 config ARCH_VERSATILE
285 bool "ARM Ltd. Versatile family"
289 select HAVE_MACH_CLKDEV
291 select GENERIC_CLOCKEVENTS
292 select ARCH_WANT_OPTIONAL_GPIOLIB
293 select PLAT_VERSATILE
294 select PLAT_VERSATILE_CLCD
295 select PLAT_VERSATILE_FPGA_IRQ
296 select ARM_TIMER_SP804
298 This enables support for ARM Ltd Versatile board.
301 bool "ARM Ltd. Versatile Express family"
302 select ARCH_WANT_OPTIONAL_GPIOLIB
304 select ARM_TIMER_SP804
306 select HAVE_MACH_CLKDEV
307 select GENERIC_CLOCKEVENTS
309 select HAVE_PATA_PLATFORM
311 select PLAT_VERSATILE
312 select PLAT_VERSATILE_CLCD
314 This enables support for the ARM Ltd Versatile Express boards.
318 select ARCH_REQUIRE_GPIOLIB
322 This enables support for systems based on the Atmel AT91RM9200,
323 AT91SAM9 and AT91CAP9 processors.
326 bool "Broadcom BCMRING"
330 select ARM_TIMER_SP804
332 select GENERIC_CLOCKEVENTS
333 select ARCH_WANT_OPTIONAL_GPIOLIB
335 Support for Broadcom's BCMRing platform.
338 bool "Calxeda Highbank-based"
339 select ARCH_WANT_OPTIONAL_GPIOLIB
342 select ARM_TIMER_SP804
345 select GENERIC_CLOCKEVENTS
347 select MIGHT_HAVE_CACHE_L2X0
350 Support for the Calxeda Highbank SoC based boards.
353 bool "Cirrus Logic CLPS711x/EP721x-based"
355 select ARCH_USES_GETTIMEOFFSET
356 select NEED_MACH_MEMORY_H
358 Support for Cirrus Logic 711x/721x based boards.
361 bool "Cavium Networks CNS3XXX family"
363 select GENERIC_CLOCKEVENTS
365 select MIGHT_HAVE_CACHE_L2X0
366 select MIGHT_HAVE_PCI
367 select PCI_DOMAINS if PCI
369 Support for Cavium Networks CNS3XXX platform.
372 bool "Cortina Systems Gemini"
374 select ARCH_REQUIRE_GPIOLIB
375 select ARCH_USES_GETTIMEOFFSET
377 Support for the Cortina Systems Gemini family SoCs
380 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
383 select GENERIC_CLOCKEVENTS
385 select GENERIC_IRQ_CHIP
386 select MIGHT_HAVE_CACHE_L2X0
390 Support for CSR SiRFSoC ARM Cortex A9 Platform
397 select ARCH_USES_GETTIMEOFFSET
398 select NEED_MACH_MEMORY_H
400 This is an evaluation board for the StrongARM processor available
401 from Digital. It has limited hardware on-board, including an
402 Ethernet interface, two PCMCIA sockets, two serial ports and a
411 select ARCH_REQUIRE_GPIOLIB
412 select ARCH_HAS_HOLES_MEMORYMODEL
413 select ARCH_USES_GETTIMEOFFSET
414 select NEED_MACH_MEMORY_H
416 This enables support for the Cirrus EP93xx series of CPUs.
418 config ARCH_FOOTBRIDGE
422 select GENERIC_CLOCKEVENTS
424 select NEED_MACH_MEMORY_H
426 Support for systems based on the DC21285 companion chip
427 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
430 bool "Freescale MXC/iMX-based"
431 select GENERIC_CLOCKEVENTS
432 select ARCH_REQUIRE_GPIOLIB
435 select GENERIC_IRQ_CHIP
436 select HAVE_SCHED_CLOCK
437 select MULTI_IRQ_HANDLER
439 Support for Freescale MXC/iMX-based family of processors
442 bool "Freescale MXS-based"
443 select GENERIC_CLOCKEVENTS
444 select ARCH_REQUIRE_GPIOLIB
448 Support for Freescale MXS-based family of processors
451 bool "Hilscher NetX based"
455 select GENERIC_CLOCKEVENTS
457 This enables support for systems based on the Hilscher NetX Soc
460 bool "Hynix HMS720x-based"
463 select ARCH_USES_GETTIMEOFFSET
465 This enables support for systems based on the Hynix HMS720x
473 select ARCH_SUPPORTS_MSI
475 select NEED_MACH_MEMORY_H
477 Support for Intel's IOP13XX (XScale) family of processors.
485 select ARCH_REQUIRE_GPIOLIB
487 Support for Intel's 80219 and IOP32X (XScale) family of
496 select ARCH_REQUIRE_GPIOLIB
498 Support for Intel's IOP33X (XScale) family of processors.
505 select ARCH_USES_GETTIMEOFFSET
506 select NEED_MACH_MEMORY_H
508 Support for Intel's IXP23xx (XScale) family of processors.
511 bool "IXP2400/2800-based"
515 select ARCH_USES_GETTIMEOFFSET
516 select NEED_MACH_MEMORY_H
518 Support for Intel's IXP2400/2800 (XScale) family of processors.
526 select GENERIC_CLOCKEVENTS
527 select HAVE_SCHED_CLOCK
528 select MIGHT_HAVE_PCI
529 select DMABOUNCE if PCI
531 Support for Intel's IXP4XX (XScale) family of processors.
537 select ARCH_REQUIRE_GPIOLIB
538 select GENERIC_CLOCKEVENTS
541 Support for the Marvell Dove SoC 88AP510
544 bool "Marvell Kirkwood"
547 select ARCH_REQUIRE_GPIOLIB
548 select GENERIC_CLOCKEVENTS
551 Support for the following Marvell Kirkwood series SoCs:
552 88F6180, 88F6192 and 88F6281.
558 select ARCH_REQUIRE_GPIOLIB
561 select USB_ARCH_HAS_OHCI
563 select GENERIC_CLOCKEVENTS
565 Support for the NXP LPC32XX family of processors
568 bool "Marvell MV78xx0"
571 select ARCH_REQUIRE_GPIOLIB
572 select GENERIC_CLOCKEVENTS
575 Support for the following Marvell MV78xx0 series SoCs:
583 select ARCH_REQUIRE_GPIOLIB
584 select GENERIC_CLOCKEVENTS
587 Support for the following Marvell Orion 5x series SoCs:
588 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
589 Orion-2 (5281), Orion-1-90 (6183).
592 bool "Marvell PXA168/910/MMP2"
594 select ARCH_REQUIRE_GPIOLIB
596 select GENERIC_CLOCKEVENTS
597 select HAVE_SCHED_CLOCK
601 select GENERIC_ALLOCATOR
603 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
606 bool "Micrel/Kendin KS8695"
608 select ARCH_REQUIRE_GPIOLIB
609 select ARCH_USES_GETTIMEOFFSET
610 select NEED_MACH_MEMORY_H
612 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
613 System-on-Chip devices.
616 bool "Nuvoton W90X900 CPU"
618 select ARCH_REQUIRE_GPIOLIB
621 select GENERIC_CLOCKEVENTS
623 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
624 At present, the w90x900 has been renamed nuc900, regarding
625 the ARM series product line, you can login the following
626 link address to know more.
628 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
629 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
635 select GENERIC_CLOCKEVENTS
638 select HAVE_SCHED_CLOCK
639 select MIGHT_HAVE_CACHE_L2X0
640 select ARCH_HAS_CPUFREQ
642 This enables support for NVIDIA Tegra based systems (Tegra APX,
643 Tegra 6xx and Tegra 2 series).
645 config ARCH_PICOXCELL
646 bool "Picochip picoXcell"
647 select ARCH_REQUIRE_GPIOLIB
648 select ARM_PATCH_PHYS_VIRT
652 select GENERIC_CLOCKEVENTS
654 select HAVE_SCHED_CLOCK
659 This enables support for systems based on the Picochip picoXcell
660 family of Femtocell devices. The picoxcell support requires device tree
664 bool "Philips Nexperia PNX4008 Mobile"
667 select ARCH_USES_GETTIMEOFFSET
669 This enables support for Philips PNX4008 mobile platform.
672 bool "PXA2xx/PXA3xx-based"
675 select ARCH_HAS_CPUFREQ
678 select ARCH_REQUIRE_GPIOLIB
679 select GENERIC_CLOCKEVENTS
680 select HAVE_SCHED_CLOCK
685 select MULTI_IRQ_HANDLER
686 select ARM_CPU_SUSPEND if PM
689 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
694 select GENERIC_CLOCKEVENTS
695 select ARCH_REQUIRE_GPIOLIB
698 Support for Qualcomm MSM/QSD based systems. This runs on the
699 apps processor of the MSM/QSD and depends on a shared memory
700 interface to the modem processor which runs the baseband
701 stack and controls some vital subsystems
702 (clock and power control, etc).
705 bool "Renesas SH-Mobile / R-Mobile"
708 select HAVE_MACH_CLKDEV
709 select GENERIC_CLOCKEVENTS
710 select MIGHT_HAVE_CACHE_L2X0
713 select MULTI_IRQ_HANDLER
714 select PM_GENERIC_DOMAINS if PM
715 select NEED_MACH_MEMORY_H
717 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
724 select ARCH_MAY_HAVE_PC_FDC
725 select HAVE_PATA_PLATFORM
728 select ARCH_SPARSEMEM_ENABLE
729 select ARCH_USES_GETTIMEOFFSET
731 select NEED_MACH_MEMORY_H
733 On the Acorn Risc-PC, Linux can support the internal IDE disk and
734 CD-ROM interface, serial and parallel port, and the floppy drive.
741 select ARCH_SPARSEMEM_ENABLE
743 select ARCH_HAS_CPUFREQ
745 select GENERIC_CLOCKEVENTS
747 select HAVE_SCHED_CLOCK
749 select ARCH_REQUIRE_GPIOLIB
751 select NEED_MACH_MEMORY_H
753 Support for StrongARM 11x0 based boards.
756 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
758 select ARCH_HAS_CPUFREQ
761 select ARCH_USES_GETTIMEOFFSET
762 select HAVE_S3C2410_I2C if I2C
764 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
765 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
766 the Samsung SMDK2410 development board (and derivatives).
768 Note, the S3C2416 and the S3C2450 are so close that they even share
769 the same SoC ID code. This means that there is no separate machine
770 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
773 bool "Samsung S3C64XX"
781 select ARCH_USES_GETTIMEOFFSET
782 select ARCH_HAS_CPUFREQ
783 select ARCH_REQUIRE_GPIOLIB
784 select SAMSUNG_CLKSRC
785 select SAMSUNG_IRQ_VIC_TIMER
786 select S3C_GPIO_TRACK
788 select USB_ARCH_HAS_OHCI
789 select SAMSUNG_GPIOLIB_4BIT
790 select HAVE_S3C2410_I2C if I2C
791 select HAVE_S3C2410_WATCHDOG if WATCHDOG
793 Samsung S3C64XX series based systems
796 bool "Samsung S5P6440 S5P6450"
802 select HAVE_S3C2410_WATCHDOG if WATCHDOG
803 select GENERIC_CLOCKEVENTS
804 select HAVE_SCHED_CLOCK
805 select HAVE_S3C2410_I2C if I2C
806 select HAVE_S3C_RTC if RTC_CLASS
808 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
812 bool "Samsung S5PC100"
817 select ARM_L1_CACHE_SHIFT_6
818 select ARCH_USES_GETTIMEOFFSET
819 select HAVE_S3C2410_I2C if I2C
820 select HAVE_S3C_RTC if RTC_CLASS
821 select HAVE_S3C2410_WATCHDOG if WATCHDOG
823 Samsung S5PC100 series based systems
826 bool "Samsung S5PV210/S5PC110"
828 select ARCH_SPARSEMEM_ENABLE
829 select ARCH_HAS_HOLES_MEMORYMODEL
834 select ARM_L1_CACHE_SHIFT_6
835 select ARCH_HAS_CPUFREQ
836 select GENERIC_CLOCKEVENTS
837 select HAVE_SCHED_CLOCK
838 select HAVE_S3C2410_I2C if I2C
839 select HAVE_S3C_RTC if RTC_CLASS
840 select HAVE_S3C2410_WATCHDOG if WATCHDOG
841 select NEED_MACH_MEMORY_H
843 Samsung S5PV210/S5PC110 series based systems
846 bool "SAMSUNG EXYNOS"
848 select ARCH_SPARSEMEM_ENABLE
849 select ARCH_HAS_HOLES_MEMORYMODEL
853 select ARCH_HAS_CPUFREQ
854 select GENERIC_CLOCKEVENTS
855 select HAVE_S3C_RTC if RTC_CLASS
856 select HAVE_S3C2410_I2C if I2C
857 select HAVE_S3C2410_WATCHDOG if WATCHDOG
858 select NEED_MACH_MEMORY_H
860 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
869 select ARCH_USES_GETTIMEOFFSET
870 select NEED_MACH_MEMORY_H
872 Support for the StrongARM based Digital DNARD machine, also known
873 as "Shark" (<http://www.shark-linux.de/shark.html>).
876 bool "Telechips TCC ARM926-based systems"
881 select GENERIC_CLOCKEVENTS
883 Support for Telechips TCC ARM926-based systems.
886 bool "ST-Ericsson U300 Series"
890 select HAVE_SCHED_CLOCK
893 select ARM_PATCH_PHYS_VIRT
895 select GENERIC_CLOCKEVENTS
897 select HAVE_MACH_CLKDEV
899 select ARCH_REQUIRE_GPIOLIB
900 select NEED_MACH_MEMORY_H
902 Support for ST-Ericsson U300 series mobile platforms.
905 bool "ST-Ericsson U8500 Series"
908 select GENERIC_CLOCKEVENTS
910 select ARCH_REQUIRE_GPIOLIB
911 select ARCH_HAS_CPUFREQ
912 select MIGHT_HAVE_CACHE_L2X0
914 Support for ST-Ericsson's Ux500 architecture
917 bool "STMicroelectronics Nomadik"
922 select GENERIC_CLOCKEVENTS
923 select MIGHT_HAVE_CACHE_L2X0
924 select ARCH_REQUIRE_GPIOLIB
926 Support for the Nomadik platform by ST-Ericsson
930 select GENERIC_CLOCKEVENTS
931 select ARCH_REQUIRE_GPIOLIB
935 select GENERIC_ALLOCATOR
936 select GENERIC_IRQ_CHIP
937 select ARCH_HAS_HOLES_MEMORYMODEL
939 Support for TI's DaVinci platform.
944 select ARCH_REQUIRE_GPIOLIB
945 select ARCH_HAS_CPUFREQ
947 select GENERIC_CLOCKEVENTS
948 select HAVE_SCHED_CLOCK
949 select ARCH_HAS_HOLES_MEMORYMODEL
951 Support for TI's OMAP platform (OMAP1/2/3/4).
956 select ARCH_REQUIRE_GPIOLIB
959 select GENERIC_CLOCKEVENTS
962 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
965 bool "VIA/WonderMedia 85xx"
968 select ARCH_HAS_CPUFREQ
969 select GENERIC_CLOCKEVENTS
970 select ARCH_REQUIRE_GPIOLIB
973 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
976 bool "Xilinx Zynq ARM Cortex A9 Platform"
978 select GENERIC_CLOCKEVENTS
983 select MIGHT_HAVE_CACHE_L2X0
986 Support for Xilinx Zynq ARM Cortex A9 Platform
990 # This is sorted alphabetically by mach-* pathname. However, plat-*
991 # Kconfigs may be included either alphabetically (according to the
992 # plat- suffix) or along side the corresponding mach-* source.
994 source "arch/arm/mach-at91/Kconfig"
996 source "arch/arm/mach-bcmring/Kconfig"
998 source "arch/arm/mach-clps711x/Kconfig"
1000 source "arch/arm/mach-cns3xxx/Kconfig"
1002 source "arch/arm/mach-davinci/Kconfig"
1004 source "arch/arm/mach-dove/Kconfig"
1006 source "arch/arm/mach-ep93xx/Kconfig"
1008 source "arch/arm/mach-footbridge/Kconfig"
1010 source "arch/arm/mach-gemini/Kconfig"
1012 source "arch/arm/mach-h720x/Kconfig"
1014 source "arch/arm/mach-integrator/Kconfig"
1016 source "arch/arm/mach-iop32x/Kconfig"
1018 source "arch/arm/mach-iop33x/Kconfig"
1020 source "arch/arm/mach-iop13xx/Kconfig"
1022 source "arch/arm/mach-ixp4xx/Kconfig"
1024 source "arch/arm/mach-ixp2000/Kconfig"
1026 source "arch/arm/mach-ixp23xx/Kconfig"
1028 source "arch/arm/mach-kirkwood/Kconfig"
1030 source "arch/arm/mach-ks8695/Kconfig"
1032 source "arch/arm/mach-lpc32xx/Kconfig"
1034 source "arch/arm/mach-msm/Kconfig"
1036 source "arch/arm/mach-mv78xx0/Kconfig"
1038 source "arch/arm/plat-mxc/Kconfig"
1040 source "arch/arm/mach-mxs/Kconfig"
1042 source "arch/arm/mach-netx/Kconfig"
1044 source "arch/arm/mach-nomadik/Kconfig"
1045 source "arch/arm/plat-nomadik/Kconfig"
1047 source "arch/arm/plat-omap/Kconfig"
1049 source "arch/arm/mach-omap1/Kconfig"
1051 source "arch/arm/mach-omap2/Kconfig"
1053 source "arch/arm/mach-orion5x/Kconfig"
1055 source "arch/arm/mach-pxa/Kconfig"
1056 source "arch/arm/plat-pxa/Kconfig"
1058 source "arch/arm/mach-mmp/Kconfig"
1060 source "arch/arm/mach-realview/Kconfig"
1062 source "arch/arm/mach-sa1100/Kconfig"
1064 source "arch/arm/plat-samsung/Kconfig"
1065 source "arch/arm/plat-s3c24xx/Kconfig"
1066 source "arch/arm/plat-s5p/Kconfig"
1068 source "arch/arm/plat-spear/Kconfig"
1070 source "arch/arm/plat-tcc/Kconfig"
1073 source "arch/arm/mach-s3c2410/Kconfig"
1074 source "arch/arm/mach-s3c2412/Kconfig"
1075 source "arch/arm/mach-s3c2416/Kconfig"
1076 source "arch/arm/mach-s3c2440/Kconfig"
1077 source "arch/arm/mach-s3c2443/Kconfig"
1081 source "arch/arm/mach-s3c64xx/Kconfig"
1084 source "arch/arm/mach-s5p64x0/Kconfig"
1086 source "arch/arm/mach-s5pc100/Kconfig"
1088 source "arch/arm/mach-s5pv210/Kconfig"
1090 source "arch/arm/mach-exynos/Kconfig"
1092 source "arch/arm/mach-shmobile/Kconfig"
1094 source "arch/arm/mach-tegra/Kconfig"
1096 source "arch/arm/mach-u300/Kconfig"
1098 source "arch/arm/mach-ux500/Kconfig"
1100 source "arch/arm/mach-versatile/Kconfig"
1102 source "arch/arm/mach-vexpress/Kconfig"
1103 source "arch/arm/plat-versatile/Kconfig"
1105 source "arch/arm/mach-vt8500/Kconfig"
1107 source "arch/arm/mach-w90x900/Kconfig"
1109 # Definitions to make life easier
1115 select GENERIC_CLOCKEVENTS
1116 select HAVE_SCHED_CLOCK
1121 select GENERIC_IRQ_CHIP
1122 select HAVE_SCHED_CLOCK
1127 config PLAT_VERSATILE
1130 config ARM_TIMER_SP804
1134 source arch/arm/mm/Kconfig
1137 bool "Enable iWMMXt support"
1138 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1139 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1141 Enable support for iWMMXt context switching at run time if
1142 running on a CPU that supports it.
1144 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1147 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1151 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1152 (!ARCH_OMAP3 || OMAP3_EMU)
1156 config MULTI_IRQ_HANDLER
1159 Allow each machine to specify it's own IRQ handler at run time.
1162 source "arch/arm/Kconfig-nommu"
1165 config ARM_ERRATA_411920
1166 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1167 depends on CPU_V6 || CPU_V6K
1169 Invalidation of the Instruction Cache operation can
1170 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1171 It does not affect the MPCore. This option enables the ARM Ltd.
1172 recommended workaround.
1174 config ARM_ERRATA_430973
1175 bool "ARM errata: Stale prediction on replaced interworking branch"
1178 This option enables the workaround for the 430973 Cortex-A8
1179 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1180 interworking branch is replaced with another code sequence at the
1181 same virtual address, whether due to self-modifying code or virtual
1182 to physical address re-mapping, Cortex-A8 does not recover from the
1183 stale interworking branch prediction. This results in Cortex-A8
1184 executing the new code sequence in the incorrect ARM or Thumb state.
1185 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1186 and also flushes the branch target cache at every context switch.
1187 Note that setting specific bits in the ACTLR register may not be
1188 available in non-secure mode.
1190 config ARM_ERRATA_458693
1191 bool "ARM errata: Processor deadlock when a false hazard is created"
1194 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1195 erratum. For very specific sequences of memory operations, it is
1196 possible for a hazard condition intended for a cache line to instead
1197 be incorrectly associated with a different cache line. This false
1198 hazard might then cause a processor deadlock. The workaround enables
1199 the L1 caching of the NEON accesses and disables the PLD instruction
1200 in the ACTLR register. Note that setting specific bits in the ACTLR
1201 register may not be available in non-secure mode.
1203 config ARM_ERRATA_460075
1204 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1207 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1208 erratum. Any asynchronous access to the L2 cache may encounter a
1209 situation in which recent store transactions to the L2 cache are lost
1210 and overwritten with stale memory contents from external memory. The
1211 workaround disables the write-allocate mode for the L2 cache via the
1212 ACTLR register. Note that setting specific bits in the ACTLR register
1213 may not be available in non-secure mode.
1215 config ARM_ERRATA_742230
1216 bool "ARM errata: DMB operation may be faulty"
1217 depends on CPU_V7 && SMP
1219 This option enables the workaround for the 742230 Cortex-A9
1220 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1221 between two write operations may not ensure the correct visibility
1222 ordering of the two writes. This workaround sets a specific bit in
1223 the diagnostic register of the Cortex-A9 which causes the DMB
1224 instruction to behave as a DSB, ensuring the correct behaviour of
1227 config ARM_ERRATA_742231
1228 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1229 depends on CPU_V7 && SMP
1231 This option enables the workaround for the 742231 Cortex-A9
1232 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1233 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1234 accessing some data located in the same cache line, may get corrupted
1235 data due to bad handling of the address hazard when the line gets
1236 replaced from one of the CPUs at the same time as another CPU is
1237 accessing it. This workaround sets specific bits in the diagnostic
1238 register of the Cortex-A9 which reduces the linefill issuing
1239 capabilities of the processor.
1241 config PL310_ERRATA_588369
1242 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1243 depends on CACHE_L2X0
1245 The PL310 L2 cache controller implements three types of Clean &
1246 Invalidate maintenance operations: by Physical Address
1247 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1248 They are architecturally defined to behave as the execution of a
1249 clean operation followed immediately by an invalidate operation,
1250 both performing to the same memory location. This functionality
1251 is not correctly implemented in PL310 as clean lines are not
1252 invalidated as a result of these operations.
1254 config ARM_ERRATA_720789
1255 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1256 depends on CPU_V7 && SMP
1258 This option enables the workaround for the 720789 Cortex-A9 (prior to
1259 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1260 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1261 As a consequence of this erratum, some TLB entries which should be
1262 invalidated are not, resulting in an incoherency in the system page
1263 tables. The workaround changes the TLB flushing routines to invalidate
1264 entries regardless of the ASID.
1266 config PL310_ERRATA_727915
1267 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1268 depends on CACHE_L2X0
1270 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1271 operation (offset 0x7FC). This operation runs in background so that
1272 PL310 can handle normal accesses while it is in progress. Under very
1273 rare circumstances, due to this erratum, write data can be lost when
1274 PL310 treats a cacheable write transaction during a Clean &
1275 Invalidate by Way operation.
1277 config ARM_ERRATA_743622
1278 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1281 This option enables the workaround for the 743622 Cortex-A9
1282 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1283 optimisation in the Cortex-A9 Store Buffer may lead to data
1284 corruption. This workaround sets a specific bit in the diagnostic
1285 register of the Cortex-A9 which disables the Store Buffer
1286 optimisation, preventing the defect from occurring. This has no
1287 visible impact on the overall performance or power consumption of the
1290 config ARM_ERRATA_751472
1291 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1292 depends on CPU_V7 && SMP
1294 This option enables the workaround for the 751472 Cortex-A9 (prior
1295 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1296 completion of a following broadcasted operation if the second
1297 operation is received by a CPU before the ICIALLUIS has completed,
1298 potentially leading to corrupted entries in the cache or TLB.
1300 config ARM_ERRATA_753970
1301 bool "ARM errata: cache sync operation may be faulty"
1302 depends on CACHE_PL310
1304 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1306 Under some condition the effect of cache sync operation on
1307 the store buffer still remains when the operation completes.
1308 This means that the store buffer is always asked to drain and
1309 this prevents it from merging any further writes. The workaround
1310 is to replace the normal offset of cache sync operation (0x730)
1311 by another offset targeting an unmapped PL310 register 0x740.
1312 This has the same effect as the cache sync operation: store buffer
1313 drain and waiting for all buffers empty.
1315 config ARM_ERRATA_754322
1316 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1319 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1320 r3p*) erratum. A speculative memory access may cause a page table walk
1321 which starts prior to an ASID switch but completes afterwards. This
1322 can populate the micro-TLB with a stale entry which may be hit with
1323 the new ASID. This workaround places two dsb instructions in the mm
1324 switching code so that no page table walks can cross the ASID switch.
1326 config ARM_ERRATA_754327
1327 bool "ARM errata: no automatic Store Buffer drain"
1328 depends on CPU_V7 && SMP
1330 This option enables the workaround for the 754327 Cortex-A9 (prior to
1331 r2p0) erratum. The Store Buffer does not have any automatic draining
1332 mechanism and therefore a livelock may occur if an external agent
1333 continuously polls a memory location waiting to observe an update.
1334 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1335 written polling loops from denying visibility of updates to memory.
1337 config ARM_ERRATA_364296
1338 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1339 depends on CPU_V6 && !SMP
1341 This options enables the workaround for the 364296 ARM1136
1342 r0p2 erratum (possible cache data corruption with
1343 hit-under-miss enabled). It sets the undocumented bit 31 in
1344 the auxiliary control register and the FI bit in the control
1345 register, thus disabling hit-under-miss without putting the
1346 processor into full low interrupt latency mode. ARM11MPCore
1349 config ARM_ERRATA_764369
1350 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1351 depends on CPU_V7 && SMP
1353 This option enables the workaround for erratum 764369
1354 affecting Cortex-A9 MPCore with two or more processors (all
1355 current revisions). Under certain timing circumstances, a data
1356 cache line maintenance operation by MVA targeting an Inner
1357 Shareable memory region may fail to proceed up to either the
1358 Point of Coherency or to the Point of Unification of the
1359 system. This workaround adds a DSB instruction before the
1360 relevant cache maintenance functions and sets a specific bit
1361 in the diagnostic control register of the SCU.
1365 source "arch/arm/common/Kconfig"
1375 Find out whether you have ISA slots on your motherboard. ISA is the
1376 name of a bus system, i.e. the way the CPU talks to the other stuff
1377 inside your box. Other bus systems are PCI, EISA, MicroChannel
1378 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1379 newer boards don't support it. If you have ISA, say Y, otherwise N.
1381 # Select ISA DMA controller support
1386 # Select ISA DMA interface
1391 bool "PCI support" if MIGHT_HAVE_PCI
1393 Find out whether you have a PCI motherboard. PCI is the name of a
1394 bus system, i.e. the way the CPU talks to the other stuff inside
1395 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1396 VESA. If you have PCI, say Y, otherwise N.
1402 config PCI_NANOENGINE
1403 bool "BSE nanoEngine PCI support"
1404 depends on SA1100_NANOENGINE
1406 Enable PCI on the BSE nanoEngine board.
1411 # Select the host bridge type
1412 config PCI_HOST_VIA82C505
1414 depends on PCI && ARCH_SHARK
1417 config PCI_HOST_ITE8152
1419 depends on PCI && MACH_ARMCORE
1423 source "drivers/pci/Kconfig"
1425 source "drivers/pcmcia/Kconfig"
1429 menu "Kernel Features"
1431 source "kernel/time/Kconfig"
1434 bool "Symmetric Multi-Processing"
1435 depends on CPU_V6K || CPU_V7
1436 depends on GENERIC_CLOCKEVENTS
1437 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1438 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1439 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1440 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
1442 select USE_GENERIC_SMP_HELPERS
1443 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1445 This enables support for systems with more than one CPU. If you have
1446 a system with only one CPU, like most personal computers, say N. If
1447 you have a system with more than one CPU, say Y.
1449 If you say N here, the kernel will run on single and multiprocessor
1450 machines, but will use only one CPU of a multiprocessor machine. If
1451 you say Y here, the kernel will run on many, but not all, single
1452 processor machines. On a single processor machine, the kernel will
1453 run faster if you say N here.
1455 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1456 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1457 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1459 If you don't know what to do here, say N.
1462 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1463 depends on EXPERIMENTAL
1464 depends on SMP && !XIP_KERNEL
1467 SMP kernels contain instructions which fail on non-SMP processors.
1468 Enabling this option allows the kernel to modify itself to make
1469 these instructions safe. Disabling it allows about 1K of space
1472 If you don't know what to do here, say Y.
1474 config ARM_CPU_TOPOLOGY
1475 bool "Support cpu topology definition"
1476 depends on SMP && CPU_V7
1479 Support ARM cpu topology definition. The MPIDR register defines
1480 affinity between processors which is then used to describe the cpu
1481 topology of an ARM System.
1484 bool "Multi-core scheduler support"
1485 depends on ARM_CPU_TOPOLOGY
1487 Multi-core scheduler support improves the CPU scheduler's decision
1488 making when dealing with multi-core CPU chips at a cost of slightly
1489 increased overhead in some places. If unsure say N here.
1492 bool "SMT scheduler support"
1493 depends on ARM_CPU_TOPOLOGY
1495 Improves the CPU scheduler's decision making when dealing with
1496 MultiThreading at a cost of slightly increased overhead in some
1497 places. If unsure say N here.
1502 This option enables support for the ARM system coherency unit
1509 This options enables support for the ARM timer and watchdog unit
1512 prompt "Memory split"
1515 Select the desired split between kernel and user memory.
1517 If you are not absolutely sure what you are doing, leave this
1521 bool "3G/1G user/kernel split"
1523 bool "2G/2G user/kernel split"
1525 bool "1G/3G user/kernel split"
1530 default 0x40000000 if VMSPLIT_1G
1531 default 0x80000000 if VMSPLIT_2G
1535 int "Maximum number of CPUs (2-32)"
1541 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1542 depends on SMP && HOTPLUG && EXPERIMENTAL
1544 Say Y here to experiment with turning CPUs off and on. CPUs
1545 can be controlled through /sys/devices/system/cpu.
1548 bool "Use local timer interrupts"
1551 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1553 Enable support for local timers on SMP platforms, rather then the
1554 legacy IPI broadcast method. Local timers allows the system
1555 accounting to be spread across the timer interval, preventing a
1556 "thundering herd" at every timer tick.
1558 source kernel/Kconfig.preempt
1562 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1563 ARCH_S5PV210 || ARCH_EXYNOS4
1564 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1565 default AT91_TIMER_HZ if ARCH_AT91
1566 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1569 config THUMB2_KERNEL
1570 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1571 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1573 select ARM_ASM_UNIFIED
1576 By enabling this option, the kernel will be compiled in
1577 Thumb-2 mode. A compiler/assembler that understand the unified
1578 ARM-Thumb syntax is needed.
1582 config THUMB2_AVOID_R_ARM_THM_JUMP11
1583 bool "Work around buggy Thumb-2 short branch relocations in gas"
1584 depends on THUMB2_KERNEL && MODULES
1587 Various binutils versions can resolve Thumb-2 branches to
1588 locally-defined, preemptible global symbols as short-range "b.n"
1589 branch instructions.
1591 This is a problem, because there's no guarantee the final
1592 destination of the symbol, or any candidate locations for a
1593 trampoline, are within range of the branch. For this reason, the
1594 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1595 relocation in modules at all, and it makes little sense to add
1598 The symptom is that the kernel fails with an "unsupported
1599 relocation" error when loading some modules.
1601 Until fixed tools are available, passing
1602 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1603 code which hits this problem, at the cost of a bit of extra runtime
1604 stack usage in some cases.
1606 The problem is described in more detail at:
1607 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1609 Only Thumb-2 kernels are affected.
1611 Unless you are sure your tools don't have this problem, say Y.
1613 config ARM_ASM_UNIFIED
1617 bool "Use the ARM EABI to compile the kernel"
1619 This option allows for the kernel to be compiled using the latest
1620 ARM ABI (aka EABI). This is only useful if you are using a user
1621 space environment that is also compiled with EABI.
1623 Since there are major incompatibilities between the legacy ABI and
1624 EABI, especially with regard to structure member alignment, this
1625 option also changes the kernel syscall calling convention to
1626 disambiguate both ABIs and allow for backward compatibility support
1627 (selected with CONFIG_OABI_COMPAT).
1629 To use this you need GCC version 4.0.0 or later.
1632 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1633 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1636 This option preserves the old syscall interface along with the
1637 new (ARM EABI) one. It also provides a compatibility layer to
1638 intercept syscalls that have structure arguments which layout
1639 in memory differs between the legacy ABI and the new ARM EABI
1640 (only for non "thumb" binaries). This option adds a tiny
1641 overhead to all syscalls and produces a slightly larger kernel.
1642 If you know you'll be using only pure EABI user space then you
1643 can say N here. If this option is not selected and you attempt
1644 to execute a legacy ABI binary then the result will be
1645 UNPREDICTABLE (in fact it can be predicted that it won't work
1646 at all). If in doubt say Y.
1648 config ARCH_HAS_HOLES_MEMORYMODEL
1651 config ARCH_SPARSEMEM_ENABLE
1654 config ARCH_SPARSEMEM_DEFAULT
1655 def_bool ARCH_SPARSEMEM_ENABLE
1657 config ARCH_SELECT_MEMORY_MODEL
1658 def_bool ARCH_SPARSEMEM_ENABLE
1660 config HAVE_ARCH_PFN_VALID
1661 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1664 bool "High Memory Support"
1667 The address space of ARM processors is only 4 Gigabytes large
1668 and it has to accommodate user address space, kernel address
1669 space as well as some memory mapped IO. That means that, if you
1670 have a large amount of physical memory and/or IO, not all of the
1671 memory can be "permanently mapped" by the kernel. The physical
1672 memory that is not permanently mapped is called "high memory".
1674 Depending on the selected kernel/user memory split, minimum
1675 vmalloc space and actual amount of RAM, you may not need this
1676 option which should result in a slightly faster kernel.
1681 bool "Allocate 2nd-level pagetables from highmem"
1684 config HW_PERF_EVENTS
1685 bool "Enable hardware performance counter support for perf events"
1686 depends on PERF_EVENTS && CPU_HAS_PMU
1689 Enable hardware performance counter support for perf events. If
1690 disabled, perf events will use software events only.
1694 config FORCE_MAX_ZONEORDER
1695 int "Maximum zone order" if ARCH_SHMOBILE
1696 range 11 64 if ARCH_SHMOBILE
1697 default "9" if SA1111
1700 The kernel memory allocator divides physically contiguous memory
1701 blocks into "zones", where each zone is a power of two number of
1702 pages. This option selects the largest power of two that the kernel
1703 keeps in the memory allocator. If you need to allocate very large
1704 blocks of physically contiguous memory, then you may need to
1705 increase this value.
1707 This config option is actually maximum order plus one. For example,
1708 a value of 11 means that the largest free memory block is 2^10 pages.
1711 bool "Timer and CPU usage LEDs"
1712 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1713 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1714 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1715 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1716 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1717 ARCH_AT91 || ARCH_DAVINCI || \
1718 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1720 If you say Y here, the LEDs on your machine will be used
1721 to provide useful information about your current system status.
1723 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1724 be able to select which LEDs are active using the options below. If
1725 you are compiling a kernel for the EBSA-110 or the LART however, the
1726 red LED will simply flash regularly to indicate that the system is
1727 still functional. It is safe to say Y here if you have a CATS
1728 system, but the driver will do nothing.
1731 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1732 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1733 || MACH_OMAP_PERSEUS2
1735 depends on !GENERIC_CLOCKEVENTS
1736 default y if ARCH_EBSA110
1738 If you say Y here, one of the system LEDs (the green one on the
1739 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1740 will flash regularly to indicate that the system is still
1741 operational. This is mainly useful to kernel hackers who are
1742 debugging unstable kernels.
1744 The LART uses the same LED for both Timer LED and CPU usage LED
1745 functions. You may choose to use both, but the Timer LED function
1746 will overrule the CPU usage LED.
1749 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1751 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1752 || MACH_OMAP_PERSEUS2
1755 If you say Y here, the red LED will be used to give a good real
1756 time indication of CPU usage, by lighting whenever the idle task
1757 is not currently executing.
1759 The LART uses the same LED for both Timer LED and CPU usage LED
1760 functions. You may choose to use both, but the Timer LED function
1761 will overrule the CPU usage LED.
1763 config ALIGNMENT_TRAP
1765 depends on CPU_CP15_MMU
1766 default y if !ARCH_EBSA110
1767 select HAVE_PROC_CPU if PROC_FS
1769 ARM processors cannot fetch/store information which is not
1770 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1771 address divisible by 4. On 32-bit ARM processors, these non-aligned
1772 fetch/store instructions will be emulated in software if you say
1773 here, which has a severe performance impact. This is necessary for
1774 correct operation of some network protocols. With an IP-only
1775 configuration it is safe to say N, otherwise say Y.
1777 config UACCESS_WITH_MEMCPY
1778 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1779 depends on MMU && EXPERIMENTAL
1780 default y if CPU_FEROCEON
1782 Implement faster copy_to_user and clear_user methods for CPU
1783 cores where a 8-word STM instruction give significantly higher
1784 memory write throughput than a sequence of individual 32bit stores.
1786 A possible side effect is a slight increase in scheduling latency
1787 between threads sharing the same address space if they invoke
1788 such copy operations with large buffers.
1790 However, if the CPU data cache is using a write-allocate mode,
1791 this option is unlikely to provide any performance gain.
1795 prompt "Enable seccomp to safely compute untrusted bytecode"
1797 This kernel feature is useful for number crunching applications
1798 that may need to compute untrusted bytecode during their
1799 execution. By using pipes or other transports made available to
1800 the process as file descriptors supporting the read/write
1801 syscalls, it's possible to isolate those applications in
1802 their own address space using seccomp. Once seccomp is
1803 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1804 and the task is only allowed to execute a few safe syscalls
1805 defined by each seccomp mode.
1807 config CC_STACKPROTECTOR
1808 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1809 depends on EXPERIMENTAL
1811 This option turns on the -fstack-protector GCC feature. This
1812 feature puts, at the beginning of functions, a canary value on
1813 the stack just before the return address, and validates
1814 the value just before actually returning. Stack based buffer
1815 overflows (that need to overwrite this return address) now also
1816 overwrite the canary, which gets detected and the attack is then
1817 neutralized via a kernel panic.
1818 This feature requires gcc version 4.2 or above.
1820 config DEPRECATED_PARAM_STRUCT
1821 bool "Provide old way to pass kernel parameters"
1823 This was deprecated in 2001 and announced to live on for 5 years.
1824 Some old boot loaders still use this way.
1831 bool "Flattened Device Tree support"
1833 select OF_EARLY_FLATTREE
1836 Include support for flattened device tree machine descriptions.
1838 # Compressed boot loader in ROM. Yes, we really want to ask about
1839 # TEXT and BSS so we preserve their values in the config files.
1840 config ZBOOT_ROM_TEXT
1841 hex "Compressed ROM boot loader base address"
1844 The physical address at which the ROM-able zImage is to be
1845 placed in the target. Platforms which normally make use of
1846 ROM-able zImage formats normally set this to a suitable
1847 value in their defconfig file.
1849 If ZBOOT_ROM is not enabled, this has no effect.
1851 config ZBOOT_ROM_BSS
1852 hex "Compressed ROM boot loader BSS address"
1855 The base address of an area of read/write memory in the target
1856 for the ROM-able zImage which must be available while the
1857 decompressor is running. It must be large enough to hold the
1858 entire decompressed kernel plus an additional 128 KiB.
1859 Platforms which normally make use of ROM-able zImage formats
1860 normally set this to a suitable value in their defconfig file.
1862 If ZBOOT_ROM is not enabled, this has no effect.
1865 bool "Compressed boot loader in ROM/flash"
1866 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1868 Say Y here if you intend to execute your compressed kernel image
1869 (zImage) directly from ROM or flash. If unsure, say N.
1872 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1873 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1874 default ZBOOT_ROM_NONE
1876 Include experimental SD/MMC loading code in the ROM-able zImage.
1877 With this enabled it is possible to write the the ROM-able zImage
1878 kernel image to an MMC or SD card and boot the kernel straight
1879 from the reset vector. At reset the processor Mask ROM will load
1880 the first part of the the ROM-able zImage which in turn loads the
1881 rest the kernel image to RAM.
1883 config ZBOOT_ROM_NONE
1884 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1886 Do not load image from SD or MMC
1888 config ZBOOT_ROM_MMCIF
1889 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1891 Load image from MMCIF hardware block.
1893 config ZBOOT_ROM_SH_MOBILE_SDHI
1894 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1896 Load image from SDHI hardware block
1900 config ARM_APPENDED_DTB
1901 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1902 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1904 With this option, the boot code will look for a device tree binary
1905 (DTB) appended to zImage
1906 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1908 This is meant as a backward compatibility convenience for those
1909 systems with a bootloader that can't be upgraded to accommodate
1910 the documented boot protocol using a device tree.
1912 Beware that there is very little in terms of protection against
1913 this option being confused by leftover garbage in memory that might
1914 look like a DTB header after a reboot if no actual DTB is appended
1915 to zImage. Do not leave this option active in a production kernel
1916 if you don't intend to always append a DTB. Proper passing of the
1917 location into r2 of a bootloader provided DTB is always preferable
1920 config ARM_ATAG_DTB_COMPAT
1921 bool "Supplement the appended DTB with traditional ATAG information"
1922 depends on ARM_APPENDED_DTB
1924 Some old bootloaders can't be updated to a DTB capable one, yet
1925 they provide ATAGs with memory configuration, the ramdisk address,
1926 the kernel cmdline string, etc. Such information is dynamically
1927 provided by the bootloader and can't always be stored in a static
1928 DTB. To allow a device tree enabled kernel to be used with such
1929 bootloaders, this option allows zImage to extract the information
1930 from the ATAG list and store it at run time into the appended DTB.
1933 string "Default kernel command string"
1936 On some architectures (EBSA110 and CATS), there is currently no way
1937 for the boot loader to pass arguments to the kernel. For these
1938 architectures, you should supply some command-line options at build
1939 time by entering them here. As a minimum, you should specify the
1940 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1943 prompt "Kernel command line type" if CMDLINE != ""
1944 default CMDLINE_FROM_BOOTLOADER
1946 config CMDLINE_FROM_BOOTLOADER
1947 bool "Use bootloader kernel arguments if available"
1949 Uses the command-line options passed by the boot loader. If
1950 the boot loader doesn't provide any, the default kernel command
1951 string provided in CMDLINE will be used.
1953 config CMDLINE_EXTEND
1954 bool "Extend bootloader kernel arguments"
1956 The command-line arguments provided by the boot loader will be
1957 appended to the default kernel command string.
1959 config CMDLINE_FORCE
1960 bool "Always use the default kernel command string"
1962 Always use the default kernel command string, even if the boot
1963 loader passes other arguments to the kernel.
1964 This is useful if you cannot or don't want to change the
1965 command-line options your boot loader passes to the kernel.
1969 bool "Kernel Execute-In-Place from ROM"
1970 depends on !ZBOOT_ROM
1972 Execute-In-Place allows the kernel to run from non-volatile storage
1973 directly addressable by the CPU, such as NOR flash. This saves RAM
1974 space since the text section of the kernel is not loaded from flash
1975 to RAM. Read-write sections, such as the data section and stack,
1976 are still copied to RAM. The XIP kernel is not compressed since
1977 it has to run directly from flash, so it will take more space to
1978 store it. The flash address used to link the kernel object files,
1979 and for storing it, is configuration dependent. Therefore, if you
1980 say Y here, you must know the proper physical address where to
1981 store the kernel image depending on your own flash memory usage.
1983 Also note that the make target becomes "make xipImage" rather than
1984 "make zImage" or "make Image". The final kernel binary to put in
1985 ROM memory will be arch/arm/boot/xipImage.
1989 config XIP_PHYS_ADDR
1990 hex "XIP Kernel Physical Location"
1991 depends on XIP_KERNEL
1992 default "0x00080000"
1994 This is the physical address in your flash memory the kernel will
1995 be linked for and stored to. This address is dependent on your
1999 bool "Kexec system call (EXPERIMENTAL)"
2000 depends on EXPERIMENTAL
2002 kexec is a system call that implements the ability to shutdown your
2003 current kernel, and to start another kernel. It is like a reboot
2004 but it is independent of the system firmware. And like a reboot
2005 you can start any kernel with it, not just Linux.
2007 It is an ongoing process to be certain the hardware in a machine
2008 is properly shutdown, so do not be surprised if this code does not
2009 initially work for you. It may help to enable device hotplugging
2013 bool "Export atags in procfs"
2017 Should the atags used to boot the kernel be exported in an "atags"
2018 file in procfs. Useful with kexec.
2021 bool "Build kdump crash kernel (EXPERIMENTAL)"
2022 depends on EXPERIMENTAL
2024 Generate crash dump after being started by kexec. This should
2025 be normally only set in special crash dump kernels which are
2026 loaded in the main kernel with kexec-tools into a specially
2027 reserved region and then later executed after a crash by
2028 kdump/kexec. The crash dump kernel must be compiled to a
2029 memory address not used by the main kernel
2031 For more details see Documentation/kdump/kdump.txt
2033 config AUTO_ZRELADDR
2034 bool "Auto calculation of the decompressed kernel image address"
2035 depends on !ZBOOT_ROM && !ARCH_U300
2037 ZRELADDR is the physical address where the decompressed kernel
2038 image will be placed. If AUTO_ZRELADDR is selected, the address
2039 will be determined at run-time by masking the current IP with
2040 0xf8000000. This assumes the zImage being placed in the first 128MB
2041 from start of memory.
2045 menu "CPU Power Management"
2049 source "drivers/cpufreq/Kconfig"
2052 tristate "CPUfreq driver for i.MX CPUs"
2053 depends on ARCH_MXC && CPU_FREQ
2055 This enables the CPUfreq driver for i.MX CPUs.
2057 config CPU_FREQ_SA1100
2060 config CPU_FREQ_SA1110
2063 config CPU_FREQ_INTEGRATOR
2064 tristate "CPUfreq driver for ARM Integrator CPUs"
2065 depends on ARCH_INTEGRATOR && CPU_FREQ
2068 This enables the CPUfreq driver for ARM Integrator CPUs.
2070 For details, take a look at <file:Documentation/cpu-freq>.
2076 depends on CPU_FREQ && ARCH_PXA && PXA25x
2078 select CPU_FREQ_TABLE
2079 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2084 Internal configuration node for common cpufreq on Samsung SoC
2086 config CPU_FREQ_S3C24XX
2087 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2088 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2091 This enables the CPUfreq driver for the Samsung S3C24XX family
2094 For details, take a look at <file:Documentation/cpu-freq>.
2098 config CPU_FREQ_S3C24XX_PLL
2099 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2100 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2102 Compile in support for changing the PLL frequency from the
2103 S3C24XX series CPUfreq driver. The PLL takes time to settle
2104 after a frequency change, so by default it is not enabled.
2106 This also means that the PLL tables for the selected CPU(s) will
2107 be built which may increase the size of the kernel image.
2109 config CPU_FREQ_S3C24XX_DEBUG
2110 bool "Debug CPUfreq Samsung driver core"
2111 depends on CPU_FREQ_S3C24XX
2113 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2115 config CPU_FREQ_S3C24XX_IODEBUG
2116 bool "Debug CPUfreq Samsung driver IO timing"
2117 depends on CPU_FREQ_S3C24XX
2119 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2121 config CPU_FREQ_S3C24XX_DEBUGFS
2122 bool "Export debugfs for CPUFreq"
2123 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2125 Export status information via debugfs.
2129 source "drivers/cpuidle/Kconfig"
2133 menu "Floating point emulation"
2135 comment "At least one emulation must be selected"
2138 bool "NWFPE math emulation"
2139 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2141 Say Y to include the NWFPE floating point emulator in the kernel.
2142 This is necessary to run most binaries. Linux does not currently
2143 support floating point hardware so you need to say Y here even if
2144 your machine has an FPA or floating point co-processor podule.
2146 You may say N here if you are going to load the Acorn FPEmulator
2147 early in the bootup.
2150 bool "Support extended precision"
2151 depends on FPE_NWFPE
2153 Say Y to include 80-bit support in the kernel floating-point
2154 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2155 Note that gcc does not generate 80-bit operations by default,
2156 so in most cases this option only enlarges the size of the
2157 floating point emulator without any good reason.
2159 You almost surely want to say N here.
2162 bool "FastFPE math emulation (EXPERIMENTAL)"
2163 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2165 Say Y here to include the FAST floating point emulator in the kernel.
2166 This is an experimental much faster emulator which now also has full
2167 precision for the mantissa. It does not support any exceptions.
2168 It is very simple, and approximately 3-6 times faster than NWFPE.
2170 It should be sufficient for most programs. It may be not suitable
2171 for scientific calculations, but you have to check this for yourself.
2172 If you do not feel you need a faster FP emulation you should better
2176 bool "VFP-format floating point maths"
2177 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2179 Say Y to include VFP support code in the kernel. This is needed
2180 if your hardware includes a VFP unit.
2182 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2183 release notes and additional status information.
2185 Say N if your target does not have VFP hardware.
2193 bool "Advanced SIMD (NEON) Extension support"
2194 depends on VFPv3 && CPU_V7
2196 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2201 menu "Userspace binary formats"
2203 source "fs/Kconfig.binfmt"
2206 tristate "RISC OS personality"
2209 Say Y here to include the kernel code necessary if you want to run
2210 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2211 experimental; if this sounds frightening, say N and sleep in peace.
2212 You can also say M here to compile this support as a module (which
2213 will be called arthur).
2217 menu "Power management options"
2219 source "kernel/power/Kconfig"
2221 config ARCH_SUSPEND_POSSIBLE
2222 depends on !ARCH_S5PC100
2223 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2224 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2227 config ARM_CPU_SUSPEND
2232 source "net/Kconfig"
2234 source "drivers/Kconfig"
2238 source "arch/arm/Kconfig.debug"
2240 source "security/Kconfig"
2242 source "crypto/Kconfig"
2244 source "lib/Kconfig"