5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
41 config ARM_HAS_SG_CHAIN
50 config SYS_SUPPORTS_APM_EMULATION
53 config HAVE_SCHED_CLOCK
59 config ARCH_USES_GETTIMEOFFSET
63 config GENERIC_CLOCKEVENTS
66 config GENERIC_CLOCKEVENTS_BROADCAST
68 depends on GENERIC_CLOCKEVENTS
77 select GENERIC_ALLOCATOR
88 The Extended Industry Standard Architecture (EISA) bus was
89 developed as an open alternative to the IBM MicroChannel bus.
91 The EISA bus provided some of the features of the IBM MicroChannel
92 bus while maintaining backward compatibility with cards made for
93 the older ISA bus. The EISA bus saw limited use between 1988 and
94 1995 when it was made obsolete by the PCI bus.
96 Say Y here if you are building a kernel for an EISA-based machine.
106 MicroChannel Architecture is found in some IBM PS/2 machines and
107 laptops. It is a bus system similar to PCI or ISA. See
108 <file:Documentation/mca.txt> (and especially the web page given
109 there) before attempting to build an MCA bus kernel.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config HARDIRQS_SW_RESEND
132 config GENERIC_IRQ_PROBE
136 config GENERIC_LOCKBREAK
139 depends on SMP && PREEMPT
141 config RWSEM_GENERIC_SPINLOCK
145 config RWSEM_XCHGADD_ALGORITHM
148 config ARCH_HAS_ILOG2_U32
151 config ARCH_HAS_ILOG2_U64
154 config ARCH_HAS_CPUFREQ
157 Internal node to signify that the ARCH has CPUFREQ support
158 and that the relevant menu configurations are displayed for
161 config ARCH_HAS_CPU_IDLE_WAIT
164 config GENERIC_HWEIGHT
168 config GENERIC_CALIBRATE_DELAY
172 config ARCH_MAY_HAVE_PC_FDC
178 config NEED_DMA_MAP_STATE
181 config GENERIC_ISA_DMA
192 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
193 default DRAM_BASE if REMAP_VECTORS_TO_RAM
196 The base address of exception vectors.
198 config ARM_PATCH_PHYS_VIRT
199 bool "Patch physical to virtual translations at runtime" if EMBEDDED
201 depends on !XIP_KERNEL && MMU
202 depends on !ARCH_REALVIEW || !SPARSEMEM
204 Patch phys-to-virt and virt-to-phys translation functions at
205 boot and module load time according to the position of the
206 kernel in system memory.
208 This can only be used with non-XIP MMU kernels where the base
209 of physical memory is at a 16MB boundary.
211 Only disable this option if you know that you do not require
212 this feature (eg, building a kernel for a single machine) and
213 you need to shrink the kernel to the minimal size.
215 config NEED_MACH_MEMORY_H
218 Select this when mach/memory.h is required to provide special
219 definitions for this platform. The need for mach/memory.h should
220 be avoided when possible.
223 hex "Physical address of main memory"
224 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
226 Please provide the physical address corresponding to the
227 location of main memory in your system.
229 source "init/Kconfig"
231 source "kernel/Kconfig.freezer"
236 bool "MMU-based Paged Memory Management Support"
239 Select if you want MMU-based virtualised addressing space
240 support by paged memory management. If unsure, say 'Y'.
243 # The "ARM system type" choice list is ordered alphabetically by option
244 # text. Please add new entries in the option alphabetic order.
247 prompt "ARM system type"
248 default ARCH_VERSATILE
250 config ARCH_INTEGRATOR
251 bool "ARM Ltd. Integrator family"
253 select ARCH_HAS_CPUFREQ
255 select HAVE_MACH_CLKDEV
257 select GENERIC_CLOCKEVENTS
258 select PLAT_VERSATILE
259 select PLAT_VERSATILE_FPGA_IRQ
260 select NEED_MACH_MEMORY_H
262 Support for ARM's Integrator platform.
265 bool "ARM Ltd. RealView family"
268 select HAVE_MACH_CLKDEV
270 select GENERIC_CLOCKEVENTS
271 select ARCH_WANT_OPTIONAL_GPIOLIB
272 select PLAT_VERSATILE
273 select PLAT_VERSATILE_CLCD
274 select ARM_TIMER_SP804
275 select GPIO_PL061 if GPIOLIB
276 select NEED_MACH_MEMORY_H
278 This enables support for ARM Ltd RealView boards.
280 config ARCH_VERSATILE
281 bool "ARM Ltd. Versatile family"
285 select HAVE_MACH_CLKDEV
287 select GENERIC_CLOCKEVENTS
288 select ARCH_WANT_OPTIONAL_GPIOLIB
289 select PLAT_VERSATILE
290 select PLAT_VERSATILE_CLCD
291 select PLAT_VERSATILE_FPGA_IRQ
292 select ARM_TIMER_SP804
294 This enables support for ARM Ltd Versatile board.
297 bool "ARM Ltd. Versatile Express family"
298 select ARCH_WANT_OPTIONAL_GPIOLIB
300 select ARM_TIMER_SP804
302 select HAVE_MACH_CLKDEV
303 select GENERIC_CLOCKEVENTS
305 select HAVE_PATA_PLATFORM
307 select PLAT_VERSATILE
308 select PLAT_VERSATILE_CLCD
310 This enables support for the ARM Ltd Versatile Express boards.
314 select ARCH_REQUIRE_GPIOLIB
318 This enables support for systems based on the Atmel AT91RM9200,
319 AT91SAM9 and AT91CAP9 processors.
322 bool "Broadcom BCMRING"
326 select ARM_TIMER_SP804
328 select GENERIC_CLOCKEVENTS
329 select ARCH_WANT_OPTIONAL_GPIOLIB
331 Support for Broadcom's BCMRing platform.
334 bool "Cirrus Logic CLPS711x/EP721x-based"
336 select ARCH_USES_GETTIMEOFFSET
337 select NEED_MACH_MEMORY_H
339 Support for Cirrus Logic 711x/721x based boards.
342 bool "Cavium Networks CNS3XXX family"
344 select GENERIC_CLOCKEVENTS
346 select MIGHT_HAVE_PCI
347 select PCI_DOMAINS if PCI
349 Support for Cavium Networks CNS3XXX platform.
352 bool "Cortina Systems Gemini"
354 select ARCH_REQUIRE_GPIOLIB
355 select ARCH_USES_GETTIMEOFFSET
357 Support for the Cortina Systems Gemini family SoCs
360 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
364 select GENERIC_CLOCKEVENTS
366 select GENERIC_IRQ_CHIP
370 Support for CSR SiRFSoC ARM Cortex A9 Platform
377 select ARCH_USES_GETTIMEOFFSET
378 select NEED_MACH_MEMORY_H
380 This is an evaluation board for the StrongARM processor available
381 from Digital. It has limited hardware on-board, including an
382 Ethernet interface, two PCMCIA sockets, two serial ports and a
391 select ARCH_REQUIRE_GPIOLIB
392 select ARCH_HAS_HOLES_MEMORYMODEL
393 select ARCH_USES_GETTIMEOFFSET
396 This enables support for the Cirrus EP93xx series of CPUs.
398 config ARCH_FOOTBRIDGE
402 select GENERIC_CLOCKEVENTS
403 select NEED_MACH_MEMORY_H
405 Support for systems based on the DC21285 companion chip
406 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
409 bool "Freescale MXC/iMX-based"
410 select GENERIC_CLOCKEVENTS
411 select ARCH_REQUIRE_GPIOLIB
414 select GENERIC_IRQ_CHIP
415 select HAVE_SCHED_CLOCK
416 select MULTI_IRQ_HANDLER
418 Support for Freescale MXC/iMX-based family of processors
421 bool "Freescale MXS-based"
422 select GENERIC_CLOCKEVENTS
423 select ARCH_REQUIRE_GPIOLIB
427 Support for Freescale MXS-based family of processors
430 bool "Hilscher NetX based"
434 select GENERIC_CLOCKEVENTS
436 This enables support for systems based on the Hilscher NetX Soc
439 bool "Hynix HMS720x-based"
442 select ARCH_USES_GETTIMEOFFSET
444 This enables support for systems based on the Hynix HMS720x
452 select ARCH_SUPPORTS_MSI
454 select NEED_MACH_MEMORY_H
456 Support for Intel's IOP13XX (XScale) family of processors.
464 select ARCH_REQUIRE_GPIOLIB
466 Support for Intel's 80219 and IOP32X (XScale) family of
475 select ARCH_REQUIRE_GPIOLIB
477 Support for Intel's IOP33X (XScale) family of processors.
484 select ARCH_USES_GETTIMEOFFSET
485 select NEED_MACH_MEMORY_H
487 Support for Intel's IXP23xx (XScale) family of processors.
490 bool "IXP2400/2800-based"
494 select ARCH_USES_GETTIMEOFFSET
495 select NEED_MACH_MEMORY_H
497 Support for Intel's IXP2400/2800 (XScale) family of processors.
505 select GENERIC_CLOCKEVENTS
506 select HAVE_SCHED_CLOCK
507 select MIGHT_HAVE_PCI
508 select DMABOUNCE if PCI
510 Support for Intel's IXP4XX (XScale) family of processors.
516 select ARCH_REQUIRE_GPIOLIB
517 select GENERIC_CLOCKEVENTS
520 Support for the Marvell Dove SoC 88AP510
523 bool "Marvell Kirkwood"
526 select ARCH_REQUIRE_GPIOLIB
527 select GENERIC_CLOCKEVENTS
530 Support for the following Marvell Kirkwood series SoCs:
531 88F6180, 88F6192 and 88F6281.
537 select ARCH_REQUIRE_GPIOLIB
540 select USB_ARCH_HAS_OHCI
543 select GENERIC_CLOCKEVENTS
545 Support for the NXP LPC32XX family of processors
548 bool "Marvell MV78xx0"
551 select ARCH_REQUIRE_GPIOLIB
552 select GENERIC_CLOCKEVENTS
555 Support for the following Marvell MV78xx0 series SoCs:
563 select ARCH_REQUIRE_GPIOLIB
564 select GENERIC_CLOCKEVENTS
567 Support for the following Marvell Orion 5x series SoCs:
568 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
569 Orion-2 (5281), Orion-1-90 (6183).
572 bool "Marvell PXA168/910/MMP2"
574 select ARCH_REQUIRE_GPIOLIB
576 select GENERIC_CLOCKEVENTS
577 select HAVE_SCHED_CLOCK
582 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
585 bool "Micrel/Kendin KS8695"
587 select ARCH_REQUIRE_GPIOLIB
588 select ARCH_USES_GETTIMEOFFSET
589 select NEED_MACH_MEMORY_H
591 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
592 System-on-Chip devices.
595 bool "Nuvoton W90X900 CPU"
597 select ARCH_REQUIRE_GPIOLIB
600 select GENERIC_CLOCKEVENTS
602 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
603 At present, the w90x900 has been renamed nuc900, regarding
604 the ARM series product line, you can login the following
605 link address to know more.
607 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
608 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
611 bool "Nuvoton NUC93X CPU"
615 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
616 low-power and high performance MPEG-4/JPEG multimedia controller chip.
623 select GENERIC_CLOCKEVENTS
626 select HAVE_SCHED_CLOCK
627 select ARCH_HAS_CPUFREQ
629 This enables support for NVIDIA Tegra based systems (Tegra APX,
630 Tegra 6xx and Tegra 2 series).
633 bool "Philips Nexperia PNX4008 Mobile"
636 select ARCH_USES_GETTIMEOFFSET
638 This enables support for Philips PNX4008 mobile platform.
641 bool "PXA2xx/PXA3xx-based"
644 select ARCH_HAS_CPUFREQ
647 select ARCH_REQUIRE_GPIOLIB
648 select GENERIC_CLOCKEVENTS
649 select HAVE_SCHED_CLOCK
654 select MULTI_IRQ_HANDLER
656 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
661 select GENERIC_CLOCKEVENTS
662 select ARCH_REQUIRE_GPIOLIB
665 Support for Qualcomm MSM/QSD based systems. This runs on the
666 apps processor of the MSM/QSD and depends on a shared memory
667 interface to the modem processor which runs the baseband
668 stack and controls some vital subsystems
669 (clock and power control, etc).
672 bool "Renesas SH-Mobile / R-Mobile"
675 select HAVE_MACH_CLKDEV
676 select GENERIC_CLOCKEVENTS
679 select MULTI_IRQ_HANDLER
680 select PM_GENERIC_DOMAINS if PM
681 select NEED_MACH_MEMORY_H
683 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
690 select ARCH_MAY_HAVE_PC_FDC
691 select HAVE_PATA_PLATFORM
694 select ARCH_SPARSEMEM_ENABLE
695 select ARCH_USES_GETTIMEOFFSET
696 select NEED_MACH_MEMORY_H
698 On the Acorn Risc-PC, Linux can support the internal IDE disk and
699 CD-ROM interface, serial and parallel port, and the floppy drive.
706 select ARCH_SPARSEMEM_ENABLE
708 select ARCH_HAS_CPUFREQ
710 select GENERIC_CLOCKEVENTS
712 select HAVE_SCHED_CLOCK
714 select ARCH_REQUIRE_GPIOLIB
715 select NEED_MACH_MEMORY_H
717 Support for StrongARM 11x0 based boards.
720 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
722 select ARCH_HAS_CPUFREQ
725 select ARCH_USES_GETTIMEOFFSET
726 select HAVE_S3C2410_I2C if I2C
728 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
729 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
730 the Samsung SMDK2410 development board (and derivatives).
732 Note, the S3C2416 and the S3C2450 are so close that they even share
733 the same SoC ID code. This means that there is no separate machine
734 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
737 bool "Samsung S3C64XX"
744 select ARCH_USES_GETTIMEOFFSET
745 select ARCH_HAS_CPUFREQ
746 select ARCH_REQUIRE_GPIOLIB
747 select SAMSUNG_CLKSRC
748 select SAMSUNG_IRQ_VIC_TIMER
749 select SAMSUNG_IRQ_UART
750 select S3C_GPIO_TRACK
751 select S3C_GPIO_PULL_UPDOWN
752 select S3C_GPIO_CFG_S3C24XX
753 select S3C_GPIO_CFG_S3C64XX
755 select USB_ARCH_HAS_OHCI
756 select SAMSUNG_GPIOLIB_4BIT
757 select HAVE_S3C2410_I2C if I2C
758 select HAVE_S3C2410_WATCHDOG if WATCHDOG
760 Samsung S3C64XX series based systems
763 bool "Samsung S5P6440 S5P6450"
769 select HAVE_S3C2410_WATCHDOG if WATCHDOG
770 select GENERIC_CLOCKEVENTS
771 select HAVE_SCHED_CLOCK
772 select HAVE_S3C2410_I2C if I2C
773 select HAVE_S3C_RTC if RTC_CLASS
775 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
779 bool "Samsung S5PC100"
784 select ARM_L1_CACHE_SHIFT_6
785 select ARCH_USES_GETTIMEOFFSET
786 select HAVE_S3C2410_I2C if I2C
787 select HAVE_S3C_RTC if RTC_CLASS
788 select HAVE_S3C2410_WATCHDOG if WATCHDOG
790 Samsung S5PC100 series based systems
793 bool "Samsung S5PV210/S5PC110"
795 select ARCH_SPARSEMEM_ENABLE
796 select ARCH_HAS_HOLES_MEMORYMODEL
801 select ARM_L1_CACHE_SHIFT_6
802 select ARCH_HAS_CPUFREQ
803 select GENERIC_CLOCKEVENTS
804 select HAVE_SCHED_CLOCK
805 select HAVE_S3C2410_I2C if I2C
806 select HAVE_S3C_RTC if RTC_CLASS
807 select HAVE_S3C2410_WATCHDOG if WATCHDOG
808 select NEED_MACH_MEMORY_H
810 Samsung S5PV210/S5PC110 series based systems
813 bool "Samsung EXYNOS4"
815 select ARCH_SPARSEMEM_ENABLE
816 select ARCH_HAS_HOLES_MEMORYMODEL
820 select ARCH_HAS_CPUFREQ
821 select GENERIC_CLOCKEVENTS
822 select HAVE_S3C_RTC if RTC_CLASS
823 select HAVE_S3C2410_I2C if I2C
824 select HAVE_S3C2410_WATCHDOG if WATCHDOG
825 select NEED_MACH_MEMORY_H
827 Samsung EXYNOS4 series based systems
836 select ARCH_USES_GETTIMEOFFSET
837 select NEED_MACH_MEMORY_H
839 Support for the StrongARM based Digital DNARD machine, also known
840 as "Shark" (<http://www.shark-linux.de/shark.html>).
843 bool "Telechips TCC ARM926-based systems"
848 select GENERIC_CLOCKEVENTS
850 Support for Telechips TCC ARM926-based systems.
853 bool "ST-Ericsson U300 Series"
857 select HAVE_SCHED_CLOCK
861 select GENERIC_CLOCKEVENTS
863 select HAVE_MACH_CLKDEV
865 select NEED_MACH_MEMORY_H
867 Support for ST-Ericsson U300 series mobile platforms.
870 bool "ST-Ericsson U8500 Series"
873 select GENERIC_CLOCKEVENTS
875 select ARCH_REQUIRE_GPIOLIB
876 select ARCH_HAS_CPUFREQ
878 Support for ST-Ericsson's Ux500 architecture
881 bool "STMicroelectronics Nomadik"
886 select GENERIC_CLOCKEVENTS
887 select ARCH_REQUIRE_GPIOLIB
889 Support for the Nomadik platform by ST-Ericsson
893 select GENERIC_CLOCKEVENTS
894 select ARCH_REQUIRE_GPIOLIB
898 select GENERIC_ALLOCATOR
899 select GENERIC_IRQ_CHIP
900 select ARCH_HAS_HOLES_MEMORYMODEL
902 Support for TI's DaVinci platform.
907 select ARCH_REQUIRE_GPIOLIB
908 select ARCH_HAS_CPUFREQ
910 select GENERIC_CLOCKEVENTS
911 select HAVE_SCHED_CLOCK
912 select ARCH_HAS_HOLES_MEMORYMODEL
914 Support for TI's OMAP platform (OMAP1/2/3/4).
919 select ARCH_REQUIRE_GPIOLIB
922 select GENERIC_CLOCKEVENTS
925 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
928 bool "VIA/WonderMedia 85xx"
931 select ARCH_HAS_CPUFREQ
932 select GENERIC_CLOCKEVENTS
933 select ARCH_REQUIRE_GPIOLIB
936 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
939 bool "Xilinx Zynq ARM Cortex A9 Platform"
942 select GENERIC_CLOCKEVENTS
949 Support for Xilinx Zynq ARM Cortex A9 Platform
953 # This is sorted alphabetically by mach-* pathname. However, plat-*
954 # Kconfigs may be included either alphabetically (according to the
955 # plat- suffix) or along side the corresponding mach-* source.
957 source "arch/arm/mach-at91/Kconfig"
959 source "arch/arm/mach-bcmring/Kconfig"
961 source "arch/arm/mach-clps711x/Kconfig"
963 source "arch/arm/mach-cns3xxx/Kconfig"
965 source "arch/arm/mach-davinci/Kconfig"
967 source "arch/arm/mach-dove/Kconfig"
969 source "arch/arm/mach-ep93xx/Kconfig"
971 source "arch/arm/mach-footbridge/Kconfig"
973 source "arch/arm/mach-gemini/Kconfig"
975 source "arch/arm/mach-h720x/Kconfig"
977 source "arch/arm/mach-integrator/Kconfig"
979 source "arch/arm/mach-iop32x/Kconfig"
981 source "arch/arm/mach-iop33x/Kconfig"
983 source "arch/arm/mach-iop13xx/Kconfig"
985 source "arch/arm/mach-ixp4xx/Kconfig"
987 source "arch/arm/mach-ixp2000/Kconfig"
989 source "arch/arm/mach-ixp23xx/Kconfig"
991 source "arch/arm/mach-kirkwood/Kconfig"
993 source "arch/arm/mach-ks8695/Kconfig"
995 source "arch/arm/mach-lpc32xx/Kconfig"
997 source "arch/arm/mach-msm/Kconfig"
999 source "arch/arm/mach-mv78xx0/Kconfig"
1001 source "arch/arm/plat-mxc/Kconfig"
1003 source "arch/arm/mach-mxs/Kconfig"
1005 source "arch/arm/mach-netx/Kconfig"
1007 source "arch/arm/mach-nomadik/Kconfig"
1008 source "arch/arm/plat-nomadik/Kconfig"
1010 source "arch/arm/mach-nuc93x/Kconfig"
1012 source "arch/arm/plat-omap/Kconfig"
1014 source "arch/arm/mach-omap1/Kconfig"
1016 source "arch/arm/mach-omap2/Kconfig"
1018 source "arch/arm/mach-orion5x/Kconfig"
1020 source "arch/arm/mach-pxa/Kconfig"
1021 source "arch/arm/plat-pxa/Kconfig"
1023 source "arch/arm/mach-mmp/Kconfig"
1025 source "arch/arm/mach-realview/Kconfig"
1027 source "arch/arm/mach-sa1100/Kconfig"
1029 source "arch/arm/plat-samsung/Kconfig"
1030 source "arch/arm/plat-s3c24xx/Kconfig"
1031 source "arch/arm/plat-s5p/Kconfig"
1033 source "arch/arm/plat-spear/Kconfig"
1035 source "arch/arm/plat-tcc/Kconfig"
1038 source "arch/arm/mach-s3c2410/Kconfig"
1039 source "arch/arm/mach-s3c2412/Kconfig"
1040 source "arch/arm/mach-s3c2416/Kconfig"
1041 source "arch/arm/mach-s3c2440/Kconfig"
1042 source "arch/arm/mach-s3c2443/Kconfig"
1046 source "arch/arm/mach-s3c64xx/Kconfig"
1049 source "arch/arm/mach-s5p64x0/Kconfig"
1051 source "arch/arm/mach-s5pc100/Kconfig"
1053 source "arch/arm/mach-s5pv210/Kconfig"
1055 source "arch/arm/mach-exynos4/Kconfig"
1057 source "arch/arm/mach-shmobile/Kconfig"
1059 source "arch/arm/mach-tegra/Kconfig"
1061 source "arch/arm/mach-u300/Kconfig"
1063 source "arch/arm/mach-ux500/Kconfig"
1065 source "arch/arm/mach-versatile/Kconfig"
1067 source "arch/arm/mach-vexpress/Kconfig"
1068 source "arch/arm/plat-versatile/Kconfig"
1070 source "arch/arm/mach-vt8500/Kconfig"
1072 source "arch/arm/mach-w90x900/Kconfig"
1074 # Definitions to make life easier
1080 select GENERIC_CLOCKEVENTS
1081 select HAVE_SCHED_CLOCK
1086 select GENERIC_IRQ_CHIP
1087 select HAVE_SCHED_CLOCK
1092 config PLAT_VERSATILE
1095 config ARM_TIMER_SP804
1099 source arch/arm/mm/Kconfig
1102 bool "Enable iWMMXt support"
1103 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1104 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1106 Enable support for iWMMXt context switching at run time if
1107 running on a CPU that supports it.
1109 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1112 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1116 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1117 (!ARCH_OMAP3 || OMAP3_EMU)
1121 config MULTI_IRQ_HANDLER
1124 Allow each machine to specify it's own IRQ handler at run time.
1127 source "arch/arm/Kconfig-nommu"
1130 config ARM_ERRATA_411920
1131 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1132 depends on CPU_V6 || CPU_V6K
1134 Invalidation of the Instruction Cache operation can
1135 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1136 It does not affect the MPCore. This option enables the ARM Ltd.
1137 recommended workaround.
1139 config ARM_ERRATA_430973
1140 bool "ARM errata: Stale prediction on replaced interworking branch"
1143 This option enables the workaround for the 430973 Cortex-A8
1144 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1145 interworking branch is replaced with another code sequence at the
1146 same virtual address, whether due to self-modifying code or virtual
1147 to physical address re-mapping, Cortex-A8 does not recover from the
1148 stale interworking branch prediction. This results in Cortex-A8
1149 executing the new code sequence in the incorrect ARM or Thumb state.
1150 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1151 and also flushes the branch target cache at every context switch.
1152 Note that setting specific bits in the ACTLR register may not be
1153 available in non-secure mode.
1155 config ARM_ERRATA_458693
1156 bool "ARM errata: Processor deadlock when a false hazard is created"
1159 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1160 erratum. For very specific sequences of memory operations, it is
1161 possible for a hazard condition intended for a cache line to instead
1162 be incorrectly associated with a different cache line. This false
1163 hazard might then cause a processor deadlock. The workaround enables
1164 the L1 caching of the NEON accesses and disables the PLD instruction
1165 in the ACTLR register. Note that setting specific bits in the ACTLR
1166 register may not be available in non-secure mode.
1168 config ARM_ERRATA_460075
1169 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1172 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1173 erratum. Any asynchronous access to the L2 cache may encounter a
1174 situation in which recent store transactions to the L2 cache are lost
1175 and overwritten with stale memory contents from external memory. The
1176 workaround disables the write-allocate mode for the L2 cache via the
1177 ACTLR register. Note that setting specific bits in the ACTLR register
1178 may not be available in non-secure mode.
1180 config ARM_ERRATA_742230
1181 bool "ARM errata: DMB operation may be faulty"
1182 depends on CPU_V7 && SMP
1184 This option enables the workaround for the 742230 Cortex-A9
1185 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1186 between two write operations may not ensure the correct visibility
1187 ordering of the two writes. This workaround sets a specific bit in
1188 the diagnostic register of the Cortex-A9 which causes the DMB
1189 instruction to behave as a DSB, ensuring the correct behaviour of
1192 config ARM_ERRATA_742231
1193 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1194 depends on CPU_V7 && SMP
1196 This option enables the workaround for the 742231 Cortex-A9
1197 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1198 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1199 accessing some data located in the same cache line, may get corrupted
1200 data due to bad handling of the address hazard when the line gets
1201 replaced from one of the CPUs at the same time as another CPU is
1202 accessing it. This workaround sets specific bits in the diagnostic
1203 register of the Cortex-A9 which reduces the linefill issuing
1204 capabilities of the processor.
1206 config PL310_ERRATA_588369
1207 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1208 depends on CACHE_L2X0
1210 The PL310 L2 cache controller implements three types of Clean &
1211 Invalidate maintenance operations: by Physical Address
1212 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1213 They are architecturally defined to behave as the execution of a
1214 clean operation followed immediately by an invalidate operation,
1215 both performing to the same memory location. This functionality
1216 is not correctly implemented in PL310 as clean lines are not
1217 invalidated as a result of these operations.
1219 config ARM_ERRATA_720789
1220 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1221 depends on CPU_V7 && SMP
1223 This option enables the workaround for the 720789 Cortex-A9 (prior to
1224 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1225 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1226 As a consequence of this erratum, some TLB entries which should be
1227 invalidated are not, resulting in an incoherency in the system page
1228 tables. The workaround changes the TLB flushing routines to invalidate
1229 entries regardless of the ASID.
1231 config PL310_ERRATA_727915
1232 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1233 depends on CACHE_L2X0
1235 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1236 operation (offset 0x7FC). This operation runs in background so that
1237 PL310 can handle normal accesses while it is in progress. Under very
1238 rare circumstances, due to this erratum, write data can be lost when
1239 PL310 treats a cacheable write transaction during a Clean &
1240 Invalidate by Way operation.
1242 config ARM_ERRATA_743622
1243 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1246 This option enables the workaround for the 743622 Cortex-A9
1247 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1248 optimisation in the Cortex-A9 Store Buffer may lead to data
1249 corruption. This workaround sets a specific bit in the diagnostic
1250 register of the Cortex-A9 which disables the Store Buffer
1251 optimisation, preventing the defect from occurring. This has no
1252 visible impact on the overall performance or power consumption of the
1255 config ARM_ERRATA_751472
1256 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1257 depends on CPU_V7 && SMP
1259 This option enables the workaround for the 751472 Cortex-A9 (prior
1260 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1261 completion of a following broadcasted operation if the second
1262 operation is received by a CPU before the ICIALLUIS has completed,
1263 potentially leading to corrupted entries in the cache or TLB.
1265 config ARM_ERRATA_753970
1266 bool "ARM errata: cache sync operation may be faulty"
1267 depends on CACHE_PL310
1269 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1271 Under some condition the effect of cache sync operation on
1272 the store buffer still remains when the operation completes.
1273 This means that the store buffer is always asked to drain and
1274 this prevents it from merging any further writes. The workaround
1275 is to replace the normal offset of cache sync operation (0x730)
1276 by another offset targeting an unmapped PL310 register 0x740.
1277 This has the same effect as the cache sync operation: store buffer
1278 drain and waiting for all buffers empty.
1280 config ARM_ERRATA_754322
1281 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1284 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1285 r3p*) erratum. A speculative memory access may cause a page table walk
1286 which starts prior to an ASID switch but completes afterwards. This
1287 can populate the micro-TLB with a stale entry which may be hit with
1288 the new ASID. This workaround places two dsb instructions in the mm
1289 switching code so that no page table walks can cross the ASID switch.
1291 config ARM_ERRATA_754327
1292 bool "ARM errata: no automatic Store Buffer drain"
1293 depends on CPU_V7 && SMP
1295 This option enables the workaround for the 754327 Cortex-A9 (prior to
1296 r2p0) erratum. The Store Buffer does not have any automatic draining
1297 mechanism and therefore a livelock may occur if an external agent
1298 continuously polls a memory location waiting to observe an update.
1299 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1300 written polling loops from denying visibility of updates to memory.
1302 config ARM_ERRATA_364296
1303 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1304 depends on CPU_V6 && !SMP
1306 This options enables the workaround for the 364296 ARM1136
1307 r0p2 erratum (possible cache data corruption with
1308 hit-under-miss enabled). It sets the undocumented bit 31 in
1309 the auxiliary control register and the FI bit in the control
1310 register, thus disabling hit-under-miss without putting the
1311 processor into full low interrupt latency mode. ARM11MPCore
1314 config ARM_ERRATA_764369
1315 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1316 depends on CPU_V7 && SMP
1318 This option enables the workaround for erratum 764369
1319 affecting Cortex-A9 MPCore with two or more processors (all
1320 current revisions). Under certain timing circumstances, a data
1321 cache line maintenance operation by MVA targeting an Inner
1322 Shareable memory region may fail to proceed up to either the
1323 Point of Coherency or to the Point of Unification of the
1324 system. This workaround adds a DSB instruction before the
1325 relevant cache maintenance functions and sets a specific bit
1326 in the diagnostic control register of the SCU.
1330 source "arch/arm/common/Kconfig"
1340 Find out whether you have ISA slots on your motherboard. ISA is the
1341 name of a bus system, i.e. the way the CPU talks to the other stuff
1342 inside your box. Other bus systems are PCI, EISA, MicroChannel
1343 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1344 newer boards don't support it. If you have ISA, say Y, otherwise N.
1346 # Select ISA DMA controller support
1351 # Select ISA DMA interface
1356 bool "PCI support" if MIGHT_HAVE_PCI
1358 Find out whether you have a PCI motherboard. PCI is the name of a
1359 bus system, i.e. the way the CPU talks to the other stuff inside
1360 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1361 VESA. If you have PCI, say Y, otherwise N.
1367 config PCI_NANOENGINE
1368 bool "BSE nanoEngine PCI support"
1369 depends on SA1100_NANOENGINE
1371 Enable PCI on the BSE nanoEngine board.
1376 # Select the host bridge type
1377 config PCI_HOST_VIA82C505
1379 depends on PCI && ARCH_SHARK
1382 config PCI_HOST_ITE8152
1384 depends on PCI && MACH_ARMCORE
1388 source "drivers/pci/Kconfig"
1390 source "drivers/pcmcia/Kconfig"
1394 menu "Kernel Features"
1396 source "kernel/time/Kconfig"
1399 bool "Symmetric Multi-Processing"
1400 depends on CPU_V6K || CPU_V7
1401 depends on GENERIC_CLOCKEVENTS
1402 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1403 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1404 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1405 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || SOC_IMX6Q
1406 select USE_GENERIC_SMP_HELPERS
1407 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1409 This enables support for systems with more than one CPU. If you have
1410 a system with only one CPU, like most personal computers, say N. If
1411 you have a system with more than one CPU, say Y.
1413 If you say N here, the kernel will run on single and multiprocessor
1414 machines, but will use only one CPU of a multiprocessor machine. If
1415 you say Y here, the kernel will run on many, but not all, single
1416 processor machines. On a single processor machine, the kernel will
1417 run faster if you say N here.
1419 See also <file:Documentation/i386/IO-APIC.txt>,
1420 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1421 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1423 If you don't know what to do here, say N.
1426 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1427 depends on EXPERIMENTAL
1428 depends on SMP && !XIP_KERNEL
1431 SMP kernels contain instructions which fail on non-SMP processors.
1432 Enabling this option allows the kernel to modify itself to make
1433 these instructions safe. Disabling it allows about 1K of space
1436 If you don't know what to do here, say Y.
1438 config ARM_CPU_TOPOLOGY
1439 bool "Support cpu topology definition"
1440 depends on SMP && CPU_V7
1443 Support ARM cpu topology definition. The MPIDR register defines
1444 affinity between processors which is then used to describe the cpu
1445 topology of an ARM System.
1448 bool "Multi-core scheduler support"
1449 depends on ARM_CPU_TOPOLOGY
1451 Multi-core scheduler support improves the CPU scheduler's decision
1452 making when dealing with multi-core CPU chips at a cost of slightly
1453 increased overhead in some places. If unsure say N here.
1456 bool "SMT scheduler support"
1457 depends on ARM_CPU_TOPOLOGY
1459 Improves the CPU scheduler's decision making when dealing with
1460 MultiThreading at a cost of slightly increased overhead in some
1461 places. If unsure say N here.
1466 This option enables support for the ARM system coherency unit
1473 This options enables support for the ARM timer and watchdog unit
1476 prompt "Memory split"
1479 Select the desired split between kernel and user memory.
1481 If you are not absolutely sure what you are doing, leave this
1485 bool "3G/1G user/kernel split"
1487 bool "2G/2G user/kernel split"
1489 bool "1G/3G user/kernel split"
1494 default 0x40000000 if VMSPLIT_1G
1495 default 0x80000000 if VMSPLIT_2G
1499 int "Maximum number of CPUs (2-32)"
1505 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1506 depends on SMP && HOTPLUG && EXPERIMENTAL
1508 Say Y here to experiment with turning CPUs off and on. CPUs
1509 can be controlled through /sys/devices/system/cpu.
1512 bool "Use local timer interrupts"
1515 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1517 Enable support for local timers on SMP platforms, rather then the
1518 legacy IPI broadcast method. Local timers allows the system
1519 accounting to be spread across the timer interval, preventing a
1520 "thundering herd" at every timer tick.
1522 source kernel/Kconfig.preempt
1526 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1527 ARCH_S5PV210 || ARCH_EXYNOS4
1528 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1529 default AT91_TIMER_HZ if ARCH_AT91
1530 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1533 config THUMB2_KERNEL
1534 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1535 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1537 select ARM_ASM_UNIFIED
1539 By enabling this option, the kernel will be compiled in
1540 Thumb-2 mode. A compiler/assembler that understand the unified
1541 ARM-Thumb syntax is needed.
1545 config THUMB2_AVOID_R_ARM_THM_JUMP11
1546 bool "Work around buggy Thumb-2 short branch relocations in gas"
1547 depends on THUMB2_KERNEL && MODULES
1550 Various binutils versions can resolve Thumb-2 branches to
1551 locally-defined, preemptible global symbols as short-range "b.n"
1552 branch instructions.
1554 This is a problem, because there's no guarantee the final
1555 destination of the symbol, or any candidate locations for a
1556 trampoline, are within range of the branch. For this reason, the
1557 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1558 relocation in modules at all, and it makes little sense to add
1561 The symptom is that the kernel fails with an "unsupported
1562 relocation" error when loading some modules.
1564 Until fixed tools are available, passing
1565 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1566 code which hits this problem, at the cost of a bit of extra runtime
1567 stack usage in some cases.
1569 The problem is described in more detail at:
1570 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1572 Only Thumb-2 kernels are affected.
1574 Unless you are sure your tools don't have this problem, say Y.
1576 config ARM_ASM_UNIFIED
1580 bool "Use the ARM EABI to compile the kernel"
1582 This option allows for the kernel to be compiled using the latest
1583 ARM ABI (aka EABI). This is only useful if you are using a user
1584 space environment that is also compiled with EABI.
1586 Since there are major incompatibilities between the legacy ABI and
1587 EABI, especially with regard to structure member alignment, this
1588 option also changes the kernel syscall calling convention to
1589 disambiguate both ABIs and allow for backward compatibility support
1590 (selected with CONFIG_OABI_COMPAT).
1592 To use this you need GCC version 4.0.0 or later.
1595 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1596 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1599 This option preserves the old syscall interface along with the
1600 new (ARM EABI) one. It also provides a compatibility layer to
1601 intercept syscalls that have structure arguments which layout
1602 in memory differs between the legacy ABI and the new ARM EABI
1603 (only for non "thumb" binaries). This option adds a tiny
1604 overhead to all syscalls and produces a slightly larger kernel.
1605 If you know you'll be using only pure EABI user space then you
1606 can say N here. If this option is not selected and you attempt
1607 to execute a legacy ABI binary then the result will be
1608 UNPREDICTABLE (in fact it can be predicted that it won't work
1609 at all). If in doubt say Y.
1611 config ARCH_HAS_HOLES_MEMORYMODEL
1614 config ARCH_SPARSEMEM_ENABLE
1617 config ARCH_SPARSEMEM_DEFAULT
1618 def_bool ARCH_SPARSEMEM_ENABLE
1620 config ARCH_SELECT_MEMORY_MODEL
1621 def_bool ARCH_SPARSEMEM_ENABLE
1623 config HAVE_ARCH_PFN_VALID
1624 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1627 bool "High Memory Support"
1630 The address space of ARM processors is only 4 Gigabytes large
1631 and it has to accommodate user address space, kernel address
1632 space as well as some memory mapped IO. That means that, if you
1633 have a large amount of physical memory and/or IO, not all of the
1634 memory can be "permanently mapped" by the kernel. The physical
1635 memory that is not permanently mapped is called "high memory".
1637 Depending on the selected kernel/user memory split, minimum
1638 vmalloc space and actual amount of RAM, you may not need this
1639 option which should result in a slightly faster kernel.
1644 bool "Allocate 2nd-level pagetables from highmem"
1647 config HW_PERF_EVENTS
1648 bool "Enable hardware performance counter support for perf events"
1649 depends on PERF_EVENTS && CPU_HAS_PMU
1652 Enable hardware performance counter support for perf events. If
1653 disabled, perf events will use software events only.
1657 config FORCE_MAX_ZONEORDER
1658 int "Maximum zone order" if ARCH_SHMOBILE
1659 range 11 64 if ARCH_SHMOBILE
1660 default "9" if SA1111
1663 The kernel memory allocator divides physically contiguous memory
1664 blocks into "zones", where each zone is a power of two number of
1665 pages. This option selects the largest power of two that the kernel
1666 keeps in the memory allocator. If you need to allocate very large
1667 blocks of physically contiguous memory, then you may need to
1668 increase this value.
1670 This config option is actually maximum order plus one. For example,
1671 a value of 11 means that the largest free memory block is 2^10 pages.
1674 bool "Timer and CPU usage LEDs"
1675 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1676 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1677 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1678 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1679 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1680 ARCH_AT91 || ARCH_DAVINCI || \
1681 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1683 If you say Y here, the LEDs on your machine will be used
1684 to provide useful information about your current system status.
1686 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1687 be able to select which LEDs are active using the options below. If
1688 you are compiling a kernel for the EBSA-110 or the LART however, the
1689 red LED will simply flash regularly to indicate that the system is
1690 still functional. It is safe to say Y here if you have a CATS
1691 system, but the driver will do nothing.
1694 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1695 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1696 || MACH_OMAP_PERSEUS2
1698 depends on !GENERIC_CLOCKEVENTS
1699 default y if ARCH_EBSA110
1701 If you say Y here, one of the system LEDs (the green one on the
1702 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1703 will flash regularly to indicate that the system is still
1704 operational. This is mainly useful to kernel hackers who are
1705 debugging unstable kernels.
1707 The LART uses the same LED for both Timer LED and CPU usage LED
1708 functions. You may choose to use both, but the Timer LED function
1709 will overrule the CPU usage LED.
1712 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1714 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1715 || MACH_OMAP_PERSEUS2
1718 If you say Y here, the red LED will be used to give a good real
1719 time indication of CPU usage, by lighting whenever the idle task
1720 is not currently executing.
1722 The LART uses the same LED for both Timer LED and CPU usage LED
1723 functions. You may choose to use both, but the Timer LED function
1724 will overrule the CPU usage LED.
1726 config ALIGNMENT_TRAP
1728 depends on CPU_CP15_MMU
1729 default y if !ARCH_EBSA110
1730 select HAVE_PROC_CPU if PROC_FS
1732 ARM processors cannot fetch/store information which is not
1733 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1734 address divisible by 4. On 32-bit ARM processors, these non-aligned
1735 fetch/store instructions will be emulated in software if you say
1736 here, which has a severe performance impact. This is necessary for
1737 correct operation of some network protocols. With an IP-only
1738 configuration it is safe to say N, otherwise say Y.
1740 config UACCESS_WITH_MEMCPY
1741 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1742 depends on MMU && EXPERIMENTAL
1743 default y if CPU_FEROCEON
1745 Implement faster copy_to_user and clear_user methods for CPU
1746 cores where a 8-word STM instruction give significantly higher
1747 memory write throughput than a sequence of individual 32bit stores.
1749 A possible side effect is a slight increase in scheduling latency
1750 between threads sharing the same address space if they invoke
1751 such copy operations with large buffers.
1753 However, if the CPU data cache is using a write-allocate mode,
1754 this option is unlikely to provide any performance gain.
1758 prompt "Enable seccomp to safely compute untrusted bytecode"
1760 This kernel feature is useful for number crunching applications
1761 that may need to compute untrusted bytecode during their
1762 execution. By using pipes or other transports made available to
1763 the process as file descriptors supporting the read/write
1764 syscalls, it's possible to isolate those applications in
1765 their own address space using seccomp. Once seccomp is
1766 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1767 and the task is only allowed to execute a few safe syscalls
1768 defined by each seccomp mode.
1770 config CC_STACKPROTECTOR
1771 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1772 depends on EXPERIMENTAL
1774 This option turns on the -fstack-protector GCC feature. This
1775 feature puts, at the beginning of functions, a canary value on
1776 the stack just before the return address, and validates
1777 the value just before actually returning. Stack based buffer
1778 overflows (that need to overwrite this return address) now also
1779 overwrite the canary, which gets detected and the attack is then
1780 neutralized via a kernel panic.
1781 This feature requires gcc version 4.2 or above.
1783 config DEPRECATED_PARAM_STRUCT
1784 bool "Provide old way to pass kernel parameters"
1786 This was deprecated in 2001 and announced to live on for 5 years.
1787 Some old boot loaders still use this way.
1794 bool "Flattened Device Tree support"
1796 select OF_EARLY_FLATTREE
1799 Include support for flattened device tree machine descriptions.
1801 # Compressed boot loader in ROM. Yes, we really want to ask about
1802 # TEXT and BSS so we preserve their values in the config files.
1803 config ZBOOT_ROM_TEXT
1804 hex "Compressed ROM boot loader base address"
1807 The physical address at which the ROM-able zImage is to be
1808 placed in the target. Platforms which normally make use of
1809 ROM-able zImage formats normally set this to a suitable
1810 value in their defconfig file.
1812 If ZBOOT_ROM is not enabled, this has no effect.
1814 config ZBOOT_ROM_BSS
1815 hex "Compressed ROM boot loader BSS address"
1818 The base address of an area of read/write memory in the target
1819 for the ROM-able zImage which must be available while the
1820 decompressor is running. It must be large enough to hold the
1821 entire decompressed kernel plus an additional 128 KiB.
1822 Platforms which normally make use of ROM-able zImage formats
1823 normally set this to a suitable value in their defconfig file.
1825 If ZBOOT_ROM is not enabled, this has no effect.
1828 bool "Compressed boot loader in ROM/flash"
1829 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1831 Say Y here if you intend to execute your compressed kernel image
1832 (zImage) directly from ROM or flash. If unsure, say N.
1835 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1836 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1837 default ZBOOT_ROM_NONE
1839 Include experimental SD/MMC loading code in the ROM-able zImage.
1840 With this enabled it is possible to write the the ROM-able zImage
1841 kernel image to an MMC or SD card and boot the kernel straight
1842 from the reset vector. At reset the processor Mask ROM will load
1843 the first part of the the ROM-able zImage which in turn loads the
1844 rest the kernel image to RAM.
1846 config ZBOOT_ROM_NONE
1847 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1849 Do not load image from SD or MMC
1851 config ZBOOT_ROM_MMCIF
1852 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1854 Load image from MMCIF hardware block.
1856 config ZBOOT_ROM_SH_MOBILE_SDHI
1857 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1859 Load image from SDHI hardware block
1863 config ARM_APPENDED_DTB
1864 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1865 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1867 With this option, the boot code will look for a device tree binary
1868 (DTB) appended to zImage
1869 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1871 This is meant as a backward compatibility convenience for those
1872 systems with a bootloader that can't be upgraded to accommodate
1873 the documented boot protocol using a device tree.
1875 Beware that there is very little in terms of protection against
1876 this option being confused by leftover garbage in memory that might
1877 look like a DTB header after a reboot if no actual DTB is appended
1878 to zImage. Do not leave this option active in a production kernel
1879 if you don't intend to always append a DTB. Proper passing of the
1880 location into r2 of a bootloader provided DTB is always preferable
1883 config ARM_ATAG_DTB_COMPAT
1884 bool "Supplement the appended DTB with traditional ATAG information"
1885 depends on ARM_APPENDED_DTB
1887 Some old bootloaders can't be updated to a DTB capable one, yet
1888 they provide ATAGs with memory configuration, the ramdisk address,
1889 the kernel cmdline string, etc. Such information is dynamically
1890 provided by the bootloader and can't always be stored in a static
1891 DTB. To allow a device tree enabled kernel to be used with such
1892 bootloaders, this option allows zImage to extract the information
1893 from the ATAG list and store it at run time into the appended DTB.
1896 string "Default kernel command string"
1899 On some architectures (EBSA110 and CATS), there is currently no way
1900 for the boot loader to pass arguments to the kernel. For these
1901 architectures, you should supply some command-line options at build
1902 time by entering them here. As a minimum, you should specify the
1903 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1906 prompt "Kernel command line type" if CMDLINE != ""
1907 default CMDLINE_FROM_BOOTLOADER
1909 config CMDLINE_FROM_BOOTLOADER
1910 bool "Use bootloader kernel arguments if available"
1912 Uses the command-line options passed by the boot loader. If
1913 the boot loader doesn't provide any, the default kernel command
1914 string provided in CMDLINE will be used.
1916 config CMDLINE_EXTEND
1917 bool "Extend bootloader kernel arguments"
1919 The command-line arguments provided by the boot loader will be
1920 appended to the default kernel command string.
1922 config CMDLINE_FORCE
1923 bool "Always use the default kernel command string"
1925 Always use the default kernel command string, even if the boot
1926 loader passes other arguments to the kernel.
1927 This is useful if you cannot or don't want to change the
1928 command-line options your boot loader passes to the kernel.
1932 bool "Kernel Execute-In-Place from ROM"
1933 depends on !ZBOOT_ROM
1935 Execute-In-Place allows the kernel to run from non-volatile storage
1936 directly addressable by the CPU, such as NOR flash. This saves RAM
1937 space since the text section of the kernel is not loaded from flash
1938 to RAM. Read-write sections, such as the data section and stack,
1939 are still copied to RAM. The XIP kernel is not compressed since
1940 it has to run directly from flash, so it will take more space to
1941 store it. The flash address used to link the kernel object files,
1942 and for storing it, is configuration dependent. Therefore, if you
1943 say Y here, you must know the proper physical address where to
1944 store the kernel image depending on your own flash memory usage.
1946 Also note that the make target becomes "make xipImage" rather than
1947 "make zImage" or "make Image". The final kernel binary to put in
1948 ROM memory will be arch/arm/boot/xipImage.
1952 config XIP_PHYS_ADDR
1953 hex "XIP Kernel Physical Location"
1954 depends on XIP_KERNEL
1955 default "0x00080000"
1957 This is the physical address in your flash memory the kernel will
1958 be linked for and stored to. This address is dependent on your
1962 bool "Kexec system call (EXPERIMENTAL)"
1963 depends on EXPERIMENTAL
1965 kexec is a system call that implements the ability to shutdown your
1966 current kernel, and to start another kernel. It is like a reboot
1967 but it is independent of the system firmware. And like a reboot
1968 you can start any kernel with it, not just Linux.
1970 It is an ongoing process to be certain the hardware in a machine
1971 is properly shutdown, so do not be surprised if this code does not
1972 initially work for you. It may help to enable device hotplugging
1976 bool "Export atags in procfs"
1980 Should the atags used to boot the kernel be exported in an "atags"
1981 file in procfs. Useful with kexec.
1984 bool "Build kdump crash kernel (EXPERIMENTAL)"
1985 depends on EXPERIMENTAL
1987 Generate crash dump after being started by kexec. This should
1988 be normally only set in special crash dump kernels which are
1989 loaded in the main kernel with kexec-tools into a specially
1990 reserved region and then later executed after a crash by
1991 kdump/kexec. The crash dump kernel must be compiled to a
1992 memory address not used by the main kernel
1994 For more details see Documentation/kdump/kdump.txt
1996 config AUTO_ZRELADDR
1997 bool "Auto calculation of the decompressed kernel image address"
1998 depends on !ZBOOT_ROM && !ARCH_U300
2000 ZRELADDR is the physical address where the decompressed kernel
2001 image will be placed. If AUTO_ZRELADDR is selected, the address
2002 will be determined at run-time by masking the current IP with
2003 0xf8000000. This assumes the zImage being placed in the first 128MB
2004 from start of memory.
2008 menu "CPU Power Management"
2012 source "drivers/cpufreq/Kconfig"
2015 tristate "CPUfreq driver for i.MX CPUs"
2016 depends on ARCH_MXC && CPU_FREQ
2018 This enables the CPUfreq driver for i.MX CPUs.
2020 config CPU_FREQ_SA1100
2023 config CPU_FREQ_SA1110
2026 config CPU_FREQ_INTEGRATOR
2027 tristate "CPUfreq driver for ARM Integrator CPUs"
2028 depends on ARCH_INTEGRATOR && CPU_FREQ
2031 This enables the CPUfreq driver for ARM Integrator CPUs.
2033 For details, take a look at <file:Documentation/cpu-freq>.
2039 depends on CPU_FREQ && ARCH_PXA && PXA25x
2041 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2046 Internal configuration node for common cpufreq on Samsung SoC
2048 config CPU_FREQ_S3C24XX
2049 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2050 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2053 This enables the CPUfreq driver for the Samsung S3C24XX family
2056 For details, take a look at <file:Documentation/cpu-freq>.
2060 config CPU_FREQ_S3C24XX_PLL
2061 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2062 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2064 Compile in support for changing the PLL frequency from the
2065 S3C24XX series CPUfreq driver. The PLL takes time to settle
2066 after a frequency change, so by default it is not enabled.
2068 This also means that the PLL tables for the selected CPU(s) will
2069 be built which may increase the size of the kernel image.
2071 config CPU_FREQ_S3C24XX_DEBUG
2072 bool "Debug CPUfreq Samsung driver core"
2073 depends on CPU_FREQ_S3C24XX
2075 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2077 config CPU_FREQ_S3C24XX_IODEBUG
2078 bool "Debug CPUfreq Samsung driver IO timing"
2079 depends on CPU_FREQ_S3C24XX
2081 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2083 config CPU_FREQ_S3C24XX_DEBUGFS
2084 bool "Export debugfs for CPUFreq"
2085 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2087 Export status information via debugfs.
2091 source "drivers/cpuidle/Kconfig"
2095 menu "Floating point emulation"
2097 comment "At least one emulation must be selected"
2100 bool "NWFPE math emulation"
2101 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2103 Say Y to include the NWFPE floating point emulator in the kernel.
2104 This is necessary to run most binaries. Linux does not currently
2105 support floating point hardware so you need to say Y here even if
2106 your machine has an FPA or floating point co-processor podule.
2108 You may say N here if you are going to load the Acorn FPEmulator
2109 early in the bootup.
2112 bool "Support extended precision"
2113 depends on FPE_NWFPE
2115 Say Y to include 80-bit support in the kernel floating-point
2116 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2117 Note that gcc does not generate 80-bit operations by default,
2118 so in most cases this option only enlarges the size of the
2119 floating point emulator without any good reason.
2121 You almost surely want to say N here.
2124 bool "FastFPE math emulation (EXPERIMENTAL)"
2125 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2127 Say Y here to include the FAST floating point emulator in the kernel.
2128 This is an experimental much faster emulator which now also has full
2129 precision for the mantissa. It does not support any exceptions.
2130 It is very simple, and approximately 3-6 times faster than NWFPE.
2132 It should be sufficient for most programs. It may be not suitable
2133 for scientific calculations, but you have to check this for yourself.
2134 If you do not feel you need a faster FP emulation you should better
2138 bool "VFP-format floating point maths"
2139 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2141 Say Y to include VFP support code in the kernel. This is needed
2142 if your hardware includes a VFP unit.
2144 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2145 release notes and additional status information.
2147 Say N if your target does not have VFP hardware.
2155 bool "Advanced SIMD (NEON) Extension support"
2156 depends on VFPv3 && CPU_V7
2158 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2163 menu "Userspace binary formats"
2165 source "fs/Kconfig.binfmt"
2168 tristate "RISC OS personality"
2171 Say Y here to include the kernel code necessary if you want to run
2172 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2173 experimental; if this sounds frightening, say N and sleep in peace.
2174 You can also say M here to compile this support as a module (which
2175 will be called arthur).
2179 menu "Power management options"
2181 source "kernel/power/Kconfig"
2183 config ARCH_SUSPEND_POSSIBLE
2184 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2185 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2186 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2191 source "net/Kconfig"
2193 source "drivers/Kconfig"
2197 source "arch/arm/Kconfig.debug"
2199 source "security/Kconfig"
2201 source "crypto/Kconfig"
2203 source "lib/Kconfig"