5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
12 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
14 select HAVE_KPROBES if !XIP_KERNEL
15 select HAVE_KRETPROBES if (HAVE_KPROBES)
16 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
17 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
18 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
19 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
20 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
21 select HAVE_GENERIC_DMA_COHERENT
22 select HAVE_KERNEL_GZIP
23 select HAVE_KERNEL_LZO
24 select HAVE_KERNEL_LZMA
27 select HAVE_PERF_EVENTS
28 select PERF_USE_VMALLOC
29 select HAVE_REGS_AND_STACK_ACCESS_API
30 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
31 select HAVE_C_RECORDMCOUNT
32 select HAVE_GENERIC_HARDIRQS
33 select GENERIC_IRQ_SHOW
34 select GENERIC_IRQ_PROBE
35 select HARDIRQS_SW_RESEND
36 select CPU_PM if (SUSPEND || CPU_IDLE)
37 select GENERIC_PCI_IOMAP
38 select HAVE_BPF_JIT if NET
40 The ARM series is a line of low-power-consumption RISC chip designs
41 licensed by ARM Ltd and targeted at embedded applications and
42 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
43 manufactured, but legacy ARM-based PC hardware remains popular in
44 Europe. There is an ARM Linux project with a web page at
45 <http://www.arm.linux.org.uk/>.
47 config ARM_HAS_SG_CHAIN
56 config SYS_SUPPORTS_APM_EMULATION
62 config ARCH_USES_GETTIMEOFFSET
66 config GENERIC_CLOCKEVENTS
69 config GENERIC_CLOCKEVENTS_BROADCAST
71 depends on GENERIC_CLOCKEVENTS
80 select GENERIC_ALLOCATOR
91 The Extended Industry Standard Architecture (EISA) bus was
92 developed as an open alternative to the IBM MicroChannel bus.
94 The EISA bus provided some of the features of the IBM MicroChannel
95 bus while maintaining backward compatibility with cards made for
96 the older ISA bus. The EISA bus saw limited use between 1988 and
97 1995 when it was made obsolete by the PCI bus.
99 Say Y here if you are building a kernel for an EISA-based machine.
109 MicroChannel Architecture is found in some IBM PS/2 machines and
110 laptops. It is a bus system similar to PCI or ISA. See
111 <file:Documentation/mca.txt> (and especially the web page given
112 there) before attempting to build an MCA bus kernel.
114 config STACKTRACE_SUPPORT
118 config HAVE_LATENCYTOP_SUPPORT
123 config LOCKDEP_SUPPORT
127 config TRACE_IRQFLAGS_SUPPORT
131 config GENERIC_LOCKBREAK
134 depends on SMP && PREEMPT
136 config RWSEM_GENERIC_SPINLOCK
140 config RWSEM_XCHGADD_ALGORITHM
143 config ARCH_HAS_ILOG2_U32
146 config ARCH_HAS_ILOG2_U64
149 config ARCH_HAS_CPUFREQ
152 Internal node to signify that the ARCH has CPUFREQ support
153 and that the relevant menu configurations are displayed for
156 config ARCH_HAS_CPU_IDLE_WAIT
159 config GENERIC_HWEIGHT
163 config GENERIC_CALIBRATE_DELAY
167 config ARCH_MAY_HAVE_PC_FDC
173 config NEED_DMA_MAP_STATE
176 config ARCH_HAS_DMA_SET_COHERENT_MASK
179 config GENERIC_ISA_DMA
185 config NEED_RET_TO_USER
193 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
194 default DRAM_BASE if REMAP_VECTORS_TO_RAM
197 The base address of exception vectors.
199 config ARM_PATCH_PHYS_VIRT
200 bool "Patch physical to virtual translations at runtime" if EMBEDDED
202 depends on !XIP_KERNEL && MMU
203 depends on !ARCH_REALVIEW || !SPARSEMEM
205 Patch phys-to-virt and virt-to-phys translation functions at
206 boot and module load time according to the position of the
207 kernel in system memory.
209 This can only be used with non-XIP MMU kernels where the base
210 of physical memory is at a 16MB boundary.
212 Only disable this option if you know that you do not require
213 this feature (eg, building a kernel for a single machine) and
214 you need to shrink the kernel to the minimal size.
216 config NEED_MACH_IO_H
219 Select this when mach/io.h is required to provide special
220 definitions for this platform. The need for mach/io.h should
221 be avoided when possible.
223 config NEED_MACH_MEMORY_H
226 Select this when mach/memory.h is required to provide special
227 definitions for this platform. The need for mach/memory.h should
228 be avoided when possible.
231 hex "Physical address of main memory" if MMU
232 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
233 default DRAM_BASE if !MMU
235 Please provide the physical address corresponding to the
236 location of main memory in your system.
242 source "init/Kconfig"
244 source "kernel/Kconfig.freezer"
249 bool "MMU-based Paged Memory Management Support"
252 Select if you want MMU-based virtualised addressing space
253 support by paged memory management. If unsure, say 'Y'.
256 # The "ARM system type" choice list is ordered alphabetically by option
257 # text. Please add new entries in the option alphabetic order.
260 prompt "ARM system type"
261 default ARCH_VERSATILE
263 config ARCH_INTEGRATOR
264 bool "ARM Ltd. Integrator family"
266 select ARCH_HAS_CPUFREQ
268 select HAVE_MACH_CLKDEV
271 select GENERIC_CLOCKEVENTS
272 select PLAT_VERSATILE
273 select PLAT_VERSATILE_FPGA_IRQ
274 select NEED_MACH_IO_H
275 select NEED_MACH_MEMORY_H
278 Support for ARM's Integrator platform.
281 bool "ARM Ltd. RealView family"
284 select HAVE_MACH_CLKDEV
286 select GENERIC_CLOCKEVENTS
287 select ARCH_WANT_OPTIONAL_GPIOLIB
288 select PLAT_VERSATILE
289 select PLAT_VERSATILE_CLCD
290 select ARM_TIMER_SP804
291 select GPIO_PL061 if GPIOLIB
292 select NEED_MACH_MEMORY_H
294 This enables support for ARM Ltd RealView boards.
296 config ARCH_VERSATILE
297 bool "ARM Ltd. Versatile family"
301 select HAVE_MACH_CLKDEV
303 select GENERIC_CLOCKEVENTS
304 select ARCH_WANT_OPTIONAL_GPIOLIB
305 select PLAT_VERSATILE
306 select PLAT_VERSATILE_CLCD
307 select PLAT_VERSATILE_FPGA_IRQ
308 select ARM_TIMER_SP804
310 This enables support for ARM Ltd Versatile board.
313 bool "ARM Ltd. Versatile Express family"
314 select ARCH_WANT_OPTIONAL_GPIOLIB
316 select ARM_TIMER_SP804
318 select HAVE_MACH_CLKDEV
319 select GENERIC_CLOCKEVENTS
321 select HAVE_PATA_PLATFORM
324 select PLAT_VERSATILE
325 select PLAT_VERSATILE_CLCD
327 This enables support for the ARM Ltd Versatile Express boards.
331 select ARCH_REQUIRE_GPIOLIB
335 select NEED_MACH_IO_H if PCCARD
337 This enables support for systems based on the Atmel AT91RM9200,
341 bool "Broadcom BCMRING"
345 select ARM_TIMER_SP804
347 select GENERIC_CLOCKEVENTS
348 select ARCH_WANT_OPTIONAL_GPIOLIB
350 Support for Broadcom's BCMRing platform.
353 bool "Calxeda Highbank-based"
354 select ARCH_WANT_OPTIONAL_GPIOLIB
357 select ARM_TIMER_SP804
361 select GENERIC_CLOCKEVENTS
367 Support for the Calxeda Highbank SoC based boards.
370 bool "Cirrus Logic CLPS711x/EP721x-based"
372 select ARCH_USES_GETTIMEOFFSET
373 select NEED_MACH_MEMORY_H
375 Support for Cirrus Logic 711x/721x based boards.
378 bool "Cavium Networks CNS3XXX family"
380 select GENERIC_CLOCKEVENTS
382 select MIGHT_HAVE_CACHE_L2X0
383 select MIGHT_HAVE_PCI
384 select PCI_DOMAINS if PCI
386 Support for Cavium Networks CNS3XXX platform.
389 bool "Cortina Systems Gemini"
391 select ARCH_REQUIRE_GPIOLIB
392 select ARCH_USES_GETTIMEOFFSET
394 Support for the Cortina Systems Gemini family SoCs
397 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
400 select GENERIC_CLOCKEVENTS
402 select GENERIC_IRQ_CHIP
403 select MIGHT_HAVE_CACHE_L2X0
407 Support for CSR SiRFSoC ARM Cortex A9 Platform
414 select ARCH_USES_GETTIMEOFFSET
415 select NEED_MACH_IO_H
416 select NEED_MACH_MEMORY_H
418 This is an evaluation board for the StrongARM processor available
419 from Digital. It has limited hardware on-board, including an
420 Ethernet interface, two PCMCIA sockets, two serial ports and a
429 select ARCH_REQUIRE_GPIOLIB
430 select ARCH_HAS_HOLES_MEMORYMODEL
431 select ARCH_USES_GETTIMEOFFSET
432 select NEED_MACH_MEMORY_H
434 This enables support for the Cirrus EP93xx series of CPUs.
436 config ARCH_FOOTBRIDGE
440 select GENERIC_CLOCKEVENTS
442 select NEED_MACH_IO_H
443 select NEED_MACH_MEMORY_H
445 Support for systems based on the DC21285 companion chip
446 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
449 bool "Freescale MXC/iMX-based"
450 select GENERIC_CLOCKEVENTS
451 select ARCH_REQUIRE_GPIOLIB
454 select GENERIC_IRQ_CHIP
455 select MULTI_IRQ_HANDLER
457 Support for Freescale MXC/iMX-based family of processors
460 bool "Freescale MXS-based"
461 select GENERIC_CLOCKEVENTS
462 select ARCH_REQUIRE_GPIOLIB
465 select HAVE_CLK_PREPARE
467 Support for Freescale MXS-based family of processors
470 bool "Hilscher NetX based"
474 select GENERIC_CLOCKEVENTS
476 This enables support for systems based on the Hilscher NetX Soc
479 bool "Hynix HMS720x-based"
482 select ARCH_USES_GETTIMEOFFSET
484 This enables support for systems based on the Hynix HMS720x
492 select ARCH_SUPPORTS_MSI
494 select NEED_MACH_IO_H
495 select NEED_MACH_MEMORY_H
496 select NEED_RET_TO_USER
498 Support for Intel's IOP13XX (XScale) family of processors.
504 select NEED_MACH_IO_H
505 select NEED_RET_TO_USER
508 select ARCH_REQUIRE_GPIOLIB
510 Support for Intel's 80219 and IOP32X (XScale) family of
517 select NEED_MACH_IO_H
518 select NEED_RET_TO_USER
521 select ARCH_REQUIRE_GPIOLIB
523 Support for Intel's IOP33X (XScale) family of processors.
530 select ARCH_USES_GETTIMEOFFSET
531 select NEED_MACH_IO_H
532 select NEED_MACH_MEMORY_H
534 Support for Intel's IXP23xx (XScale) family of processors.
537 bool "IXP2400/2800-based"
541 select ARCH_USES_GETTIMEOFFSET
542 select NEED_MACH_IO_H
543 select NEED_MACH_MEMORY_H
545 Support for Intel's IXP2400/2800 (XScale) family of processors.
550 select ARCH_HAS_DMA_SET_COHERENT_MASK
554 select GENERIC_CLOCKEVENTS
555 select MIGHT_HAVE_PCI
556 select NEED_MACH_IO_H
557 select DMABOUNCE if PCI
559 Support for Intel's IXP4XX (XScale) family of processors.
565 select ARCH_REQUIRE_GPIOLIB
566 select GENERIC_CLOCKEVENTS
567 select NEED_MACH_IO_H
570 Support for the Marvell Dove SoC 88AP510
573 bool "Marvell Kirkwood"
576 select ARCH_REQUIRE_GPIOLIB
577 select GENERIC_CLOCKEVENTS
578 select NEED_MACH_IO_H
581 Support for the following Marvell Kirkwood series SoCs:
582 88F6180, 88F6192 and 88F6281.
588 select ARCH_REQUIRE_GPIOLIB
591 select USB_ARCH_HAS_OHCI
593 select GENERIC_CLOCKEVENTS
595 Support for the NXP LPC32XX family of processors
598 bool "Marvell MV78xx0"
601 select ARCH_REQUIRE_GPIOLIB
602 select GENERIC_CLOCKEVENTS
603 select NEED_MACH_IO_H
606 Support for the following Marvell MV78xx0 series SoCs:
614 select ARCH_REQUIRE_GPIOLIB
615 select GENERIC_CLOCKEVENTS
618 Support for the following Marvell Orion 5x series SoCs:
619 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
620 Orion-2 (5281), Orion-1-90 (6183).
623 bool "Marvell PXA168/910/MMP2"
625 select ARCH_REQUIRE_GPIOLIB
627 select GENERIC_CLOCKEVENTS
632 select GENERIC_ALLOCATOR
634 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
637 bool "Micrel/Kendin KS8695"
639 select ARCH_REQUIRE_GPIOLIB
640 select ARCH_USES_GETTIMEOFFSET
641 select NEED_MACH_MEMORY_H
643 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
644 System-on-Chip devices.
647 bool "Nuvoton W90X900 CPU"
649 select ARCH_REQUIRE_GPIOLIB
652 select GENERIC_CLOCKEVENTS
654 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
655 At present, the w90x900 has been renamed nuc900, regarding
656 the ARM series product line, you can login the following
657 link address to know more.
659 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
660 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
666 select GENERIC_CLOCKEVENTS
670 select MIGHT_HAVE_CACHE_L2X0
671 select NEED_MACH_IO_H if PCI
672 select ARCH_HAS_CPUFREQ
674 This enables support for NVIDIA Tegra based systems (Tegra APX,
675 Tegra 6xx and Tegra 2 series).
677 config ARCH_PICOXCELL
678 bool "Picochip picoXcell"
679 select ARCH_REQUIRE_GPIOLIB
680 select ARM_PATCH_PHYS_VIRT
684 select GENERIC_CLOCKEVENTS
691 This enables support for systems based on the Picochip picoXcell
692 family of Femtocell devices. The picoxcell support requires device tree
696 bool "Philips Nexperia PNX4008 Mobile"
699 select ARCH_USES_GETTIMEOFFSET
701 This enables support for Philips PNX4008 mobile platform.
704 bool "PXA2xx/PXA3xx-based"
707 select ARCH_HAS_CPUFREQ
710 select ARCH_REQUIRE_GPIOLIB
711 select GENERIC_CLOCKEVENTS
717 select MULTI_IRQ_HANDLER
718 select ARM_CPU_SUSPEND if PM
721 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
726 select GENERIC_CLOCKEVENTS
727 select ARCH_REQUIRE_GPIOLIB
730 Support for Qualcomm MSM/QSD based systems. This runs on the
731 apps processor of the MSM/QSD and depends on a shared memory
732 interface to the modem processor which runs the baseband
733 stack and controls some vital subsystems
734 (clock and power control, etc).
737 bool "Renesas SH-Mobile / R-Mobile"
740 select HAVE_MACH_CLKDEV
742 select GENERIC_CLOCKEVENTS
743 select MIGHT_HAVE_CACHE_L2X0
746 select MULTI_IRQ_HANDLER
747 select PM_GENERIC_DOMAINS if PM
748 select NEED_MACH_MEMORY_H
750 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
756 select ARCH_MAY_HAVE_PC_FDC
757 select HAVE_PATA_PLATFORM
760 select ARCH_SPARSEMEM_ENABLE
761 select ARCH_USES_GETTIMEOFFSET
763 select NEED_MACH_IO_H
764 select NEED_MACH_MEMORY_H
766 On the Acorn Risc-PC, Linux can support the internal IDE disk and
767 CD-ROM interface, serial and parallel port, and the floppy drive.
774 select ARCH_SPARSEMEM_ENABLE
776 select ARCH_HAS_CPUFREQ
778 select GENERIC_CLOCKEVENTS
781 select ARCH_REQUIRE_GPIOLIB
783 select NEED_MACH_MEMORY_H
786 Support for StrongARM 11x0 based boards.
789 bool "Samsung S3C24XX SoCs"
791 select ARCH_HAS_CPUFREQ
794 select ARCH_USES_GETTIMEOFFSET
795 select HAVE_S3C2410_I2C if I2C
796 select HAVE_S3C_RTC if RTC_CLASS
797 select HAVE_S3C2410_WATCHDOG if WATCHDOG
798 select NEED_MACH_IO_H
800 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
801 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
802 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
803 Samsung SMDK2410 development board (and derivatives).
806 bool "Samsung S3C64XX"
814 select ARCH_USES_GETTIMEOFFSET
815 select ARCH_HAS_CPUFREQ
816 select ARCH_REQUIRE_GPIOLIB
817 select SAMSUNG_CLKSRC
818 select SAMSUNG_IRQ_VIC_TIMER
819 select S3C_GPIO_TRACK
821 select USB_ARCH_HAS_OHCI
822 select SAMSUNG_GPIOLIB_4BIT
823 select HAVE_S3C2410_I2C if I2C
824 select HAVE_S3C2410_WATCHDOG if WATCHDOG
826 Samsung S3C64XX series based systems
829 bool "Samsung S5P6440 S5P6450"
835 select HAVE_S3C2410_WATCHDOG if WATCHDOG
836 select GENERIC_CLOCKEVENTS
837 select HAVE_S3C2410_I2C if I2C
838 select HAVE_S3C_RTC if RTC_CLASS
840 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
844 bool "Samsung S5PC100"
849 select ARCH_USES_GETTIMEOFFSET
850 select HAVE_S3C2410_I2C if I2C
851 select HAVE_S3C_RTC if RTC_CLASS
852 select HAVE_S3C2410_WATCHDOG if WATCHDOG
854 Samsung S5PC100 series based systems
857 bool "Samsung S5PV210/S5PC110"
859 select ARCH_SPARSEMEM_ENABLE
860 select ARCH_HAS_HOLES_MEMORYMODEL
865 select ARCH_HAS_CPUFREQ
866 select GENERIC_CLOCKEVENTS
867 select HAVE_S3C2410_I2C if I2C
868 select HAVE_S3C_RTC if RTC_CLASS
869 select HAVE_S3C2410_WATCHDOG if WATCHDOG
870 select NEED_MACH_MEMORY_H
872 Samsung S5PV210/S5PC110 series based systems
875 bool "SAMSUNG EXYNOS"
877 select ARCH_SPARSEMEM_ENABLE
878 select ARCH_HAS_HOLES_MEMORYMODEL
882 select ARCH_HAS_CPUFREQ
883 select GENERIC_CLOCKEVENTS
884 select HAVE_S3C_RTC if RTC_CLASS
885 select HAVE_S3C2410_I2C if I2C
886 select HAVE_S3C2410_WATCHDOG if WATCHDOG
887 select NEED_MACH_MEMORY_H
889 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
898 select ARCH_USES_GETTIMEOFFSET
899 select NEED_MACH_MEMORY_H
900 select NEED_MACH_IO_H
902 Support for the StrongARM based Digital DNARD machine, also known
903 as "Shark" (<http://www.shark-linux.de/shark.html>).
906 bool "ST-Ericsson U300 Series"
912 select ARM_PATCH_PHYS_VIRT
914 select GENERIC_CLOCKEVENTS
916 select HAVE_MACH_CLKDEV
918 select ARCH_REQUIRE_GPIOLIB
920 Support for ST-Ericsson U300 series mobile platforms.
923 bool "ST-Ericsson U8500 Series"
927 select GENERIC_CLOCKEVENTS
929 select ARCH_REQUIRE_GPIOLIB
930 select ARCH_HAS_CPUFREQ
932 select MIGHT_HAVE_CACHE_L2X0
934 Support for ST-Ericsson's Ux500 architecture
937 bool "STMicroelectronics Nomadik"
942 select GENERIC_CLOCKEVENTS
943 select MIGHT_HAVE_CACHE_L2X0
944 select ARCH_REQUIRE_GPIOLIB
946 Support for the Nomadik platform by ST-Ericsson
950 select GENERIC_CLOCKEVENTS
951 select ARCH_REQUIRE_GPIOLIB
955 select GENERIC_ALLOCATOR
956 select GENERIC_IRQ_CHIP
957 select ARCH_HAS_HOLES_MEMORYMODEL
959 Support for TI's DaVinci platform.
964 select ARCH_REQUIRE_GPIOLIB
965 select ARCH_HAS_CPUFREQ
967 select GENERIC_CLOCKEVENTS
968 select ARCH_HAS_HOLES_MEMORYMODEL
970 Support for TI's OMAP platform (OMAP1/2/3/4).
975 select ARCH_REQUIRE_GPIOLIB
978 select GENERIC_CLOCKEVENTS
981 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
984 bool "VIA/WonderMedia 85xx"
987 select ARCH_HAS_CPUFREQ
988 select GENERIC_CLOCKEVENTS
989 select ARCH_REQUIRE_GPIOLIB
992 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
995 bool "Xilinx Zynq ARM Cortex A9 Platform"
997 select GENERIC_CLOCKEVENTS
1002 select MIGHT_HAVE_CACHE_L2X0
1005 Support for Xilinx Zynq ARM Cortex A9 Platform
1009 # This is sorted alphabetically by mach-* pathname. However, plat-*
1010 # Kconfigs may be included either alphabetically (according to the
1011 # plat- suffix) or along side the corresponding mach-* source.
1013 source "arch/arm/mach-at91/Kconfig"
1015 source "arch/arm/mach-bcmring/Kconfig"
1017 source "arch/arm/mach-clps711x/Kconfig"
1019 source "arch/arm/mach-cns3xxx/Kconfig"
1021 source "arch/arm/mach-davinci/Kconfig"
1023 source "arch/arm/mach-dove/Kconfig"
1025 source "arch/arm/mach-ep93xx/Kconfig"
1027 source "arch/arm/mach-footbridge/Kconfig"
1029 source "arch/arm/mach-gemini/Kconfig"
1031 source "arch/arm/mach-h720x/Kconfig"
1033 source "arch/arm/mach-integrator/Kconfig"
1035 source "arch/arm/mach-iop32x/Kconfig"
1037 source "arch/arm/mach-iop33x/Kconfig"
1039 source "arch/arm/mach-iop13xx/Kconfig"
1041 source "arch/arm/mach-ixp4xx/Kconfig"
1043 source "arch/arm/mach-ixp2000/Kconfig"
1045 source "arch/arm/mach-ixp23xx/Kconfig"
1047 source "arch/arm/mach-kirkwood/Kconfig"
1049 source "arch/arm/mach-ks8695/Kconfig"
1051 source "arch/arm/mach-lpc32xx/Kconfig"
1053 source "arch/arm/mach-msm/Kconfig"
1055 source "arch/arm/mach-mv78xx0/Kconfig"
1057 source "arch/arm/plat-mxc/Kconfig"
1059 source "arch/arm/mach-mxs/Kconfig"
1061 source "arch/arm/mach-netx/Kconfig"
1063 source "arch/arm/mach-nomadik/Kconfig"
1064 source "arch/arm/plat-nomadik/Kconfig"
1066 source "arch/arm/plat-omap/Kconfig"
1068 source "arch/arm/mach-omap1/Kconfig"
1070 source "arch/arm/mach-omap2/Kconfig"
1072 source "arch/arm/mach-orion5x/Kconfig"
1074 source "arch/arm/mach-pxa/Kconfig"
1075 source "arch/arm/plat-pxa/Kconfig"
1077 source "arch/arm/mach-mmp/Kconfig"
1079 source "arch/arm/mach-realview/Kconfig"
1081 source "arch/arm/mach-sa1100/Kconfig"
1083 source "arch/arm/plat-samsung/Kconfig"
1084 source "arch/arm/plat-s3c24xx/Kconfig"
1085 source "arch/arm/plat-s5p/Kconfig"
1087 source "arch/arm/plat-spear/Kconfig"
1089 source "arch/arm/mach-s3c24xx/Kconfig"
1091 source "arch/arm/mach-s3c2412/Kconfig"
1092 source "arch/arm/mach-s3c2440/Kconfig"
1096 source "arch/arm/mach-s3c64xx/Kconfig"
1099 source "arch/arm/mach-s5p64x0/Kconfig"
1101 source "arch/arm/mach-s5pc100/Kconfig"
1103 source "arch/arm/mach-s5pv210/Kconfig"
1105 source "arch/arm/mach-exynos/Kconfig"
1107 source "arch/arm/mach-shmobile/Kconfig"
1109 source "arch/arm/mach-tegra/Kconfig"
1111 source "arch/arm/mach-u300/Kconfig"
1113 source "arch/arm/mach-ux500/Kconfig"
1115 source "arch/arm/mach-versatile/Kconfig"
1117 source "arch/arm/mach-vexpress/Kconfig"
1118 source "arch/arm/plat-versatile/Kconfig"
1120 source "arch/arm/mach-vt8500/Kconfig"
1122 source "arch/arm/mach-w90x900/Kconfig"
1124 # Definitions to make life easier
1130 select GENERIC_CLOCKEVENTS
1135 select GENERIC_IRQ_CHIP
1140 config PLAT_VERSATILE
1143 config ARM_TIMER_SP804
1146 select HAVE_SCHED_CLOCK
1148 source arch/arm/mm/Kconfig
1152 default 16 if ARCH_EP93XX
1156 bool "Enable iWMMXt support"
1157 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1158 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1160 Enable support for iWMMXt context switching at run time if
1161 running on a CPU that supports it.
1165 depends on CPU_XSCALE
1169 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1170 (!ARCH_OMAP3 || OMAP3_EMU)
1174 config MULTI_IRQ_HANDLER
1177 Allow each machine to specify it's own IRQ handler at run time.
1180 source "arch/arm/Kconfig-nommu"
1183 config ARM_ERRATA_411920
1184 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1185 depends on CPU_V6 || CPU_V6K
1187 Invalidation of the Instruction Cache operation can
1188 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1189 It does not affect the MPCore. This option enables the ARM Ltd.
1190 recommended workaround.
1192 config ARM_ERRATA_430973
1193 bool "ARM errata: Stale prediction on replaced interworking branch"
1196 This option enables the workaround for the 430973 Cortex-A8
1197 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1198 interworking branch is replaced with another code sequence at the
1199 same virtual address, whether due to self-modifying code or virtual
1200 to physical address re-mapping, Cortex-A8 does not recover from the
1201 stale interworking branch prediction. This results in Cortex-A8
1202 executing the new code sequence in the incorrect ARM or Thumb state.
1203 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1204 and also flushes the branch target cache at every context switch.
1205 Note that setting specific bits in the ACTLR register may not be
1206 available in non-secure mode.
1208 config ARM_ERRATA_458693
1209 bool "ARM errata: Processor deadlock when a false hazard is created"
1212 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1213 erratum. For very specific sequences of memory operations, it is
1214 possible for a hazard condition intended for a cache line to instead
1215 be incorrectly associated with a different cache line. This false
1216 hazard might then cause a processor deadlock. The workaround enables
1217 the L1 caching of the NEON accesses and disables the PLD instruction
1218 in the ACTLR register. Note that setting specific bits in the ACTLR
1219 register may not be available in non-secure mode.
1221 config ARM_ERRATA_460075
1222 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1225 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1226 erratum. Any asynchronous access to the L2 cache may encounter a
1227 situation in which recent store transactions to the L2 cache are lost
1228 and overwritten with stale memory contents from external memory. The
1229 workaround disables the write-allocate mode for the L2 cache via the
1230 ACTLR register. Note that setting specific bits in the ACTLR register
1231 may not be available in non-secure mode.
1233 config ARM_ERRATA_742230
1234 bool "ARM errata: DMB operation may be faulty"
1235 depends on CPU_V7 && SMP
1237 This option enables the workaround for the 742230 Cortex-A9
1238 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1239 between two write operations may not ensure the correct visibility
1240 ordering of the two writes. This workaround sets a specific bit in
1241 the diagnostic register of the Cortex-A9 which causes the DMB
1242 instruction to behave as a DSB, ensuring the correct behaviour of
1245 config ARM_ERRATA_742231
1246 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1247 depends on CPU_V7 && SMP
1249 This option enables the workaround for the 742231 Cortex-A9
1250 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1251 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1252 accessing some data located in the same cache line, may get corrupted
1253 data due to bad handling of the address hazard when the line gets
1254 replaced from one of the CPUs at the same time as another CPU is
1255 accessing it. This workaround sets specific bits in the diagnostic
1256 register of the Cortex-A9 which reduces the linefill issuing
1257 capabilities of the processor.
1259 config PL310_ERRATA_588369
1260 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1261 depends on CACHE_L2X0
1263 The PL310 L2 cache controller implements three types of Clean &
1264 Invalidate maintenance operations: by Physical Address
1265 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1266 They are architecturally defined to behave as the execution of a
1267 clean operation followed immediately by an invalidate operation,
1268 both performing to the same memory location. This functionality
1269 is not correctly implemented in PL310 as clean lines are not
1270 invalidated as a result of these operations.
1272 config ARM_ERRATA_720789
1273 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1276 This option enables the workaround for the 720789 Cortex-A9 (prior to
1277 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1278 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1279 As a consequence of this erratum, some TLB entries which should be
1280 invalidated are not, resulting in an incoherency in the system page
1281 tables. The workaround changes the TLB flushing routines to invalidate
1282 entries regardless of the ASID.
1284 config PL310_ERRATA_727915
1285 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1286 depends on CACHE_L2X0
1288 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1289 operation (offset 0x7FC). This operation runs in background so that
1290 PL310 can handle normal accesses while it is in progress. Under very
1291 rare circumstances, due to this erratum, write data can be lost when
1292 PL310 treats a cacheable write transaction during a Clean &
1293 Invalidate by Way operation.
1295 config ARM_ERRATA_743622
1296 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1299 This option enables the workaround for the 743622 Cortex-A9
1300 (r2p*) erratum. Under very rare conditions, a faulty
1301 optimisation in the Cortex-A9 Store Buffer may lead to data
1302 corruption. This workaround sets a specific bit in the diagnostic
1303 register of the Cortex-A9 which disables the Store Buffer
1304 optimisation, preventing the defect from occurring. This has no
1305 visible impact on the overall performance or power consumption of the
1308 config ARM_ERRATA_751472
1309 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1312 This option enables the workaround for the 751472 Cortex-A9 (prior
1313 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1314 completion of a following broadcasted operation if the second
1315 operation is received by a CPU before the ICIALLUIS has completed,
1316 potentially leading to corrupted entries in the cache or TLB.
1318 config PL310_ERRATA_753970
1319 bool "PL310 errata: cache sync operation may be faulty"
1320 depends on CACHE_PL310
1322 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1324 Under some condition the effect of cache sync operation on
1325 the store buffer still remains when the operation completes.
1326 This means that the store buffer is always asked to drain and
1327 this prevents it from merging any further writes. The workaround
1328 is to replace the normal offset of cache sync operation (0x730)
1329 by another offset targeting an unmapped PL310 register 0x740.
1330 This has the same effect as the cache sync operation: store buffer
1331 drain and waiting for all buffers empty.
1333 config ARM_ERRATA_754322
1334 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1337 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1338 r3p*) erratum. A speculative memory access may cause a page table walk
1339 which starts prior to an ASID switch but completes afterwards. This
1340 can populate the micro-TLB with a stale entry which may be hit with
1341 the new ASID. This workaround places two dsb instructions in the mm
1342 switching code so that no page table walks can cross the ASID switch.
1344 config ARM_ERRATA_754327
1345 bool "ARM errata: no automatic Store Buffer drain"
1346 depends on CPU_V7 && SMP
1348 This option enables the workaround for the 754327 Cortex-A9 (prior to
1349 r2p0) erratum. The Store Buffer does not have any automatic draining
1350 mechanism and therefore a livelock may occur if an external agent
1351 continuously polls a memory location waiting to observe an update.
1352 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1353 written polling loops from denying visibility of updates to memory.
1355 config ARM_ERRATA_364296
1356 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1357 depends on CPU_V6 && !SMP
1359 This options enables the workaround for the 364296 ARM1136
1360 r0p2 erratum (possible cache data corruption with
1361 hit-under-miss enabled). It sets the undocumented bit 31 in
1362 the auxiliary control register and the FI bit in the control
1363 register, thus disabling hit-under-miss without putting the
1364 processor into full low interrupt latency mode. ARM11MPCore
1367 config ARM_ERRATA_764369
1368 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1369 depends on CPU_V7 && SMP
1371 This option enables the workaround for erratum 764369
1372 affecting Cortex-A9 MPCore with two or more processors (all
1373 current revisions). Under certain timing circumstances, a data
1374 cache line maintenance operation by MVA targeting an Inner
1375 Shareable memory region may fail to proceed up to either the
1376 Point of Coherency or to the Point of Unification of the
1377 system. This workaround adds a DSB instruction before the
1378 relevant cache maintenance functions and sets a specific bit
1379 in the diagnostic control register of the SCU.
1381 config PL310_ERRATA_769419
1382 bool "PL310 errata: no automatic Store Buffer drain"
1383 depends on CACHE_L2X0
1385 On revisions of the PL310 prior to r3p2, the Store Buffer does
1386 not automatically drain. This can cause normal, non-cacheable
1387 writes to be retained when the memory system is idle, leading
1388 to suboptimal I/O performance for drivers using coherent DMA.
1389 This option adds a write barrier to the cpu_idle loop so that,
1390 on systems with an outer cache, the store buffer is drained
1395 source "arch/arm/common/Kconfig"
1405 Find out whether you have ISA slots on your motherboard. ISA is the
1406 name of a bus system, i.e. the way the CPU talks to the other stuff
1407 inside your box. Other bus systems are PCI, EISA, MicroChannel
1408 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1409 newer boards don't support it. If you have ISA, say Y, otherwise N.
1411 # Select ISA DMA controller support
1416 # Select ISA DMA interface
1421 bool "PCI support" if MIGHT_HAVE_PCI
1423 Find out whether you have a PCI motherboard. PCI is the name of a
1424 bus system, i.e. the way the CPU talks to the other stuff inside
1425 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1426 VESA. If you have PCI, say Y, otherwise N.
1432 config PCI_NANOENGINE
1433 bool "BSE nanoEngine PCI support"
1434 depends on SA1100_NANOENGINE
1436 Enable PCI on the BSE nanoEngine board.
1441 # Select the host bridge type
1442 config PCI_HOST_VIA82C505
1444 depends on PCI && ARCH_SHARK
1447 config PCI_HOST_ITE8152
1449 depends on PCI && MACH_ARMCORE
1453 source "drivers/pci/Kconfig"
1455 source "drivers/pcmcia/Kconfig"
1459 menu "Kernel Features"
1461 source "kernel/time/Kconfig"
1466 This option should be selected by machines which have an SMP-
1469 The only effect of this option is to make the SMP-related
1470 options available to the user for configuration.
1473 bool "Symmetric Multi-Processing"
1474 depends on CPU_V6K || CPU_V7
1475 depends on GENERIC_CLOCKEVENTS
1478 select USE_GENERIC_SMP_HELPERS
1479 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1481 This enables support for systems with more than one CPU. If you have
1482 a system with only one CPU, like most personal computers, say N. If
1483 you have a system with more than one CPU, say Y.
1485 If you say N here, the kernel will run on single and multiprocessor
1486 machines, but will use only one CPU of a multiprocessor machine. If
1487 you say Y here, the kernel will run on many, but not all, single
1488 processor machines. On a single processor machine, the kernel will
1489 run faster if you say N here.
1491 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1492 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1493 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1495 If you don't know what to do here, say N.
1498 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1499 depends on EXPERIMENTAL
1500 depends on SMP && !XIP_KERNEL
1503 SMP kernels contain instructions which fail on non-SMP processors.
1504 Enabling this option allows the kernel to modify itself to make
1505 these instructions safe. Disabling it allows about 1K of space
1508 If you don't know what to do here, say Y.
1510 config ARM_CPU_TOPOLOGY
1511 bool "Support cpu topology definition"
1512 depends on SMP && CPU_V7
1515 Support ARM cpu topology definition. The MPIDR register defines
1516 affinity between processors which is then used to describe the cpu
1517 topology of an ARM System.
1520 bool "Multi-core scheduler support"
1521 depends on ARM_CPU_TOPOLOGY
1523 Multi-core scheduler support improves the CPU scheduler's decision
1524 making when dealing with multi-core CPU chips at a cost of slightly
1525 increased overhead in some places. If unsure say N here.
1528 bool "SMT scheduler support"
1529 depends on ARM_CPU_TOPOLOGY
1531 Improves the CPU scheduler's decision making when dealing with
1532 MultiThreading at a cost of slightly increased overhead in some
1533 places. If unsure say N here.
1538 This option enables support for the ARM system coherency unit
1545 This options enables support for the ARM timer and watchdog unit
1548 prompt "Memory split"
1551 Select the desired split between kernel and user memory.
1553 If you are not absolutely sure what you are doing, leave this
1557 bool "3G/1G user/kernel split"
1559 bool "2G/2G user/kernel split"
1561 bool "1G/3G user/kernel split"
1566 default 0x40000000 if VMSPLIT_1G
1567 default 0x80000000 if VMSPLIT_2G
1571 int "Maximum number of CPUs (2-32)"
1577 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1578 depends on SMP && HOTPLUG && EXPERIMENTAL
1580 Say Y here to experiment with turning CPUs off and on. CPUs
1581 can be controlled through /sys/devices/system/cpu.
1584 bool "Use local timer interrupts"
1587 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1589 Enable support for local timers on SMP platforms, rather then the
1590 legacy IPI broadcast method. Local timers allows the system
1591 accounting to be spread across the timer interval, preventing a
1592 "thundering herd" at every timer tick.
1596 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1597 default 355 if ARCH_U8500
1598 default 264 if MACH_H4700
1601 Maximum number of GPIOs in the system.
1603 If unsure, leave the default value.
1605 source kernel/Kconfig.preempt
1609 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1610 ARCH_S5PV210 || ARCH_EXYNOS4
1611 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1612 default AT91_TIMER_HZ if ARCH_AT91
1613 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1616 config THUMB2_KERNEL
1617 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1618 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1620 select ARM_ASM_UNIFIED
1623 By enabling this option, the kernel will be compiled in
1624 Thumb-2 mode. A compiler/assembler that understand the unified
1625 ARM-Thumb syntax is needed.
1629 config THUMB2_AVOID_R_ARM_THM_JUMP11
1630 bool "Work around buggy Thumb-2 short branch relocations in gas"
1631 depends on THUMB2_KERNEL && MODULES
1634 Various binutils versions can resolve Thumb-2 branches to
1635 locally-defined, preemptible global symbols as short-range "b.n"
1636 branch instructions.
1638 This is a problem, because there's no guarantee the final
1639 destination of the symbol, or any candidate locations for a
1640 trampoline, are within range of the branch. For this reason, the
1641 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1642 relocation in modules at all, and it makes little sense to add
1645 The symptom is that the kernel fails with an "unsupported
1646 relocation" error when loading some modules.
1648 Until fixed tools are available, passing
1649 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1650 code which hits this problem, at the cost of a bit of extra runtime
1651 stack usage in some cases.
1653 The problem is described in more detail at:
1654 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1656 Only Thumb-2 kernels are affected.
1658 Unless you are sure your tools don't have this problem, say Y.
1660 config ARM_ASM_UNIFIED
1664 bool "Use the ARM EABI to compile the kernel"
1666 This option allows for the kernel to be compiled using the latest
1667 ARM ABI (aka EABI). This is only useful if you are using a user
1668 space environment that is also compiled with EABI.
1670 Since there are major incompatibilities between the legacy ABI and
1671 EABI, especially with regard to structure member alignment, this
1672 option also changes the kernel syscall calling convention to
1673 disambiguate both ABIs and allow for backward compatibility support
1674 (selected with CONFIG_OABI_COMPAT).
1676 To use this you need GCC version 4.0.0 or later.
1679 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1680 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1683 This option preserves the old syscall interface along with the
1684 new (ARM EABI) one. It also provides a compatibility layer to
1685 intercept syscalls that have structure arguments which layout
1686 in memory differs between the legacy ABI and the new ARM EABI
1687 (only for non "thumb" binaries). This option adds a tiny
1688 overhead to all syscalls and produces a slightly larger kernel.
1689 If you know you'll be using only pure EABI user space then you
1690 can say N here. If this option is not selected and you attempt
1691 to execute a legacy ABI binary then the result will be
1692 UNPREDICTABLE (in fact it can be predicted that it won't work
1693 at all). If in doubt say Y.
1695 config ARCH_HAS_HOLES_MEMORYMODEL
1698 config ARCH_SPARSEMEM_ENABLE
1701 config ARCH_SPARSEMEM_DEFAULT
1702 def_bool ARCH_SPARSEMEM_ENABLE
1704 config ARCH_SELECT_MEMORY_MODEL
1705 def_bool ARCH_SPARSEMEM_ENABLE
1707 config HAVE_ARCH_PFN_VALID
1708 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1711 bool "High Memory Support"
1714 The address space of ARM processors is only 4 Gigabytes large
1715 and it has to accommodate user address space, kernel address
1716 space as well as some memory mapped IO. That means that, if you
1717 have a large amount of physical memory and/or IO, not all of the
1718 memory can be "permanently mapped" by the kernel. The physical
1719 memory that is not permanently mapped is called "high memory".
1721 Depending on the selected kernel/user memory split, minimum
1722 vmalloc space and actual amount of RAM, you may not need this
1723 option which should result in a slightly faster kernel.
1728 bool "Allocate 2nd-level pagetables from highmem"
1731 config HW_PERF_EVENTS
1732 bool "Enable hardware performance counter support for perf events"
1733 depends on PERF_EVENTS && CPU_HAS_PMU
1736 Enable hardware performance counter support for perf events. If
1737 disabled, perf events will use software events only.
1741 config FORCE_MAX_ZONEORDER
1742 int "Maximum zone order" if ARCH_SHMOBILE
1743 range 11 64 if ARCH_SHMOBILE
1744 default "9" if SA1111
1747 The kernel memory allocator divides physically contiguous memory
1748 blocks into "zones", where each zone is a power of two number of
1749 pages. This option selects the largest power of two that the kernel
1750 keeps in the memory allocator. If you need to allocate very large
1751 blocks of physically contiguous memory, then you may need to
1752 increase this value.
1754 This config option is actually maximum order plus one. For example,
1755 a value of 11 means that the largest free memory block is 2^10 pages.
1758 bool "Timer and CPU usage LEDs"
1759 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1760 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1761 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1762 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1763 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1764 ARCH_AT91 || ARCH_DAVINCI || \
1765 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1767 If you say Y here, the LEDs on your machine will be used
1768 to provide useful information about your current system status.
1770 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1771 be able to select which LEDs are active using the options below. If
1772 you are compiling a kernel for the EBSA-110 or the LART however, the
1773 red LED will simply flash regularly to indicate that the system is
1774 still functional. It is safe to say Y here if you have a CATS
1775 system, but the driver will do nothing.
1778 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1779 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1780 || MACH_OMAP_PERSEUS2
1782 depends on !GENERIC_CLOCKEVENTS
1783 default y if ARCH_EBSA110
1785 If you say Y here, one of the system LEDs (the green one on the
1786 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1787 will flash regularly to indicate that the system is still
1788 operational. This is mainly useful to kernel hackers who are
1789 debugging unstable kernels.
1791 The LART uses the same LED for both Timer LED and CPU usage LED
1792 functions. You may choose to use both, but the Timer LED function
1793 will overrule the CPU usage LED.
1796 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1798 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1799 || MACH_OMAP_PERSEUS2
1802 If you say Y here, the red LED will be used to give a good real
1803 time indication of CPU usage, by lighting whenever the idle task
1804 is not currently executing.
1806 The LART uses the same LED for both Timer LED and CPU usage LED
1807 functions. You may choose to use both, but the Timer LED function
1808 will overrule the CPU usage LED.
1810 config ALIGNMENT_TRAP
1812 depends on CPU_CP15_MMU
1813 default y if !ARCH_EBSA110
1814 select HAVE_PROC_CPU if PROC_FS
1816 ARM processors cannot fetch/store information which is not
1817 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1818 address divisible by 4. On 32-bit ARM processors, these non-aligned
1819 fetch/store instructions will be emulated in software if you say
1820 here, which has a severe performance impact. This is necessary for
1821 correct operation of some network protocols. With an IP-only
1822 configuration it is safe to say N, otherwise say Y.
1824 config UACCESS_WITH_MEMCPY
1825 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1826 depends on MMU && EXPERIMENTAL
1827 default y if CPU_FEROCEON
1829 Implement faster copy_to_user and clear_user methods for CPU
1830 cores where a 8-word STM instruction give significantly higher
1831 memory write throughput than a sequence of individual 32bit stores.
1833 A possible side effect is a slight increase in scheduling latency
1834 between threads sharing the same address space if they invoke
1835 such copy operations with large buffers.
1837 However, if the CPU data cache is using a write-allocate mode,
1838 this option is unlikely to provide any performance gain.
1842 prompt "Enable seccomp to safely compute untrusted bytecode"
1844 This kernel feature is useful for number crunching applications
1845 that may need to compute untrusted bytecode during their
1846 execution. By using pipes or other transports made available to
1847 the process as file descriptors supporting the read/write
1848 syscalls, it's possible to isolate those applications in
1849 their own address space using seccomp. Once seccomp is
1850 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1851 and the task is only allowed to execute a few safe syscalls
1852 defined by each seccomp mode.
1854 config CC_STACKPROTECTOR
1855 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1856 depends on EXPERIMENTAL
1858 This option turns on the -fstack-protector GCC feature. This
1859 feature puts, at the beginning of functions, a canary value on
1860 the stack just before the return address, and validates
1861 the value just before actually returning. Stack based buffer
1862 overflows (that need to overwrite this return address) now also
1863 overwrite the canary, which gets detected and the attack is then
1864 neutralized via a kernel panic.
1865 This feature requires gcc version 4.2 or above.
1867 config DEPRECATED_PARAM_STRUCT
1868 bool "Provide old way to pass kernel parameters"
1870 This was deprecated in 2001 and announced to live on for 5 years.
1871 Some old boot loaders still use this way.
1878 bool "Flattened Device Tree support"
1880 select OF_EARLY_FLATTREE
1883 Include support for flattened device tree machine descriptions.
1885 # Compressed boot loader in ROM. Yes, we really want to ask about
1886 # TEXT and BSS so we preserve their values in the config files.
1887 config ZBOOT_ROM_TEXT
1888 hex "Compressed ROM boot loader base address"
1891 The physical address at which the ROM-able zImage is to be
1892 placed in the target. Platforms which normally make use of
1893 ROM-able zImage formats normally set this to a suitable
1894 value in their defconfig file.
1896 If ZBOOT_ROM is not enabled, this has no effect.
1898 config ZBOOT_ROM_BSS
1899 hex "Compressed ROM boot loader BSS address"
1902 The base address of an area of read/write memory in the target
1903 for the ROM-able zImage which must be available while the
1904 decompressor is running. It must be large enough to hold the
1905 entire decompressed kernel plus an additional 128 KiB.
1906 Platforms which normally make use of ROM-able zImage formats
1907 normally set this to a suitable value in their defconfig file.
1909 If ZBOOT_ROM is not enabled, this has no effect.
1912 bool "Compressed boot loader in ROM/flash"
1913 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1915 Say Y here if you intend to execute your compressed kernel image
1916 (zImage) directly from ROM or flash. If unsure, say N.
1919 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1920 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1921 default ZBOOT_ROM_NONE
1923 Include experimental SD/MMC loading code in the ROM-able zImage.
1924 With this enabled it is possible to write the the ROM-able zImage
1925 kernel image to an MMC or SD card and boot the kernel straight
1926 from the reset vector. At reset the processor Mask ROM will load
1927 the first part of the the ROM-able zImage which in turn loads the
1928 rest the kernel image to RAM.
1930 config ZBOOT_ROM_NONE
1931 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1933 Do not load image from SD or MMC
1935 config ZBOOT_ROM_MMCIF
1936 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1938 Load image from MMCIF hardware block.
1940 config ZBOOT_ROM_SH_MOBILE_SDHI
1941 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1943 Load image from SDHI hardware block
1947 config ARM_APPENDED_DTB
1948 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1949 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1951 With this option, the boot code will look for a device tree binary
1952 (DTB) appended to zImage
1953 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1955 This is meant as a backward compatibility convenience for those
1956 systems with a bootloader that can't be upgraded to accommodate
1957 the documented boot protocol using a device tree.
1959 Beware that there is very little in terms of protection against
1960 this option being confused by leftover garbage in memory that might
1961 look like a DTB header after a reboot if no actual DTB is appended
1962 to zImage. Do not leave this option active in a production kernel
1963 if you don't intend to always append a DTB. Proper passing of the
1964 location into r2 of a bootloader provided DTB is always preferable
1967 config ARM_ATAG_DTB_COMPAT
1968 bool "Supplement the appended DTB with traditional ATAG information"
1969 depends on ARM_APPENDED_DTB
1971 Some old bootloaders can't be updated to a DTB capable one, yet
1972 they provide ATAGs with memory configuration, the ramdisk address,
1973 the kernel cmdline string, etc. Such information is dynamically
1974 provided by the bootloader and can't always be stored in a static
1975 DTB. To allow a device tree enabled kernel to be used with such
1976 bootloaders, this option allows zImage to extract the information
1977 from the ATAG list and store it at run time into the appended DTB.
1980 string "Default kernel command string"
1983 On some architectures (EBSA110 and CATS), there is currently no way
1984 for the boot loader to pass arguments to the kernel. For these
1985 architectures, you should supply some command-line options at build
1986 time by entering them here. As a minimum, you should specify the
1987 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1990 prompt "Kernel command line type" if CMDLINE != ""
1991 default CMDLINE_FROM_BOOTLOADER
1993 config CMDLINE_FROM_BOOTLOADER
1994 bool "Use bootloader kernel arguments if available"
1996 Uses the command-line options passed by the boot loader. If
1997 the boot loader doesn't provide any, the default kernel command
1998 string provided in CMDLINE will be used.
2000 config CMDLINE_EXTEND
2001 bool "Extend bootloader kernel arguments"
2003 The command-line arguments provided by the boot loader will be
2004 appended to the default kernel command string.
2006 config CMDLINE_FORCE
2007 bool "Always use the default kernel command string"
2009 Always use the default kernel command string, even if the boot
2010 loader passes other arguments to the kernel.
2011 This is useful if you cannot or don't want to change the
2012 command-line options your boot loader passes to the kernel.
2016 bool "Kernel Execute-In-Place from ROM"
2017 depends on !ZBOOT_ROM && !ARM_LPAE
2019 Execute-In-Place allows the kernel to run from non-volatile storage
2020 directly addressable by the CPU, such as NOR flash. This saves RAM
2021 space since the text section of the kernel is not loaded from flash
2022 to RAM. Read-write sections, such as the data section and stack,
2023 are still copied to RAM. The XIP kernel is not compressed since
2024 it has to run directly from flash, so it will take more space to
2025 store it. The flash address used to link the kernel object files,
2026 and for storing it, is configuration dependent. Therefore, if you
2027 say Y here, you must know the proper physical address where to
2028 store the kernel image depending on your own flash memory usage.
2030 Also note that the make target becomes "make xipImage" rather than
2031 "make zImage" or "make Image". The final kernel binary to put in
2032 ROM memory will be arch/arm/boot/xipImage.
2036 config XIP_PHYS_ADDR
2037 hex "XIP Kernel Physical Location"
2038 depends on XIP_KERNEL
2039 default "0x00080000"
2041 This is the physical address in your flash memory the kernel will
2042 be linked for and stored to. This address is dependent on your
2046 bool "Kexec system call (EXPERIMENTAL)"
2047 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2049 kexec is a system call that implements the ability to shutdown your
2050 current kernel, and to start another kernel. It is like a reboot
2051 but it is independent of the system firmware. And like a reboot
2052 you can start any kernel with it, not just Linux.
2054 It is an ongoing process to be certain the hardware in a machine
2055 is properly shutdown, so do not be surprised if this code does not
2056 initially work for you. It may help to enable device hotplugging
2060 bool "Export atags in procfs"
2064 Should the atags used to boot the kernel be exported in an "atags"
2065 file in procfs. Useful with kexec.
2068 bool "Build kdump crash kernel (EXPERIMENTAL)"
2069 depends on EXPERIMENTAL
2071 Generate crash dump after being started by kexec. This should
2072 be normally only set in special crash dump kernels which are
2073 loaded in the main kernel with kexec-tools into a specially
2074 reserved region and then later executed after a crash by
2075 kdump/kexec. The crash dump kernel must be compiled to a
2076 memory address not used by the main kernel
2078 For more details see Documentation/kdump/kdump.txt
2080 config AUTO_ZRELADDR
2081 bool "Auto calculation of the decompressed kernel image address"
2082 depends on !ZBOOT_ROM && !ARCH_U300
2084 ZRELADDR is the physical address where the decompressed kernel
2085 image will be placed. If AUTO_ZRELADDR is selected, the address
2086 will be determined at run-time by masking the current IP with
2087 0xf8000000. This assumes the zImage being placed in the first 128MB
2088 from start of memory.
2092 menu "CPU Power Management"
2096 source "drivers/cpufreq/Kconfig"
2099 tristate "CPUfreq driver for i.MX CPUs"
2100 depends on ARCH_MXC && CPU_FREQ
2102 This enables the CPUfreq driver for i.MX CPUs.
2104 config CPU_FREQ_SA1100
2107 config CPU_FREQ_SA1110
2110 config CPU_FREQ_INTEGRATOR
2111 tristate "CPUfreq driver for ARM Integrator CPUs"
2112 depends on ARCH_INTEGRATOR && CPU_FREQ
2115 This enables the CPUfreq driver for ARM Integrator CPUs.
2117 For details, take a look at <file:Documentation/cpu-freq>.
2123 depends on CPU_FREQ && ARCH_PXA && PXA25x
2125 select CPU_FREQ_TABLE
2126 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2131 Internal configuration node for common cpufreq on Samsung SoC
2133 config CPU_FREQ_S3C24XX
2134 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2135 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2138 This enables the CPUfreq driver for the Samsung S3C24XX family
2141 For details, take a look at <file:Documentation/cpu-freq>.
2145 config CPU_FREQ_S3C24XX_PLL
2146 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2147 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2149 Compile in support for changing the PLL frequency from the
2150 S3C24XX series CPUfreq driver. The PLL takes time to settle
2151 after a frequency change, so by default it is not enabled.
2153 This also means that the PLL tables for the selected CPU(s) will
2154 be built which may increase the size of the kernel image.
2156 config CPU_FREQ_S3C24XX_DEBUG
2157 bool "Debug CPUfreq Samsung driver core"
2158 depends on CPU_FREQ_S3C24XX
2160 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2162 config CPU_FREQ_S3C24XX_IODEBUG
2163 bool "Debug CPUfreq Samsung driver IO timing"
2164 depends on CPU_FREQ_S3C24XX
2166 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2168 config CPU_FREQ_S3C24XX_DEBUGFS
2169 bool "Export debugfs for CPUFreq"
2170 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2172 Export status information via debugfs.
2176 source "drivers/cpuidle/Kconfig"
2180 menu "Floating point emulation"
2182 comment "At least one emulation must be selected"
2185 bool "NWFPE math emulation"
2186 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2188 Say Y to include the NWFPE floating point emulator in the kernel.
2189 This is necessary to run most binaries. Linux does not currently
2190 support floating point hardware so you need to say Y here even if
2191 your machine has an FPA or floating point co-processor podule.
2193 You may say N here if you are going to load the Acorn FPEmulator
2194 early in the bootup.
2197 bool "Support extended precision"
2198 depends on FPE_NWFPE
2200 Say Y to include 80-bit support in the kernel floating-point
2201 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2202 Note that gcc does not generate 80-bit operations by default,
2203 so in most cases this option only enlarges the size of the
2204 floating point emulator without any good reason.
2206 You almost surely want to say N here.
2209 bool "FastFPE math emulation (EXPERIMENTAL)"
2210 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2212 Say Y here to include the FAST floating point emulator in the kernel.
2213 This is an experimental much faster emulator which now also has full
2214 precision for the mantissa. It does not support any exceptions.
2215 It is very simple, and approximately 3-6 times faster than NWFPE.
2217 It should be sufficient for most programs. It may be not suitable
2218 for scientific calculations, but you have to check this for yourself.
2219 If you do not feel you need a faster FP emulation you should better
2223 bool "VFP-format floating point maths"
2224 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2226 Say Y to include VFP support code in the kernel. This is needed
2227 if your hardware includes a VFP unit.
2229 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2230 release notes and additional status information.
2232 Say N if your target does not have VFP hardware.
2240 bool "Advanced SIMD (NEON) Extension support"
2241 depends on VFPv3 && CPU_V7
2243 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2248 menu "Userspace binary formats"
2250 source "fs/Kconfig.binfmt"
2253 tristate "RISC OS personality"
2256 Say Y here to include the kernel code necessary if you want to run
2257 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2258 experimental; if this sounds frightening, say N and sleep in peace.
2259 You can also say M here to compile this support as a module (which
2260 will be called arthur).
2264 menu "Power management options"
2266 source "kernel/power/Kconfig"
2268 config ARCH_SUSPEND_POSSIBLE
2269 depends on !ARCH_S5PC100
2270 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2271 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2274 config ARM_CPU_SUSPEND
2279 source "net/Kconfig"
2281 source "drivers/Kconfig"
2285 source "arch/arm/Kconfig.debug"
2287 source "security/Kconfig"
2289 source "crypto/Kconfig"
2291 source "lib/Kconfig"