4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_SUPPORTS_ATOMIC_RMW
8 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
9 select ARCH_HAS_GCOV_PROFILE_ALL
10 select ARCH_WANT_IPC_PARSE_VERSION
11 select BUILDTIME_EXTABLE_SORT if MMU
12 select CPU_PM if (SUSPEND || CPU_IDLE)
13 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
14 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
15 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
16 select GENERIC_IRQ_PROBE
17 select GENERIC_IRQ_SHOW
18 select GENERIC_PCI_IOMAP
19 select GENERIC_SMP_IDLE_THREAD
20 select GENERIC_IDLE_POLL_SETUP
21 select GENERIC_STRNCPY_FROM_USER
22 select GENERIC_STRNLEN_USER
23 select HARDIRQS_SW_RESEND
24 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
26 select HAVE_ARCH_SECCOMP_FILTER
27 select HAVE_ARCH_TRACEHOOK
29 select HAVE_C_RECORDMCOUNT
30 select HAVE_DEBUG_KMEMLEAK
31 select HAVE_DMA_API_DEBUG
33 select HAVE_DMA_CONTIGUOUS if MMU
34 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
35 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
36 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
37 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
38 select HAVE_GENERIC_DMA_COHERENT
39 select HAVE_GENERIC_HARDIRQS
40 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
41 select HAVE_IDE if PCI || ISA || PCMCIA
42 select HAVE_IRQ_TIME_ACCOUNTING
43 select HAVE_KERNEL_GZIP
44 select HAVE_KERNEL_LZMA
45 select HAVE_KERNEL_LZO
47 select HAVE_KPROBES if !XIP_KERNEL
48 select HAVE_KRETPROBES if (HAVE_KPROBES)
50 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
51 select HAVE_PERF_EVENTS
53 select HAVE_REGS_AND_STACK_ACCESS_API
54 select HAVE_SYSCALL_TRACEPOINTS
57 select PERF_USE_VMALLOC
59 select SYS_SUPPORTS_APM_EMULATION
60 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
61 select MODULES_USE_ELF_REL
62 select CLONE_BACKWARDS
63 select OLD_SIGSUSPEND3
65 select HAVE_CONTEXT_TRACKING
67 The ARM series is a line of low-power-consumption RISC chip designs
68 licensed by ARM Ltd and targeted at embedded applications and
69 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
70 manufactured, but legacy ARM-based PC hardware remains popular in
71 Europe. There is an ARM Linux project with a web page at
72 <http://www.arm.linux.org.uk/>.
74 config ARM_HAS_SG_CHAIN
77 config NEED_SG_DMA_LENGTH
80 config ARM_DMA_USE_IOMMU
82 select ARM_HAS_SG_CHAIN
83 select NEED_SG_DMA_LENGTH
87 config ARM_DMA_IOMMU_ALIGNMENT
88 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
92 DMA mapping framework by default aligns all buffers to the smallest
93 PAGE_SIZE order which is greater than or equal to the requested buffer
94 size. This works well for buffers up to a few hundreds kilobytes, but
95 for larger buffers it just a waste of address space. Drivers which has
96 relatively small addressing window (like 64Mib) might run out of
97 virtual space with just a few allocations.
99 With this parameter you can specify the maximum PAGE_SIZE order for
100 DMA IOMMU buffers. Larger buffers will be aligned only to this
101 specified order. The order is expressed as a power of two multiplied
109 config MIGHT_HAVE_PCI
112 config SYS_SUPPORTS_APM_EMULATION
117 select GENERIC_ALLOCATOR
128 The Extended Industry Standard Architecture (EISA) bus was
129 developed as an open alternative to the IBM MicroChannel bus.
131 The EISA bus provided some of the features of the IBM MicroChannel
132 bus while maintaining backward compatibility with cards made for
133 the older ISA bus. The EISA bus saw limited use between 1988 and
134 1995 when it was made obsolete by the PCI bus.
136 Say Y here if you are building a kernel for an EISA-based machine.
143 config STACKTRACE_SUPPORT
147 config HAVE_LATENCYTOP_SUPPORT
152 config LOCKDEP_SUPPORT
156 config TRACE_IRQFLAGS_SUPPORT
160 config RWSEM_GENERIC_SPINLOCK
164 config RWSEM_XCHGADD_ALGORITHM
167 config ARCH_HAS_ILOG2_U32
170 config ARCH_HAS_ILOG2_U64
173 config ARCH_HAS_CPUFREQ
176 Internal node to signify that the ARCH has CPUFREQ support
177 and that the relevant menu configurations are displayed for
180 config GENERIC_HWEIGHT
184 config GENERIC_CALIBRATE_DELAY
188 config ARCH_MAY_HAVE_PC_FDC
194 config NEED_DMA_MAP_STATE
197 config ARCH_HAS_DMA_SET_COHERENT_MASK
200 config GENERIC_ISA_DMA
206 config NEED_RET_TO_USER
214 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
215 default DRAM_BASE if REMAP_VECTORS_TO_RAM
218 The base address of exception vectors. This must be two pages
221 config ARM_PATCH_PHYS_VIRT
222 bool "Patch physical to virtual translations at runtime" if EMBEDDED
224 depends on !XIP_KERNEL && MMU
225 depends on !ARCH_REALVIEW || !SPARSEMEM
227 Patch phys-to-virt and virt-to-phys translation functions at
228 boot and module load time according to the position of the
229 kernel in system memory.
231 This can only be used with non-XIP MMU kernels where the base
232 of physical memory is at a 16MB boundary.
234 Only disable this option if you know that you do not require
235 this feature (eg, building a kernel for a single machine) and
236 you need to shrink the kernel to the minimal size.
238 config NEED_MACH_GPIO_H
241 Select this when mach/gpio.h is required to provide special
242 definitions for this platform. The need for mach/gpio.h should
243 be avoided when possible.
245 config NEED_MACH_IO_H
248 Select this when mach/io.h is required to provide special
249 definitions for this platform. The need for mach/io.h should
250 be avoided when possible.
252 config NEED_MACH_MEMORY_H
255 Select this when mach/memory.h is required to provide special
256 definitions for this platform. The need for mach/memory.h should
257 be avoided when possible.
260 hex "Physical address of main memory" if MMU
261 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
262 default DRAM_BASE if !MMU
264 Please provide the physical address corresponding to the
265 location of main memory in your system.
271 source "init/Kconfig"
273 source "kernel/Kconfig.freezer"
278 bool "MMU-based Paged Memory Management Support"
281 Select if you want MMU-based virtualised addressing space
282 support by paged memory management. If unsure, say 'Y'.
285 # The "ARM system type" choice list is ordered alphabetically by option
286 # text. Please add new entries in the option alphabetic order.
289 prompt "ARM system type"
290 default ARCH_VERSATILE if !MMU
291 default ARCH_MULTIPLATFORM if MMU
293 config ARCH_MULTIPLATFORM
294 bool "Allow multiple platforms to be selected"
296 select ARM_PATCH_PHYS_VIRT
299 select MULTI_IRQ_HANDLER
303 config ARCH_INTEGRATOR
304 bool "ARM Ltd. Integrator family"
305 select ARCH_HAS_CPUFREQ
308 select COMMON_CLK_VERSATILE
309 select GENERIC_CLOCKEVENTS
312 select MULTI_IRQ_HANDLER
313 select NEED_MACH_MEMORY_H
314 select PLAT_VERSATILE
316 select VERSATILE_FPGA_IRQ
318 Support for ARM's Integrator platform.
321 bool "ARM Ltd. RealView family"
322 select ARCH_WANT_OPTIONAL_GPIOLIB
324 select ARM_TIMER_SP804
326 select COMMON_CLK_VERSATILE
327 select GENERIC_CLOCKEVENTS
328 select GPIO_PL061 if GPIOLIB
330 select NEED_MACH_MEMORY_H
331 select PLAT_VERSATILE
332 select PLAT_VERSATILE_CLCD
334 This enables support for ARM Ltd RealView boards.
336 config ARCH_VERSATILE
337 bool "ARM Ltd. Versatile family"
338 select ARCH_WANT_OPTIONAL_GPIOLIB
340 select ARM_TIMER_SP804
343 select GENERIC_CLOCKEVENTS
344 select HAVE_MACH_CLKDEV
346 select PLAT_VERSATILE
347 select PLAT_VERSATILE_CLCD
348 select PLAT_VERSATILE_CLOCK
349 select VERSATILE_FPGA_IRQ
351 This enables support for ARM Ltd Versatile board.
355 select ARCH_REQUIRE_GPIOLIB
359 select NEED_MACH_GPIO_H
360 select NEED_MACH_IO_H if PCCARD
362 select PINCTRL_AT91 if USE_OF
364 This enables support for systems based on Atmel
365 AT91RM9200 and AT91SAM9* processors.
368 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
369 select ARCH_REQUIRE_GPIOLIB
374 select GENERIC_CLOCKEVENTS
375 select MULTI_IRQ_HANDLER
376 select NEED_MACH_MEMORY_H
379 Support for Cirrus Logic 711x/721x/731x based boards.
382 bool "Cortina Systems Gemini"
383 select ARCH_REQUIRE_GPIOLIB
384 select ARCH_USES_GETTIMEOFFSET
385 select NEED_MACH_GPIO_H
388 Support for the Cortina Systems Gemini family SoCs
392 select ARCH_USES_GETTIMEOFFSET
395 select NEED_MACH_IO_H
396 select NEED_MACH_MEMORY_H
399 This is an evaluation board for the StrongARM processor available
400 from Digital. It has limited hardware on-board, including an
401 Ethernet interface, two PCMCIA sockets, two serial ports and a
406 select ARCH_HAS_HOLES_MEMORYMODEL
407 select ARCH_REQUIRE_GPIOLIB
408 select ARCH_USES_GETTIMEOFFSET
413 select NEED_MACH_MEMORY_H
415 This enables support for the Cirrus EP93xx series of CPUs.
417 config ARCH_FOOTBRIDGE
421 select GENERIC_CLOCKEVENTS
423 select NEED_MACH_IO_H if !MMU
424 select NEED_MACH_MEMORY_H
426 Support for systems based on the DC21285 companion chip
427 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
430 bool "Hilscher NetX based"
434 select GENERIC_CLOCKEVENTS
436 This enables support for systems based on the Hilscher NetX Soc
441 select ARCH_SUPPORTS_MSI
443 select NEED_MACH_MEMORY_H
444 select NEED_RET_TO_USER
449 Support for Intel's IOP13XX (XScale) family of processors.
454 select ARCH_REQUIRE_GPIOLIB
456 select NEED_MACH_GPIO_H
457 select NEED_RET_TO_USER
461 Support for Intel's 80219 and IOP32X (XScale) family of
467 select ARCH_REQUIRE_GPIOLIB
469 select NEED_MACH_GPIO_H
470 select NEED_RET_TO_USER
474 Support for Intel's IOP33X (XScale) family of processors.
479 select ARCH_HAS_DMA_SET_COHERENT_MASK
480 select ARCH_SUPPORTS_BIG_ENDIAN
481 select ARCH_REQUIRE_GPIOLIB
484 select DMABOUNCE if PCI
485 select GENERIC_CLOCKEVENTS
486 select MIGHT_HAVE_PCI
487 select NEED_MACH_IO_H
488 select USB_EHCI_BIG_ENDIAN_MMIO
489 select USB_EHCI_BIG_ENDIAN_DESC
491 Support for Intel's IXP4XX (XScale) family of processors.
495 select ARCH_REQUIRE_GPIOLIB
497 select GENERIC_CLOCKEVENTS
498 select MIGHT_HAVE_PCI
501 select PLAT_ORION_LEGACY
502 select USB_ARCH_HAS_EHCI
505 Support for the Marvell Dove SoC 88AP510
508 bool "Marvell Kirkwood"
509 select ARCH_REQUIRE_GPIOLIB
511 select GENERIC_CLOCKEVENTS
515 select PINCTRL_KIRKWOOD
516 select PLAT_ORION_LEGACY
519 Support for the following Marvell Kirkwood series SoCs:
520 88F6180, 88F6192 and 88F6281.
523 bool "Marvell MV78xx0"
524 select ARCH_REQUIRE_GPIOLIB
526 select GENERIC_CLOCKEVENTS
528 select PLAT_ORION_LEGACY
531 Support for the following Marvell MV78xx0 series SoCs:
537 select ARCH_REQUIRE_GPIOLIB
539 select GENERIC_CLOCKEVENTS
541 select PLAT_ORION_LEGACY
544 Support for the following Marvell Orion 5x series SoCs:
545 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
546 Orion-2 (5281), Orion-1-90 (6183).
549 bool "Marvell PXA168/910/MMP2"
551 select ARCH_REQUIRE_GPIOLIB
553 select GENERIC_ALLOCATOR
554 select GENERIC_CLOCKEVENTS
557 select NEED_MACH_GPIO_H
562 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
565 bool "Micrel/Kendin KS8695"
566 select ARCH_REQUIRE_GPIOLIB
569 select GENERIC_CLOCKEVENTS
570 select NEED_MACH_MEMORY_H
572 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
573 System-on-Chip devices.
576 bool "Nuvoton W90X900 CPU"
577 select ARCH_REQUIRE_GPIOLIB
581 select GENERIC_CLOCKEVENTS
583 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
584 At present, the w90x900 has been renamed nuc900, regarding
585 the ARM series product line, you can login the following
586 link address to know more.
588 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
589 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
593 select ARCH_REQUIRE_GPIOLIB
598 select GENERIC_CLOCKEVENTS
601 select USB_ARCH_HAS_OHCI
604 Support for the NXP LPC32XX family of processors
607 bool "PXA2xx/PXA3xx-based"
609 select ARCH_HAS_CPUFREQ
611 select ARCH_REQUIRE_GPIOLIB
612 select ARM_CPU_SUSPEND if PM
616 select GENERIC_CLOCKEVENTS
619 select MULTI_IRQ_HANDLER
620 select NEED_MACH_GPIO_H
624 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
628 select ARCH_REQUIRE_GPIOLIB
630 select GENERIC_CLOCKEVENTS
633 Support for Qualcomm MSM/QSD based systems. This runs on the
634 apps processor of the MSM/QSD and depends on a shared memory
635 interface to the modem processor which runs the baseband
636 stack and controls some vital subsystems
637 (clock and power control, etc).
640 bool "Renesas SH-Mobile / R-Mobile"
642 select GENERIC_CLOCKEVENTS
643 select HAVE_ARM_SCU if SMP
644 select HAVE_ARM_TWD if LOCAL_TIMERS
646 select HAVE_MACH_CLKDEV
648 select MIGHT_HAVE_CACHE_L2X0
649 select MULTI_IRQ_HANDLER
650 select NEED_MACH_MEMORY_H
652 select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
653 select PM_GENERIC_DOMAINS if PM
656 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
661 select ARCH_MAY_HAVE_PC_FDC
662 select ARCH_SPARSEMEM_ENABLE
663 select ARCH_USES_GETTIMEOFFSET
666 select HAVE_PATA_PLATFORM
668 select NEED_MACH_IO_H
669 select NEED_MACH_MEMORY_H
673 On the Acorn Risc-PC, Linux can support the internal IDE disk and
674 CD-ROM interface, serial and parallel port, and the floppy drive.
678 select ARCH_HAS_CPUFREQ
680 select ARCH_REQUIRE_GPIOLIB
681 select ARCH_SPARSEMEM_ENABLE
686 select GENERIC_CLOCKEVENTS
689 select NEED_MACH_GPIO_H
690 select NEED_MACH_MEMORY_H
693 Support for StrongARM 11x0 based boards.
696 bool "Samsung S3C24XX SoCs"
697 select ARCH_HAS_CPUFREQ
698 select ARCH_REQUIRE_GPIOLIB
701 select GENERIC_CLOCKEVENTS
703 select HAVE_S3C2410_I2C if I2C
704 select HAVE_S3C2410_WATCHDOG if WATCHDOG
705 select HAVE_S3C_RTC if RTC_CLASS
706 select MULTI_IRQ_HANDLER
707 select NEED_MACH_GPIO_H
708 select NEED_MACH_IO_H
710 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
711 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
712 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
713 Samsung SMDK2410 development board (and derivatives).
716 bool "Samsung S3C64XX"
717 select ARCH_HAS_CPUFREQ
718 select ARCH_REQUIRE_GPIOLIB
723 select GENERIC_CLOCKEVENTS
725 select HAVE_S3C2410_I2C if I2C
726 select HAVE_S3C2410_WATCHDOG if WATCHDOG
728 select NEED_MACH_GPIO_H
732 select S3C_GPIO_TRACK
733 select SAMSUNG_CLKSRC
734 select SAMSUNG_GPIOLIB_4BIT
735 select SAMSUNG_IRQ_VIC_TIMER
736 select USB_ARCH_HAS_OHCI
738 Samsung S3C64XX series based systems
741 bool "Samsung S5P6440 S5P6450"
745 select GENERIC_CLOCKEVENTS
747 select HAVE_S3C2410_I2C if I2C
748 select HAVE_S3C2410_WATCHDOG if WATCHDOG
749 select HAVE_S3C_RTC if RTC_CLASS
750 select NEED_MACH_GPIO_H
752 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
756 bool "Samsung S5PC100"
757 select ARCH_REQUIRE_GPIOLIB
761 select GENERIC_CLOCKEVENTS
763 select HAVE_S3C2410_I2C if I2C
764 select HAVE_S3C2410_WATCHDOG if WATCHDOG
765 select HAVE_S3C_RTC if RTC_CLASS
766 select NEED_MACH_GPIO_H
768 Samsung S5PC100 series based systems
771 bool "Samsung S5PV210/S5PC110"
772 select ARCH_HAS_CPUFREQ
773 select ARCH_HAS_HOLES_MEMORYMODEL
774 select ARCH_SPARSEMEM_ENABLE
778 select GENERIC_CLOCKEVENTS
780 select HAVE_S3C2410_I2C if I2C
781 select HAVE_S3C2410_WATCHDOG if WATCHDOG
782 select HAVE_S3C_RTC if RTC_CLASS
783 select NEED_MACH_GPIO_H
784 select NEED_MACH_MEMORY_H
786 Samsung S5PV210/S5PC110 series based systems
789 bool "Samsung EXYNOS"
790 select ARCH_HAS_CPUFREQ
791 select ARCH_HAS_HOLES_MEMORYMODEL
792 select ARCH_SPARSEMEM_ENABLE
796 select GENERIC_CLOCKEVENTS
798 select HAVE_S3C2410_I2C if I2C
799 select HAVE_S3C2410_WATCHDOG if WATCHDOG
800 select HAVE_S3C_RTC if RTC_CLASS
801 select NEED_MACH_GPIO_H
802 select NEED_MACH_MEMORY_H
804 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
808 select ARCH_USES_GETTIMEOFFSET
812 select NEED_MACH_MEMORY_H
817 Support for the StrongARM based Digital DNARD machine, also known
818 as "Shark" (<http://www.shark-linux.de/shark.html>).
821 bool "ST-Ericsson U300 Series"
823 select ARCH_REQUIRE_GPIOLIB
825 select ARM_PATCH_PHYS_VIRT
831 select GENERIC_CLOCKEVENTS
835 Support for ST-Ericsson U300 series mobile platforms.
839 select ARCH_HAS_HOLES_MEMORYMODEL
840 select ARCH_REQUIRE_GPIOLIB
842 select GENERIC_ALLOCATOR
843 select GENERIC_CLOCKEVENTS
844 select GENERIC_IRQ_CHIP
846 select NEED_MACH_GPIO_H
850 Support for TI's DaVinci platform.
855 select ARCH_HAS_CPUFREQ
856 select ARCH_HAS_HOLES_MEMORYMODEL
858 select ARCH_REQUIRE_GPIOLIB
861 select GENERIC_CLOCKEVENTS
862 select GENERIC_IRQ_CHIP
866 select NEED_MACH_IO_H if PCCARD
867 select NEED_MACH_MEMORY_H
869 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
873 menu "Multiple platform selection"
874 depends on ARCH_MULTIPLATFORM
876 comment "CPU Core family selection"
879 bool "ARMv4 based platforms (FA526, StrongARM)"
880 depends on !ARCH_MULTI_V6_V7
881 select ARCH_MULTI_V4_V5
883 config ARCH_MULTI_V4T
884 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
885 depends on !ARCH_MULTI_V6_V7
886 select ARCH_MULTI_V4_V5
889 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
890 depends on !ARCH_MULTI_V6_V7
891 select ARCH_MULTI_V4_V5
893 config ARCH_MULTI_V4_V5
897 bool "ARMv6 based platforms (ARM11)"
898 select ARCH_MULTI_V6_V7
902 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
904 select ARCH_MULTI_V6_V7
907 config ARCH_MULTI_V6_V7
910 config ARCH_MULTI_CPU_AUTO
911 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
917 # This is sorted alphabetically by mach-* pathname. However, plat-*
918 # Kconfigs may be included either alphabetically (according to the
919 # plat- suffix) or along side the corresponding mach-* source.
921 source "arch/arm/mach-mvebu/Kconfig"
923 source "arch/arm/mach-at91/Kconfig"
925 source "arch/arm/mach-bcm/Kconfig"
927 source "arch/arm/mach-bcm2835/Kconfig"
929 source "arch/arm/mach-clps711x/Kconfig"
931 source "arch/arm/mach-cns3xxx/Kconfig"
933 source "arch/arm/mach-davinci/Kconfig"
935 source "arch/arm/mach-dove/Kconfig"
937 source "arch/arm/mach-ep93xx/Kconfig"
939 source "arch/arm/mach-footbridge/Kconfig"
941 source "arch/arm/mach-gemini/Kconfig"
943 source "arch/arm/mach-highbank/Kconfig"
945 source "arch/arm/mach-integrator/Kconfig"
947 source "arch/arm/mach-iop32x/Kconfig"
949 source "arch/arm/mach-iop33x/Kconfig"
951 source "arch/arm/mach-iop13xx/Kconfig"
953 source "arch/arm/mach-ixp4xx/Kconfig"
955 source "arch/arm/mach-kirkwood/Kconfig"
957 source "arch/arm/mach-ks8695/Kconfig"
959 source "arch/arm/mach-msm/Kconfig"
961 source "arch/arm/mach-mv78xx0/Kconfig"
963 source "arch/arm/mach-imx/Kconfig"
965 source "arch/arm/mach-mxs/Kconfig"
967 source "arch/arm/mach-netx/Kconfig"
969 source "arch/arm/mach-nomadik/Kconfig"
971 source "arch/arm/plat-omap/Kconfig"
973 source "arch/arm/mach-omap1/Kconfig"
975 source "arch/arm/mach-omap2/Kconfig"
977 source "arch/arm/mach-orion5x/Kconfig"
979 source "arch/arm/mach-picoxcell/Kconfig"
981 source "arch/arm/mach-pxa/Kconfig"
982 source "arch/arm/plat-pxa/Kconfig"
984 source "arch/arm/mach-mmp/Kconfig"
986 source "arch/arm/mach-realview/Kconfig"
988 source "arch/arm/mach-rockchip/Kconfig"
990 source "arch/arm/mach-sa1100/Kconfig"
992 source "arch/arm/plat-samsung/Kconfig"
994 source "arch/arm/mach-socfpga/Kconfig"
996 source "arch/arm/mach-spear/Kconfig"
998 source "arch/arm/mach-s3c24xx/Kconfig"
1001 source "arch/arm/mach-s3c64xx/Kconfig"
1004 source "arch/arm/mach-s5p64x0/Kconfig"
1006 source "arch/arm/mach-s5pc100/Kconfig"
1008 source "arch/arm/mach-s5pv210/Kconfig"
1010 source "arch/arm/mach-exynos/Kconfig"
1012 source "arch/arm/mach-shmobile/Kconfig"
1014 source "arch/arm/mach-sunxi/Kconfig"
1016 source "arch/arm/mach-prima2/Kconfig"
1018 source "arch/arm/mach-tegra/Kconfig"
1020 source "arch/arm/mach-u300/Kconfig"
1022 source "arch/arm/mach-ux500/Kconfig"
1024 source "arch/arm/mach-versatile/Kconfig"
1026 source "arch/arm/mach-vexpress/Kconfig"
1027 source "arch/arm/plat-versatile/Kconfig"
1029 source "arch/arm/mach-virt/Kconfig"
1031 source "arch/arm/mach-vt8500/Kconfig"
1033 source "arch/arm/mach-w90x900/Kconfig"
1035 source "arch/arm/mach-zynq/Kconfig"
1037 # Definitions to make life easier
1043 select GENERIC_CLOCKEVENTS
1049 select GENERIC_IRQ_CHIP
1052 config PLAT_ORION_LEGACY
1059 config PLAT_VERSATILE
1062 config ARM_TIMER_SP804
1065 select CLKSRC_OF if OF
1067 source arch/arm/mm/Kconfig
1071 default 16 if ARCH_EP93XX
1075 bool "Enable iWMMXt support" if !CPU_PJ4
1076 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1077 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1079 Enable support for iWMMXt context switching at run time if
1080 running on a CPU that supports it.
1084 depends on CPU_XSCALE
1087 config MULTI_IRQ_HANDLER
1090 Allow each machine to specify it's own IRQ handler at run time.
1093 source "arch/arm/Kconfig-nommu"
1096 config PJ4B_ERRATA_4742
1097 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1098 depends on CPU_PJ4B && MACH_ARMADA_370
1101 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1102 Event (WFE) IDLE states, a specific timing sensitivity exists between
1103 the retiring WFI/WFE instructions and the newly issued subsequent
1104 instructions. This sensitivity can result in a CPU hang scenario.
1106 The software must insert either a Data Synchronization Barrier (DSB)
1107 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1110 config ARM_ERRATA_326103
1111 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1114 Executing a SWP instruction to read-only memory does not set bit 11
1115 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1116 treat the access as a read, preventing a COW from occurring and
1117 causing the faulting task to livelock.
1119 config ARM_ERRATA_411920
1120 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1121 depends on CPU_V6 || CPU_V6K
1123 Invalidation of the Instruction Cache operation can
1124 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1125 It does not affect the MPCore. This option enables the ARM Ltd.
1126 recommended workaround.
1128 config ARM_ERRATA_430973
1129 bool "ARM errata: Stale prediction on replaced interworking branch"
1132 This option enables the workaround for the 430973 Cortex-A8
1133 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1134 interworking branch is replaced with another code sequence at the
1135 same virtual address, whether due to self-modifying code or virtual
1136 to physical address re-mapping, Cortex-A8 does not recover from the
1137 stale interworking branch prediction. This results in Cortex-A8
1138 executing the new code sequence in the incorrect ARM or Thumb state.
1139 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1140 and also flushes the branch target cache at every context switch.
1141 Note that setting specific bits in the ACTLR register may not be
1142 available in non-secure mode.
1144 config ARM_ERRATA_458693
1145 bool "ARM errata: Processor deadlock when a false hazard is created"
1147 depends on !ARCH_MULTIPLATFORM
1149 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1150 erratum. For very specific sequences of memory operations, it is
1151 possible for a hazard condition intended for a cache line to instead
1152 be incorrectly associated with a different cache line. This false
1153 hazard might then cause a processor deadlock. The workaround enables
1154 the L1 caching of the NEON accesses and disables the PLD instruction
1155 in the ACTLR register. Note that setting specific bits in the ACTLR
1156 register may not be available in non-secure mode.
1158 config ARM_ERRATA_460075
1159 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1161 depends on !ARCH_MULTIPLATFORM
1163 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1164 erratum. Any asynchronous access to the L2 cache may encounter a
1165 situation in which recent store transactions to the L2 cache are lost
1166 and overwritten with stale memory contents from external memory. The
1167 workaround disables the write-allocate mode for the L2 cache via the
1168 ACTLR register. Note that setting specific bits in the ACTLR register
1169 may not be available in non-secure mode.
1171 config ARM_ERRATA_742230
1172 bool "ARM errata: DMB operation may be faulty"
1173 depends on CPU_V7 && SMP
1174 depends on !ARCH_MULTIPLATFORM
1176 This option enables the workaround for the 742230 Cortex-A9
1177 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1178 between two write operations may not ensure the correct visibility
1179 ordering of the two writes. This workaround sets a specific bit in
1180 the diagnostic register of the Cortex-A9 which causes the DMB
1181 instruction to behave as a DSB, ensuring the correct behaviour of
1184 config ARM_ERRATA_742231
1185 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1186 depends on CPU_V7 && SMP
1187 depends on !ARCH_MULTIPLATFORM
1189 This option enables the workaround for the 742231 Cortex-A9
1190 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1191 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1192 accessing some data located in the same cache line, may get corrupted
1193 data due to bad handling of the address hazard when the line gets
1194 replaced from one of the CPUs at the same time as another CPU is
1195 accessing it. This workaround sets specific bits in the diagnostic
1196 register of the Cortex-A9 which reduces the linefill issuing
1197 capabilities of the processor.
1199 config PL310_ERRATA_588369
1200 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1201 depends on CACHE_L2X0
1203 The PL310 L2 cache controller implements three types of Clean &
1204 Invalidate maintenance operations: by Physical Address
1205 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1206 They are architecturally defined to behave as the execution of a
1207 clean operation followed immediately by an invalidate operation,
1208 both performing to the same memory location. This functionality
1209 is not correctly implemented in PL310 as clean lines are not
1210 invalidated as a result of these operations.
1212 config ARM_ERRATA_643719
1213 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1214 depends on CPU_V7 && SMP
1216 This option enables the workaround for the 643719 Cortex-A9 (prior to
1217 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1218 register returns zero when it should return one. The workaround
1219 corrects this value, ensuring cache maintenance operations which use
1220 it behave as intended and avoiding data corruption.
1222 config ARM_ERRATA_720789
1223 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1226 This option enables the workaround for the 720789 Cortex-A9 (prior to
1227 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1228 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1229 As a consequence of this erratum, some TLB entries which should be
1230 invalidated are not, resulting in an incoherency in the system page
1231 tables. The workaround changes the TLB flushing routines to invalidate
1232 entries regardless of the ASID.
1234 config PL310_ERRATA_727915
1235 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1236 depends on CACHE_L2X0
1238 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1239 operation (offset 0x7FC). This operation runs in background so that
1240 PL310 can handle normal accesses while it is in progress. Under very
1241 rare circumstances, due to this erratum, write data can be lost when
1242 PL310 treats a cacheable write transaction during a Clean &
1243 Invalidate by Way operation.
1245 config ARM_ERRATA_743622
1246 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1248 depends on !ARCH_MULTIPLATFORM
1250 This option enables the workaround for the 743622 Cortex-A9
1251 (r2p*) erratum. Under very rare conditions, a faulty
1252 optimisation in the Cortex-A9 Store Buffer may lead to data
1253 corruption. This workaround sets a specific bit in the diagnostic
1254 register of the Cortex-A9 which disables the Store Buffer
1255 optimisation, preventing the defect from occurring. This has no
1256 visible impact on the overall performance or power consumption of the
1259 config ARM_ERRATA_751472
1260 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1262 depends on !ARCH_MULTIPLATFORM
1264 This option enables the workaround for the 751472 Cortex-A9 (prior
1265 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1266 completion of a following broadcasted operation if the second
1267 operation is received by a CPU before the ICIALLUIS has completed,
1268 potentially leading to corrupted entries in the cache or TLB.
1270 config PL310_ERRATA_753970
1271 bool "PL310 errata: cache sync operation may be faulty"
1272 depends on CACHE_PL310
1274 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1276 Under some condition the effect of cache sync operation on
1277 the store buffer still remains when the operation completes.
1278 This means that the store buffer is always asked to drain and
1279 this prevents it from merging any further writes. The workaround
1280 is to replace the normal offset of cache sync operation (0x730)
1281 by another offset targeting an unmapped PL310 register 0x740.
1282 This has the same effect as the cache sync operation: store buffer
1283 drain and waiting for all buffers empty.
1285 config ARM_ERRATA_754322
1286 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1289 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1290 r3p*) erratum. A speculative memory access may cause a page table walk
1291 which starts prior to an ASID switch but completes afterwards. This
1292 can populate the micro-TLB with a stale entry which may be hit with
1293 the new ASID. This workaround places two dsb instructions in the mm
1294 switching code so that no page table walks can cross the ASID switch.
1296 config ARM_ERRATA_754327
1297 bool "ARM errata: no automatic Store Buffer drain"
1298 depends on CPU_V7 && SMP
1300 This option enables the workaround for the 754327 Cortex-A9 (prior to
1301 r2p0) erratum. The Store Buffer does not have any automatic draining
1302 mechanism and therefore a livelock may occur if an external agent
1303 continuously polls a memory location waiting to observe an update.
1304 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1305 written polling loops from denying visibility of updates to memory.
1307 config ARM_ERRATA_364296
1308 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1309 depends on CPU_V6 && !SMP
1311 This options enables the workaround for the 364296 ARM1136
1312 r0p2 erratum (possible cache data corruption with
1313 hit-under-miss enabled). It sets the undocumented bit 31 in
1314 the auxiliary control register and the FI bit in the control
1315 register, thus disabling hit-under-miss without putting the
1316 processor into full low interrupt latency mode. ARM11MPCore
1319 config ARM_ERRATA_764369
1320 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1321 depends on CPU_V7 && SMP
1323 This option enables the workaround for erratum 764369
1324 affecting Cortex-A9 MPCore with two or more processors (all
1325 current revisions). Under certain timing circumstances, a data
1326 cache line maintenance operation by MVA targeting an Inner
1327 Shareable memory region may fail to proceed up to either the
1328 Point of Coherency or to the Point of Unification of the
1329 system. This workaround adds a DSB instruction before the
1330 relevant cache maintenance functions and sets a specific bit
1331 in the diagnostic control register of the SCU.
1333 config PL310_ERRATA_769419
1334 bool "PL310 errata: no automatic Store Buffer drain"
1335 depends on CACHE_L2X0
1337 On revisions of the PL310 prior to r3p2, the Store Buffer does
1338 not automatically drain. This can cause normal, non-cacheable
1339 writes to be retained when the memory system is idle, leading
1340 to suboptimal I/O performance for drivers using coherent DMA.
1341 This option adds a write barrier to the cpu_idle loop so that,
1342 on systems with an outer cache, the store buffer is drained
1345 config ARM_ERRATA_775420
1346 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1349 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1350 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1351 operation aborts with MMU exception, it might cause the processor
1352 to deadlock. This workaround puts DSB before executing ISB if
1353 an abort may occur on cache maintenance.
1355 config ARM_ERRATA_798181
1356 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1357 depends on CPU_V7 && SMP
1359 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1360 adequately shooting down all use of the old entries. This
1361 option enables the Linux kernel workaround for this erratum
1362 which sends an IPI to the CPUs that are running the same ASID
1363 as the one being invalidated.
1365 config ARM_ERRATA_818325
1366 bool "ARM errata: Execution of an UNPREDICTABLE STR or STM instruction might deadlock"
1369 This option enables the workaround for the 818325 Cortex-A12
1370 (r0p0..r0p1-00lac0-rc11) erratum. When a CPU executes a sequence of
1371 two conditional store instructions with opposite condition code and
1372 updating the same register, the system might enter a deadlock if the
1373 second conditional instruction is an UNPREDICTABLE STR or STM
1374 instruction. This workaround setting bit[12] of the Feature Register
1375 prevents the erratum. This bit disables an optimisation applied to a
1376 sequence of 2 instructions that use opposing condition codes.
1378 config ARM_ERRATA_821420
1379 bool "ARM errata: A sequence of VMOV to core registers instruction might lead to a deadlock"
1382 This option enables the workaround for the 821420 Cortex-A12 (r0p0,
1383 r0p1) erratum. In very rare timing conditions, a sequence of VMOV to
1384 Core registers instructions, for which the second one is in the
1385 shadow of a branch or abort, can lead to a deadlock when the VMOV
1386 instructions are issued out-of-order.
1390 source "arch/arm/common/Kconfig"
1400 Find out whether you have ISA slots on your motherboard. ISA is the
1401 name of a bus system, i.e. the way the CPU talks to the other stuff
1402 inside your box. Other bus systems are PCI, EISA, MicroChannel
1403 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1404 newer boards don't support it. If you have ISA, say Y, otherwise N.
1406 # Select ISA DMA controller support
1411 # Select ISA DMA interface
1416 bool "PCI support" if MIGHT_HAVE_PCI
1418 Find out whether you have a PCI motherboard. PCI is the name of a
1419 bus system, i.e. the way the CPU talks to the other stuff inside
1420 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1421 VESA. If you have PCI, say Y, otherwise N.
1427 config PCI_NANOENGINE
1428 bool "BSE nanoEngine PCI support"
1429 depends on SA1100_NANOENGINE
1431 Enable PCI on the BSE nanoEngine board.
1436 # Select the host bridge type
1437 config PCI_HOST_VIA82C505
1439 depends on PCI && ARCH_SHARK
1442 config PCI_HOST_ITE8152
1444 depends on PCI && MACH_ARMCORE
1448 source "drivers/pci/Kconfig"
1450 source "drivers/pcmcia/Kconfig"
1454 menu "Kernel Features"
1459 This option should be selected by machines which have an SMP-
1462 The only effect of this option is to make the SMP-related
1463 options available to the user for configuration.
1466 bool "Symmetric Multi-Processing"
1467 depends on CPU_V6K || CPU_V7
1468 depends on GENERIC_CLOCKEVENTS
1471 select USE_GENERIC_SMP_HELPERS
1473 This enables support for systems with more than one CPU. If you have
1474 a system with only one CPU, like most personal computers, say N. If
1475 you have a system with more than one CPU, say Y.
1477 If you say N here, the kernel will run on single and multiprocessor
1478 machines, but will use only one CPU of a multiprocessor machine. If
1479 you say Y here, the kernel will run on many, but not all, single
1480 processor machines. On a single processor machine, the kernel will
1481 run faster if you say N here.
1483 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1484 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1485 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1487 If you don't know what to do here, say N.
1490 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1491 depends on SMP && !XIP_KERNEL
1494 SMP kernels contain instructions which fail on non-SMP processors.
1495 Enabling this option allows the kernel to modify itself to make
1496 these instructions safe. Disabling it allows about 1K of space
1499 If you don't know what to do here, say Y.
1501 config ARM_CPU_TOPOLOGY
1502 bool "Support cpu topology definition"
1503 depends on SMP && CPU_V7
1506 Support ARM cpu topology definition. The MPIDR register defines
1507 affinity between processors which is then used to describe the cpu
1508 topology of an ARM System.
1511 bool "Multi-core scheduler support"
1512 depends on ARM_CPU_TOPOLOGY
1514 Multi-core scheduler support improves the CPU scheduler's decision
1515 making when dealing with multi-core CPU chips at a cost of slightly
1516 increased overhead in some places. If unsure say N here.
1519 bool "SMT scheduler support"
1520 depends on ARM_CPU_TOPOLOGY
1522 Improves the CPU scheduler's decision making when dealing with
1523 MultiThreading at a cost of slightly increased overhead in some
1524 places. If unsure say N here.
1526 config DISABLE_CPU_SCHED_DOMAIN_BALANCE
1527 bool "(EXPERIMENTAL) Disable CPU level scheduler load-balancing"
1529 Disables scheduler load-balancing at CPU sched domain level.
1532 bool "(EXPERIMENTAL) Heterogenous multiprocessor scheduling"
1533 depends on DISABLE_CPU_SCHED_DOMAIN_BALANCE && SCHED_MC && FAIR_GROUP_SCHED && !SCHED_AUTOGROUP
1535 Experimental scheduler optimizations for heterogeneous platforms.
1536 Attempts to introspectively select task affinity to optimize power
1537 and performance. Basic support for multiple (>2) cpu types is in place,
1538 but it has only been tested with two types of cpus.
1539 There is currently no support for migration of task groups, hence
1540 !SCHED_AUTOGROUP. Furthermore, normal load-balancing must be disabled
1541 between cpus of different type (DISABLE_CPU_SCHED_DOMAIN_BALANCE).
1542 When turned on, this option adds sys/kernel/hmp directory which
1543 contains the following files:
1544 up_threshold - the load average threshold used for up migration
1546 down_threshold - the load average threshold used for down migration
1548 hmp_domains - a list of cpumasks for the present HMP domains,
1549 starting with the 'biggest' and ending with the
1551 Note that both the threshold files can be written at runtime to
1552 control scheduler behaviour.
1554 config SCHED_HMP_PRIO_FILTER
1555 bool "(EXPERIMENTAL) Filter HMP migrations by task priority"
1556 depends on SCHED_HMP
1558 Enables task priority based HMP migration filter. Any task with
1559 a NICE value above the threshold will always be on low-power cpus
1560 with less compute capacity.
1562 config SCHED_HMP_PRIO_FILTER_VAL
1563 int "NICE priority threshold"
1565 depends on SCHED_HMP_PRIO_FILTER
1567 config HMP_FAST_CPU_MASK
1568 string "HMP scheduler fast CPU mask"
1569 depends on SCHED_HMP
1571 Leave empty to use device tree information.
1572 Specify the cpuids of the fast CPUs in the system as a list string,
1573 e.g. cpuid 0+1 should be specified as 0-1.
1575 config HMP_SLOW_CPU_MASK
1576 string "HMP scheduler slow CPU mask"
1577 depends on SCHED_HMP
1579 Leave empty to use device tree information.
1580 Specify the cpuids of the slow CPUs in the system as a list string,
1581 e.g. cpuid 0+1 should be specified as 0-1.
1583 config HMP_VARIABLE_SCALE
1584 bool "Allows changing the load tracking scale through sysfs"
1585 depends on SCHED_HMP
1587 When turned on, this option exports the load average period value
1588 for the load tracking patches through sysfs.
1589 The values can be modified to change the rate of load accumulation
1590 used for HMP migration. 'load_avg_period_ms' is the time in ms to
1591 reach a load average of 0.5 for an idle task of 0 load average
1592 ratio which becomes 100% busy.
1593 For example, with load_avg_period_ms = 128 and up_threshold = 512,
1594 a running task with a load of 0 will be migrated to a bigger CPU after
1595 128ms, because after 128ms its load_avg_ratio is 0.5 and the real
1596 up_threshold is 0.5.
1597 This patch has the same behavior as changing the Y of the load
1598 average computation to
1599 (1002/1024)^(LOAD_AVG_PERIOD/load_avg_period_ms)
1600 but removes intermediate overflows in computation.
1602 config HMP_FREQUENCY_INVARIANT_SCALE
1603 bool "(EXPERIMENTAL) Frequency-Invariant Tracked Load for HMP"
1604 depends on SCHED_HMP && CPU_FREQ
1606 Scales the current load contribution in line with the frequency
1607 of the CPU that the task was executed on.
1608 In this version, we use a simple linear scale derived from the
1609 maximum frequency reported by CPUFreq.
1610 Restricting tracked load to be scaled by the CPU's frequency
1611 represents the consumption of possible compute capacity
1612 (rather than consumption of actual instantaneous capacity as
1613 normal) and allows the HMP migration's simple threshold
1614 migration strategy to interact more predictably with CPUFreq's
1615 asynchronous compute capacity changes.
1617 config SCHED_HMP_LITTLE_PACKING
1618 bool "Small task packing for HMP"
1619 depends on SCHED_HMP
1622 Allows the HMP Scheduler to pack small tasks into CPUs in the
1623 smallest HMP domain.
1624 Controlled by two sysfs files in sys/kernel/hmp.
1625 packing_enable: 1 to enable, 0 to disable packing. Default 1.
1626 packing_limit: runqueue load ratio where a RQ is considered
1627 to be full. Default is NICE_0_LOAD * 9/8.
1632 This option enables support for the ARM system coherency unit
1634 config HAVE_ARM_ARCH_TIMER
1635 bool "Architected timer support"
1637 select ARM_ARCH_TIMER
1639 This option enables support for the ARM architected timer
1644 select CLKSRC_OF if OF
1646 This options enables support for the ARM timer and watchdog unit
1649 bool "Multi-Cluster Power Management"
1650 depends on CPU_V7 && SMP
1652 This option provides the common power management infrastructure
1653 for (multi-)cluster based systems, such as big.LITTLE based
1657 bool "big.LITTLE support (Experimental)"
1658 depends on CPU_V7 && SMP
1661 This option enables support for the big.LITTLE architecture.
1664 bool "big.LITTLE switcher support"
1665 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1667 select ARM_CPU_SUSPEND
1669 The big.LITTLE "switcher" provides the core functionality to
1670 transparently handle transition between a cluster of A15's
1671 and a cluster of A7's in a big.LITTLE system.
1673 config BL_SWITCHER_DUMMY_IF
1674 tristate "Simple big.LITTLE switcher user interface"
1675 depends on BL_SWITCHER && DEBUG_KERNEL
1677 This is a simple and dummy char dev interface to control
1678 the big.LITTLE switcher core code. It is meant for
1679 debugging purposes only.
1682 prompt "Memory split"
1685 Select the desired split between kernel and user memory.
1687 If you are not absolutely sure what you are doing, leave this
1691 bool "3G/1G user/kernel split"
1693 bool "2G/2G user/kernel split"
1695 bool "1G/3G user/kernel split"
1700 default 0x40000000 if VMSPLIT_1G
1701 default 0x80000000 if VMSPLIT_2G
1705 int "Maximum number of CPUs (2-32)"
1711 bool "Support for hot-pluggable CPUs"
1712 depends on SMP && HOTPLUG
1714 Say Y here to experiment with turning CPUs off and on. CPUs
1715 can be controlled through /sys/devices/system/cpu.
1718 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1721 Say Y here if you want Linux to communicate with system firmware
1722 implementing the PSCI specification for CPU-centric power
1723 management operations described in ARM document number ARM DEN
1724 0022A ("Power State Coordination Interface System Software on
1728 bool "Use local timer interrupts"
1732 Enable support for local timers on SMP platforms, rather then the
1733 legacy IPI broadcast method. Local timers allows the system
1734 accounting to be spread across the timer interval, preventing a
1735 "thundering herd" at every timer tick.
1737 # The GPIO number here must be sorted by descending number. In case of
1738 # a multiplatform kernel, we just want the highest value required by the
1739 # selected platforms.
1742 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1743 default 512 if SOC_OMAP5
1744 default 512 if ARCH_ROCKCHIP
1745 default 392 if ARCH_U8500
1746 default 352 if ARCH_VT8500
1747 default 288 if ARCH_SUNXI
1748 default 264 if MACH_H4700
1751 Maximum number of GPIOs in the system.
1753 If unsure, leave the default value.
1755 source kernel/Kconfig.preempt
1759 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1760 ARCH_S5PV210 || ARCH_EXYNOS4
1761 default AT91_TIMER_HZ if ARCH_AT91
1762 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1766 def_bool HIGH_RES_TIMERS
1768 config THUMB2_KERNEL
1769 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1770 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1771 default y if CPU_THUMBONLY
1773 select ARM_ASM_UNIFIED
1776 By enabling this option, the kernel will be compiled in
1777 Thumb-2 mode. A compiler/assembler that understand the unified
1778 ARM-Thumb syntax is needed.
1782 config THUMB2_AVOID_R_ARM_THM_JUMP11
1783 bool "Work around buggy Thumb-2 short branch relocations in gas"
1784 depends on THUMB2_KERNEL && MODULES
1787 Various binutils versions can resolve Thumb-2 branches to
1788 locally-defined, preemptible global symbols as short-range "b.n"
1789 branch instructions.
1791 This is a problem, because there's no guarantee the final
1792 destination of the symbol, or any candidate locations for a
1793 trampoline, are within range of the branch. For this reason, the
1794 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1795 relocation in modules at all, and it makes little sense to add
1798 The symptom is that the kernel fails with an "unsupported
1799 relocation" error when loading some modules.
1801 Until fixed tools are available, passing
1802 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1803 code which hits this problem, at the cost of a bit of extra runtime
1804 stack usage in some cases.
1806 The problem is described in more detail at:
1807 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1809 Only Thumb-2 kernels are affected.
1811 Unless you are sure your tools don't have this problem, say Y.
1813 config ARM_ASM_UNIFIED
1817 bool "Use the ARM EABI to compile the kernel"
1819 This option allows for the kernel to be compiled using the latest
1820 ARM ABI (aka EABI). This is only useful if you are using a user
1821 space environment that is also compiled with EABI.
1823 Since there are major incompatibilities between the legacy ABI and
1824 EABI, especially with regard to structure member alignment, this
1825 option also changes the kernel syscall calling convention to
1826 disambiguate both ABIs and allow for backward compatibility support
1827 (selected with CONFIG_OABI_COMPAT).
1829 To use this you need GCC version 4.0.0 or later.
1832 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1833 depends on AEABI && !THUMB2_KERNEL
1836 This option preserves the old syscall interface along with the
1837 new (ARM EABI) one. It also provides a compatibility layer to
1838 intercept syscalls that have structure arguments which layout
1839 in memory differs between the legacy ABI and the new ARM EABI
1840 (only for non "thumb" binaries). This option adds a tiny
1841 overhead to all syscalls and produces a slightly larger kernel.
1842 If you know you'll be using only pure EABI user space then you
1843 can say N here. If this option is not selected and you attempt
1844 to execute a legacy ABI binary then the result will be
1845 UNPREDICTABLE (in fact it can be predicted that it won't work
1846 at all). If in doubt say Y.
1848 config ARCH_HAS_HOLES_MEMORYMODEL
1851 config ARCH_SPARSEMEM_ENABLE
1854 config ARCH_SPARSEMEM_DEFAULT
1855 def_bool ARCH_SPARSEMEM_ENABLE
1857 config ARCH_SELECT_MEMORY_MODEL
1858 def_bool ARCH_SPARSEMEM_ENABLE
1860 config HAVE_ARCH_PFN_VALID
1861 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1864 bool "High Memory Support"
1867 The address space of ARM processors is only 4 Gigabytes large
1868 and it has to accommodate user address space, kernel address
1869 space as well as some memory mapped IO. That means that, if you
1870 have a large amount of physical memory and/or IO, not all of the
1871 memory can be "permanently mapped" by the kernel. The physical
1872 memory that is not permanently mapped is called "high memory".
1874 Depending on the selected kernel/user memory split, minimum
1875 vmalloc space and actual amount of RAM, you may not need this
1876 option which should result in a slightly faster kernel.
1881 bool "Allocate 2nd-level pagetables from highmem"
1884 config HW_PERF_EVENTS
1885 bool "Enable hardware performance counter support for perf events"
1886 depends on PERF_EVENTS
1889 Enable hardware performance counter support for perf events. If
1890 disabled, perf events will use software events only.
1892 config SYS_SUPPORTS_HUGETLBFS
1896 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1902 config FORCE_MAX_ZONEORDER
1903 int "Maximum zone order" if ARCH_SHMOBILE
1904 range 11 64 if ARCH_SHMOBILE
1905 default "12" if SOC_AM33XX
1906 default "9" if SA1111
1909 The kernel memory allocator divides physically contiguous memory
1910 blocks into "zones", where each zone is a power of two number of
1911 pages. This option selects the largest power of two that the kernel
1912 keeps in the memory allocator. If you need to allocate very large
1913 blocks of physically contiguous memory, then you may need to
1914 increase this value.
1916 This config option is actually maximum order plus one. For example,
1917 a value of 11 means that the largest free memory block is 2^10 pages.
1919 config ALIGNMENT_TRAP
1921 depends on CPU_CP15_MMU
1922 default y if !ARCH_EBSA110
1923 select HAVE_PROC_CPU if PROC_FS
1925 ARM processors cannot fetch/store information which is not
1926 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1927 address divisible by 4. On 32-bit ARM processors, these non-aligned
1928 fetch/store instructions will be emulated in software if you say
1929 here, which has a severe performance impact. This is necessary for
1930 correct operation of some network protocols. With an IP-only
1931 configuration it is safe to say N, otherwise say Y.
1933 config UACCESS_WITH_MEMCPY
1934 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1936 default y if CPU_FEROCEON
1938 Implement faster copy_to_user and clear_user methods for CPU
1939 cores where a 8-word STM instruction give significantly higher
1940 memory write throughput than a sequence of individual 32bit stores.
1942 A possible side effect is a slight increase in scheduling latency
1943 between threads sharing the same address space if they invoke
1944 such copy operations with large buffers.
1946 However, if the CPU data cache is using a write-allocate mode,
1947 this option is unlikely to provide any performance gain.
1951 prompt "Enable seccomp to safely compute untrusted bytecode"
1953 This kernel feature is useful for number crunching applications
1954 that may need to compute untrusted bytecode during their
1955 execution. By using pipes or other transports made available to
1956 the process as file descriptors supporting the read/write
1957 syscalls, it's possible to isolate those applications in
1958 their own address space using seccomp. Once seccomp is
1959 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1960 and the task is only allowed to execute a few safe syscalls
1961 defined by each seccomp mode.
1963 config CC_STACKPROTECTOR
1964 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1966 This option turns on the -fstack-protector GCC feature. This
1967 feature puts, at the beginning of functions, a canary value on
1968 the stack just before the return address, and validates
1969 the value just before actually returning. Stack based buffer
1970 overflows (that need to overwrite this return address) now also
1971 overwrite the canary, which gets detected and the attack is then
1972 neutralized via a kernel panic.
1973 This feature requires gcc version 4.2 or above.
1980 bool "Xen guest support on ARM (EXPERIMENTAL)"
1981 depends on ARM && AEABI && OF
1982 depends on CPU_V7 && !CPU_V6
1983 depends on !GENERIC_ATOMIC64
1986 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1988 config ARM_FLUSH_CONSOLE_ON_RESTART
1989 bool "Force flush the console on restart"
1991 If the console is locked while the system is rebooted, the messages
1992 in the temporary logbuffer would not have propogated to all the
1993 console drivers. This option forces the console lock to be
1994 released if it failed to be acquired, which will cause all the
1995 pending messages to be flushed.
2002 bool "Flattened Device Tree support"
2005 select OF_EARLY_FLATTREE
2007 Include support for flattened device tree machine descriptions.
2010 bool "Support for the traditional ATAGS boot data passing" if USE_OF
2013 This is the traditional way of passing data to the kernel at boot
2014 time. If you are solely relying on the flattened device tree (or
2015 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
2016 to remove ATAGS support from your kernel binary. If unsure,
2019 config DEPRECATED_PARAM_STRUCT
2020 bool "Provide old way to pass kernel parameters"
2023 This was deprecated in 2001 and announced to live on for 5 years.
2024 Some old boot loaders still use this way.
2026 config BUILD_ARM_APPENDED_DTB_IMAGE
2027 bool "Build a concatenated zImage/dtb by default"
2030 Enabling this option will cause a concatenated zImage and DTB to
2031 be built by default (instead of a standalone zImage.) The image
2032 will built in arch/arm/boot/zImage-dtb.<dtb name>
2034 config BUILD_ARM_APPENDED_DTB_IMAGE_NAME
2035 string "Default dtb name"
2036 depends on BUILD_ARM_APPENDED_DTB_IMAGE
2038 name of the dtb to append when building a concatenated
2041 # Compressed boot loader in ROM. Yes, we really want to ask about
2042 # TEXT and BSS so we preserve their values in the config files.
2043 config ZBOOT_ROM_TEXT
2044 hex "Compressed ROM boot loader base address"
2047 The physical address at which the ROM-able zImage is to be
2048 placed in the target. Platforms which normally make use of
2049 ROM-able zImage formats normally set this to a suitable
2050 value in their defconfig file.
2052 If ZBOOT_ROM is not enabled, this has no effect.
2054 config ZBOOT_ROM_BSS
2055 hex "Compressed ROM boot loader BSS address"
2058 The base address of an area of read/write memory in the target
2059 for the ROM-able zImage which must be available while the
2060 decompressor is running. It must be large enough to hold the
2061 entire decompressed kernel plus an additional 128 KiB.
2062 Platforms which normally make use of ROM-able zImage formats
2063 normally set this to a suitable value in their defconfig file.
2065 If ZBOOT_ROM is not enabled, this has no effect.
2068 bool "Compressed boot loader in ROM/flash"
2069 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
2071 Say Y here if you intend to execute your compressed kernel image
2072 (zImage) directly from ROM or flash. If unsure, say N.
2075 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
2076 depends on ZBOOT_ROM && ARCH_SH7372
2077 default ZBOOT_ROM_NONE
2079 Include experimental SD/MMC loading code in the ROM-able zImage.
2080 With this enabled it is possible to write the ROM-able zImage
2081 kernel image to an MMC or SD card and boot the kernel straight
2082 from the reset vector. At reset the processor Mask ROM will load
2083 the first part of the ROM-able zImage which in turn loads the
2084 rest the kernel image to RAM.
2086 config ZBOOT_ROM_NONE
2087 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
2089 Do not load image from SD or MMC
2091 config ZBOOT_ROM_MMCIF
2092 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
2094 Load image from MMCIF hardware block.
2096 config ZBOOT_ROM_SH_MOBILE_SDHI
2097 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2099 Load image from SDHI hardware block
2103 config ARM_APPENDED_DTB
2104 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2105 depends on OF && !ZBOOT_ROM
2107 With this option, the boot code will look for a device tree binary
2108 (DTB) appended to zImage
2109 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2111 This is meant as a backward compatibility convenience for those
2112 systems with a bootloader that can't be upgraded to accommodate
2113 the documented boot protocol using a device tree.
2115 Beware that there is very little in terms of protection against
2116 this option being confused by leftover garbage in memory that might
2117 look like a DTB header after a reboot if no actual DTB is appended
2118 to zImage. Do not leave this option active in a production kernel
2119 if you don't intend to always append a DTB. Proper passing of the
2120 location into r2 of a bootloader provided DTB is always preferable
2123 config ARM_ATAG_DTB_COMPAT
2124 bool "Supplement the appended DTB with traditional ATAG information"
2125 depends on ARM_APPENDED_DTB
2127 Some old bootloaders can't be updated to a DTB capable one, yet
2128 they provide ATAGs with memory configuration, the ramdisk address,
2129 the kernel cmdline string, etc. Such information is dynamically
2130 provided by the bootloader and can't always be stored in a static
2131 DTB. To allow a device tree enabled kernel to be used with such
2132 bootloaders, this option allows zImage to extract the information
2133 from the ATAG list and store it at run time into the appended DTB.
2136 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2137 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2139 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2140 bool "Use bootloader kernel arguments if available"
2142 Uses the command-line options passed by the boot loader instead of
2143 the device tree bootargs property. If the boot loader doesn't provide
2144 any, the device tree bootargs property will be used.
2146 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2147 bool "Extend with bootloader kernel arguments"
2149 The command-line arguments provided by the boot loader will be
2150 appended to the the device tree bootargs property.
2155 string "Default kernel command string"
2158 On some architectures (EBSA110 and CATS), there is currently no way
2159 for the boot loader to pass arguments to the kernel. For these
2160 architectures, you should supply some command-line options at build
2161 time by entering them here. As a minimum, you should specify the
2162 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2165 prompt "Kernel command line type" if CMDLINE != ""
2166 default CMDLINE_FROM_BOOTLOADER
2169 config CMDLINE_FROM_BOOTLOADER
2170 bool "Use bootloader kernel arguments if available"
2172 Uses the command-line options passed by the boot loader. If
2173 the boot loader doesn't provide any, the default kernel command
2174 string provided in CMDLINE will be used.
2176 config CMDLINE_EXTEND
2177 bool "Extend bootloader kernel arguments"
2179 The command-line arguments provided by the boot loader will be
2180 appended to the default kernel command string.
2182 config CMDLINE_FORCE
2183 bool "Always use the default kernel command string"
2185 Always use the default kernel command string, even if the boot
2186 loader passes other arguments to the kernel.
2187 This is useful if you cannot or don't want to change the
2188 command-line options your boot loader passes to the kernel.
2192 bool "Kernel Execute-In-Place from ROM"
2193 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2195 Execute-In-Place allows the kernel to run from non-volatile storage
2196 directly addressable by the CPU, such as NOR flash. This saves RAM
2197 space since the text section of the kernel is not loaded from flash
2198 to RAM. Read-write sections, such as the data section and stack,
2199 are still copied to RAM. The XIP kernel is not compressed since
2200 it has to run directly from flash, so it will take more space to
2201 store it. The flash address used to link the kernel object files,
2202 and for storing it, is configuration dependent. Therefore, if you
2203 say Y here, you must know the proper physical address where to
2204 store the kernel image depending on your own flash memory usage.
2206 Also note that the make target becomes "make xipImage" rather than
2207 "make zImage" or "make Image". The final kernel binary to put in
2208 ROM memory will be arch/arm/boot/xipImage.
2212 config XIP_PHYS_ADDR
2213 hex "XIP Kernel Physical Location"
2214 depends on XIP_KERNEL
2215 default "0x00080000"
2217 This is the physical address in your flash memory the kernel will
2218 be linked for and stored to. This address is dependent on your
2222 bool "Kexec system call (EXPERIMENTAL)"
2223 depends on (!SMP || PM_SLEEP_SMP)
2225 kexec is a system call that implements the ability to shutdown your
2226 current kernel, and to start another kernel. It is like a reboot
2227 but it is independent of the system firmware. And like a reboot
2228 you can start any kernel with it, not just Linux.
2230 It is an ongoing process to be certain the hardware in a machine
2231 is properly shutdown, so do not be surprised if this code does not
2232 initially work for you. It may help to enable device hotplugging
2236 bool "Export atags in procfs"
2237 depends on ATAGS && KEXEC
2240 Should the atags used to boot the kernel be exported in an "atags"
2241 file in procfs. Useful with kexec.
2244 bool "Build kdump crash kernel (EXPERIMENTAL)"
2246 Generate crash dump after being started by kexec. This should
2247 be normally only set in special crash dump kernels which are
2248 loaded in the main kernel with kexec-tools into a specially
2249 reserved region and then later executed after a crash by
2250 kdump/kexec. The crash dump kernel must be compiled to a
2251 memory address not used by the main kernel
2253 For more details see Documentation/kdump/kdump.txt
2255 config AUTO_ZRELADDR
2256 bool "Auto calculation of the decompressed kernel image address"
2257 depends on !ZBOOT_ROM && !ARCH_U300
2259 ZRELADDR is the physical address where the decompressed kernel
2260 image will be placed. If AUTO_ZRELADDR is selected, the address
2261 will be determined at run-time by masking the current IP with
2262 0xf8000000. This assumes the zImage being placed in the first 128MB
2263 from start of memory.
2267 menu "CPU Power Management"
2270 source "drivers/cpufreq/Kconfig"
2275 Internal configuration node for common cpufreq on Samsung SoC
2277 config CPU_FREQ_S3C24XX
2278 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2279 depends on ARCH_S3C24XX && CPU_FREQ
2282 This enables the CPUfreq driver for the Samsung S3C24XX family
2285 For details, take a look at <file:Documentation/cpu-freq>.
2289 config CPU_FREQ_S3C24XX_PLL
2290 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2291 depends on CPU_FREQ_S3C24XX
2293 Compile in support for changing the PLL frequency from the
2294 S3C24XX series CPUfreq driver. The PLL takes time to settle
2295 after a frequency change, so by default it is not enabled.
2297 This also means that the PLL tables for the selected CPU(s) will
2298 be built which may increase the size of the kernel image.
2300 config CPU_FREQ_S3C24XX_DEBUG
2301 bool "Debug CPUfreq Samsung driver core"
2302 depends on CPU_FREQ_S3C24XX
2304 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2306 config CPU_FREQ_S3C24XX_IODEBUG
2307 bool "Debug CPUfreq Samsung driver IO timing"
2308 depends on CPU_FREQ_S3C24XX
2310 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2312 config CPU_FREQ_S3C24XX_DEBUGFS
2313 bool "Export debugfs for CPUFreq"
2314 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2316 Export status information via debugfs.
2320 source "drivers/cpuidle/Kconfig"
2324 menu "Floating point emulation"
2326 comment "At least one emulation must be selected"
2329 bool "NWFPE math emulation"
2330 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2332 Say Y to include the NWFPE floating point emulator in the kernel.
2333 This is necessary to run most binaries. Linux does not currently
2334 support floating point hardware so you need to say Y here even if
2335 your machine has an FPA or floating point co-processor podule.
2337 You may say N here if you are going to load the Acorn FPEmulator
2338 early in the bootup.
2341 bool "Support extended precision"
2342 depends on FPE_NWFPE
2344 Say Y to include 80-bit support in the kernel floating-point
2345 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2346 Note that gcc does not generate 80-bit operations by default,
2347 so in most cases this option only enlarges the size of the
2348 floating point emulator without any good reason.
2350 You almost surely want to say N here.
2353 bool "FastFPE math emulation (EXPERIMENTAL)"
2354 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2356 Say Y here to include the FAST floating point emulator in the kernel.
2357 This is an experimental much faster emulator which now also has full
2358 precision for the mantissa. It does not support any exceptions.
2359 It is very simple, and approximately 3-6 times faster than NWFPE.
2361 It should be sufficient for most programs. It may be not suitable
2362 for scientific calculations, but you have to check this for yourself.
2363 If you do not feel you need a faster FP emulation you should better
2367 bool "VFP-format floating point maths"
2368 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2370 Say Y to include VFP support code in the kernel. This is needed
2371 if your hardware includes a VFP unit.
2373 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2374 release notes and additional status information.
2376 Say N if your target does not have VFP hardware.
2384 bool "Advanced SIMD (NEON) Extension support"
2385 depends on VFPv3 && CPU_V7
2387 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2390 config KERNEL_MODE_NEON
2391 bool "Support for NEON in kernel mode"
2395 Say Y to include support for NEON in kernel mode.
2399 menu "Userspace binary formats"
2401 source "fs/Kconfig.binfmt"
2404 tristate "RISC OS personality"
2407 Say Y here to include the kernel code necessary if you want to run
2408 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2409 experimental; if this sounds frightening, say N and sleep in peace.
2410 You can also say M here to compile this support as a module (which
2411 will be called arthur).
2415 menu "Power management options"
2417 source "kernel/power/Kconfig"
2419 config ARCH_SUSPEND_POSSIBLE
2420 depends on !ARCH_S5PC100
2421 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2422 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2425 config ARM_CPU_SUSPEND
2430 source "net/Kconfig"
2432 source "drivers/Kconfig"
2436 source "arch/arm/Kconfig.debug"
2438 source "security/Kconfig"
2440 source "crypto/Kconfig"
2442 source "lib/Kconfig"
2444 source "arch/arm/kvm/Kconfig"