4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_STRNCPY_FROM_USER
19 select GENERIC_STRNLEN_USER
20 select HARDIRQS_SW_RESEND
22 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
24 select HAVE_ARCH_SECCOMP_FILTER
25 select HAVE_ARCH_TRACEHOOK
27 select HAVE_C_RECORDMCOUNT
28 select HAVE_DEBUG_KMEMLEAK
29 select HAVE_DMA_API_DEBUG
31 select HAVE_DMA_CONTIGUOUS if MMU
32 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
33 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
34 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
35 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
36 select HAVE_GENERIC_DMA_COHERENT
37 select HAVE_GENERIC_HARDIRQS
38 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
39 select HAVE_IDE if PCI || ISA || PCMCIA
40 select HAVE_KERNEL_GZIP
41 select HAVE_KERNEL_LZMA
42 select HAVE_KERNEL_LZO
44 select HAVE_KPROBES if !XIP_KERNEL
45 select HAVE_KRETPROBES if (HAVE_KPROBES)
47 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
48 select HAVE_PERF_EVENTS
49 select HAVE_REGS_AND_STACK_ACCESS_API
50 select HAVE_SYSCALL_TRACEPOINTS
53 select PERF_USE_VMALLOC
55 select SYS_SUPPORTS_APM_EMULATION
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select MODULES_USE_ELF_REL
58 select CLONE_BACKWARDS
60 The ARM series is a line of low-power-consumption RISC chip designs
61 licensed by ARM Ltd and targeted at embedded applications and
62 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
63 manufactured, but legacy ARM-based PC hardware remains popular in
64 Europe. There is an ARM Linux project with a web page at
65 <http://www.arm.linux.org.uk/>.
67 config ARM_HAS_SG_CHAIN
70 config NEED_SG_DMA_LENGTH
73 config ARM_DMA_USE_IOMMU
75 select ARM_HAS_SG_CHAIN
76 select NEED_SG_DMA_LENGTH
84 config SYS_SUPPORTS_APM_EMULATION
92 select GENERIC_ALLOCATOR
103 The Extended Industry Standard Architecture (EISA) bus was
104 developed as an open alternative to the IBM MicroChannel bus.
106 The EISA bus provided some of the features of the IBM MicroChannel
107 bus while maintaining backward compatibility with cards made for
108 the older ISA bus. The EISA bus saw limited use between 1988 and
109 1995 when it was made obsolete by the PCI bus.
111 Say Y here if you are building a kernel for an EISA-based machine.
118 config STACKTRACE_SUPPORT
122 config HAVE_LATENCYTOP_SUPPORT
127 config LOCKDEP_SUPPORT
131 config TRACE_IRQFLAGS_SUPPORT
135 config RWSEM_GENERIC_SPINLOCK
139 config RWSEM_XCHGADD_ALGORITHM
142 config ARCH_HAS_ILOG2_U32
145 config ARCH_HAS_ILOG2_U64
148 config ARCH_HAS_CPUFREQ
151 Internal node to signify that the ARCH has CPUFREQ support
152 and that the relevant menu configurations are displayed for
155 config GENERIC_HWEIGHT
159 config GENERIC_CALIBRATE_DELAY
163 config ARCH_MAY_HAVE_PC_FDC
169 config NEED_DMA_MAP_STATE
172 config ARCH_HAS_DMA_SET_COHERENT_MASK
175 config GENERIC_ISA_DMA
181 config NEED_RET_TO_USER
189 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
190 default DRAM_BASE if REMAP_VECTORS_TO_RAM
193 The base address of exception vectors.
195 config ARM_PATCH_PHYS_VIRT
196 bool "Patch physical to virtual translations at runtime" if EMBEDDED
198 depends on !XIP_KERNEL && MMU
199 depends on !ARCH_REALVIEW || !SPARSEMEM
201 Patch phys-to-virt and virt-to-phys translation functions at
202 boot and module load time according to the position of the
203 kernel in system memory.
205 This can only be used with non-XIP MMU kernels where the base
206 of physical memory is at a 16MB boundary.
208 Only disable this option if you know that you do not require
209 this feature (eg, building a kernel for a single machine) and
210 you need to shrink the kernel to the minimal size.
212 config NEED_MACH_GPIO_H
215 Select this when mach/gpio.h is required to provide special
216 definitions for this platform. The need for mach/gpio.h should
217 be avoided when possible.
219 config NEED_MACH_IO_H
222 Select this when mach/io.h is required to provide special
223 definitions for this platform. The need for mach/io.h should
224 be avoided when possible.
226 config NEED_MACH_MEMORY_H
229 Select this when mach/memory.h is required to provide special
230 definitions for this platform. The need for mach/memory.h should
231 be avoided when possible.
234 hex "Physical address of main memory" if MMU
235 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
236 default DRAM_BASE if !MMU
238 Please provide the physical address corresponding to the
239 location of main memory in your system.
245 source "init/Kconfig"
247 source "kernel/Kconfig.freezer"
252 bool "MMU-based Paged Memory Management Support"
255 Select if you want MMU-based virtualised addressing space
256 support by paged memory management. If unsure, say 'Y'.
259 # The "ARM system type" choice list is ordered alphabetically by option
260 # text. Please add new entries in the option alphabetic order.
263 prompt "ARM system type"
264 default ARCH_VERSATILE if !MMU
265 default ARCH_MULTIPLATFORM if MMU
267 config ARCH_MULTIPLATFORM
268 bool "Allow multiple platforms to be selected"
270 select ARM_PATCH_PHYS_VIRT
273 select MULTI_IRQ_HANDLER
277 config ARCH_INTEGRATOR
278 bool "ARM Ltd. Integrator family"
279 select ARCH_HAS_CPUFREQ
282 select COMMON_CLK_VERSATILE
283 select GENERIC_CLOCKEVENTS
286 select MULTI_IRQ_HANDLER
287 select NEED_MACH_MEMORY_H
288 select PLAT_VERSATILE
290 select VERSATILE_FPGA_IRQ
292 Support for ARM's Integrator platform.
295 bool "ARM Ltd. RealView family"
296 select ARCH_WANT_OPTIONAL_GPIOLIB
298 select ARM_TIMER_SP804
300 select COMMON_CLK_VERSATILE
301 select GENERIC_CLOCKEVENTS
302 select GPIO_PL061 if GPIOLIB
304 select NEED_MACH_MEMORY_H
305 select PLAT_VERSATILE
306 select PLAT_VERSATILE_CLCD
308 This enables support for ARM Ltd RealView boards.
310 config ARCH_VERSATILE
311 bool "ARM Ltd. Versatile family"
312 select ARCH_WANT_OPTIONAL_GPIOLIB
314 select ARM_TIMER_SP804
317 select GENERIC_CLOCKEVENTS
318 select HAVE_MACH_CLKDEV
320 select PLAT_VERSATILE
321 select PLAT_VERSATILE_CLCD
322 select PLAT_VERSATILE_CLOCK
323 select VERSATILE_FPGA_IRQ
325 This enables support for ARM Ltd Versatile board.
329 select ARCH_REQUIRE_GPIOLIB
333 select NEED_MACH_GPIO_H
334 select NEED_MACH_IO_H if PCCARD
336 select PINCTRL_AT91 if USE_OF
338 This enables support for systems based on Atmel
339 AT91RM9200 and AT91SAM9* processors.
342 bool "Broadcom BCM2835 family"
343 select ARCH_REQUIRE_GPIOLIB
345 select ARM_ERRATA_411920
346 select ARM_TIMER_SP804
351 select GENERIC_CLOCKEVENTS
352 select MULTI_IRQ_HANDLER
354 select PINCTRL_BCM2835
358 This enables support for the Broadcom BCM2835 SoC. This SoC is
359 use in the Raspberry Pi, and Roku 2 devices.
362 bool "Cavium Networks CNS3XXX family"
365 select GENERIC_CLOCKEVENTS
366 select MIGHT_HAVE_CACHE_L2X0
367 select MIGHT_HAVE_PCI
368 select PCI_DOMAINS if PCI
370 Support for Cavium Networks CNS3XXX platform.
373 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
374 select ARCH_REQUIRE_GPIOLIB
379 select GENERIC_CLOCKEVENTS
380 select MULTI_IRQ_HANDLER
381 select NEED_MACH_MEMORY_H
384 Support for Cirrus Logic 711x/721x/731x based boards.
387 bool "Cortina Systems Gemini"
388 select ARCH_REQUIRE_GPIOLIB
389 select ARCH_USES_GETTIMEOFFSET
392 Support for the Cortina Systems Gemini family SoCs
396 select ARCH_REQUIRE_GPIOLIB
399 select GENERIC_CLOCKEVENTS
400 select GENERIC_IRQ_CHIP
401 select MIGHT_HAVE_CACHE_L2X0
407 Support for CSR SiRFprimaII/Marco/Polo platforms
411 select ARCH_USES_GETTIMEOFFSET
414 select NEED_MACH_IO_H
415 select NEED_MACH_MEMORY_H
418 This is an evaluation board for the StrongARM processor available
419 from Digital. It has limited hardware on-board, including an
420 Ethernet interface, two PCMCIA sockets, two serial ports and a
425 select ARCH_HAS_HOLES_MEMORYMODEL
426 select ARCH_REQUIRE_GPIOLIB
427 select ARCH_USES_GETTIMEOFFSET
432 select NEED_MACH_MEMORY_H
434 This enables support for the Cirrus EP93xx series of CPUs.
436 config ARCH_FOOTBRIDGE
440 select GENERIC_CLOCKEVENTS
442 select NEED_MACH_IO_H if !MMU
443 select NEED_MACH_MEMORY_H
445 Support for systems based on the DC21285 companion chip
446 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
449 bool "Freescale MXS-based"
450 select ARCH_REQUIRE_GPIOLIB
454 select GENERIC_CLOCKEVENTS
455 select HAVE_CLK_PREPARE
456 select MULTI_IRQ_HANDLER
461 Support for Freescale MXS-based family of processors
464 bool "Hilscher NetX based"
468 select GENERIC_CLOCKEVENTS
470 This enables support for systems based on the Hilscher NetX Soc
473 bool "Hynix HMS720x-based"
474 select ARCH_USES_GETTIMEOFFSET
478 This enables support for systems based on the Hynix HMS720x
483 select ARCH_SUPPORTS_MSI
485 select NEED_MACH_MEMORY_H
486 select NEED_RET_TO_USER
491 Support for Intel's IOP13XX (XScale) family of processors.
496 select ARCH_REQUIRE_GPIOLIB
498 select NEED_MACH_GPIO_H
499 select NEED_RET_TO_USER
503 Support for Intel's 80219 and IOP32X (XScale) family of
509 select ARCH_REQUIRE_GPIOLIB
511 select NEED_MACH_GPIO_H
512 select NEED_RET_TO_USER
516 Support for Intel's IOP33X (XScale) family of processors.
521 select ARCH_HAS_DMA_SET_COHERENT_MASK
522 select ARCH_REQUIRE_GPIOLIB
525 select DMABOUNCE if PCI
526 select GENERIC_CLOCKEVENTS
527 select MIGHT_HAVE_PCI
528 select NEED_MACH_IO_H
530 Support for Intel's IXP4XX (XScale) family of processors.
534 select ARCH_REQUIRE_GPIOLIB
535 select COMMON_CLK_DOVE
537 select GENERIC_CLOCKEVENTS
538 select MIGHT_HAVE_PCI
541 select PLAT_ORION_LEGACY
542 select USB_ARCH_HAS_EHCI
544 Support for the Marvell Dove SoC 88AP510
547 bool "Marvell Kirkwood"
548 select ARCH_REQUIRE_GPIOLIB
550 select GENERIC_CLOCKEVENTS
554 select PINCTRL_KIRKWOOD
555 select PLAT_ORION_LEGACY
557 Support for the following Marvell Kirkwood series SoCs:
558 88F6180, 88F6192 and 88F6281.
561 bool "Marvell MV78xx0"
562 select ARCH_REQUIRE_GPIOLIB
564 select GENERIC_CLOCKEVENTS
566 select PLAT_ORION_LEGACY
568 Support for the following Marvell MV78xx0 series SoCs:
574 select ARCH_REQUIRE_GPIOLIB
576 select GENERIC_CLOCKEVENTS
578 select PLAT_ORION_LEGACY
580 Support for the following Marvell Orion 5x series SoCs:
581 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
582 Orion-2 (5281), Orion-1-90 (6183).
585 bool "Marvell PXA168/910/MMP2"
587 select ARCH_REQUIRE_GPIOLIB
589 select GENERIC_ALLOCATOR
590 select GENERIC_CLOCKEVENTS
593 select NEED_MACH_GPIO_H
598 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
601 bool "Micrel/Kendin KS8695"
602 select ARCH_REQUIRE_GPIOLIB
605 select GENERIC_CLOCKEVENTS
606 select NEED_MACH_MEMORY_H
608 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
609 System-on-Chip devices.
612 bool "Nuvoton W90X900 CPU"
613 select ARCH_REQUIRE_GPIOLIB
617 select GENERIC_CLOCKEVENTS
619 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
620 At present, the w90x900 has been renamed nuc900, regarding
621 the ARM series product line, you can login the following
622 link address to know more.
624 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
625 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
629 select ARCH_REQUIRE_GPIOLIB
634 select GENERIC_CLOCKEVENTS
637 select USB_ARCH_HAS_OHCI
640 Support for the NXP LPC32XX family of processors
644 select ARCH_HAS_CPUFREQ
645 select ARCH_REQUIRE_GPIOLIB
650 select GENERIC_CLOCKEVENTS
653 select MIGHT_HAVE_CACHE_L2X0
657 This enables support for NVIDIA Tegra based systems (Tegra APX,
658 Tegra 6xx and Tegra 2 series).
661 bool "PXA2xx/PXA3xx-based"
663 select ARCH_HAS_CPUFREQ
665 select ARCH_REQUIRE_GPIOLIB
666 select ARM_CPU_SUSPEND if PM
670 select GENERIC_CLOCKEVENTS
673 select MULTI_IRQ_HANDLER
674 select NEED_MACH_GPIO_H
678 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
682 select ARCH_REQUIRE_GPIOLIB
684 select GENERIC_CLOCKEVENTS
687 Support for Qualcomm MSM/QSD based systems. This runs on the
688 apps processor of the MSM/QSD and depends on a shared memory
689 interface to the modem processor which runs the baseband
690 stack and controls some vital subsystems
691 (clock and power control, etc).
694 bool "Renesas SH-Mobile / R-Mobile"
696 select GENERIC_CLOCKEVENTS
698 select HAVE_MACH_CLKDEV
700 select MIGHT_HAVE_CACHE_L2X0
701 select MULTI_IRQ_HANDLER
702 select NEED_MACH_MEMORY_H
705 select PM_GENERIC_DOMAINS if PM
708 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
713 select ARCH_MAY_HAVE_PC_FDC
714 select ARCH_SPARSEMEM_ENABLE
715 select ARCH_USES_GETTIMEOFFSET
718 select HAVE_PATA_PLATFORM
720 select NEED_MACH_IO_H
721 select NEED_MACH_MEMORY_H
724 On the Acorn Risc-PC, Linux can support the internal IDE disk and
725 CD-ROM interface, serial and parallel port, and the floppy drive.
729 select ARCH_HAS_CPUFREQ
731 select ARCH_REQUIRE_GPIOLIB
732 select ARCH_SPARSEMEM_ENABLE
737 select GENERIC_CLOCKEVENTS
740 select NEED_MACH_GPIO_H
741 select NEED_MACH_MEMORY_H
744 Support for StrongARM 11x0 based boards.
747 bool "Samsung S3C24XX SoCs"
748 select ARCH_HAS_CPUFREQ
749 select ARCH_USES_GETTIMEOFFSET
752 select HAVE_S3C2410_I2C if I2C
753 select HAVE_S3C2410_WATCHDOG if WATCHDOG
754 select HAVE_S3C_RTC if RTC_CLASS
755 select NEED_MACH_GPIO_H
756 select NEED_MACH_IO_H
758 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
759 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
760 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
761 Samsung SMDK2410 development board (and derivatives).
764 bool "Samsung S3C64XX"
765 select ARCH_HAS_CPUFREQ
766 select ARCH_REQUIRE_GPIOLIB
767 select ARCH_USES_GETTIMEOFFSET
772 select HAVE_S3C2410_I2C if I2C
773 select HAVE_S3C2410_WATCHDOG if WATCHDOG
775 select NEED_MACH_GPIO_H
779 select S3C_GPIO_TRACK
780 select SAMSUNG_CLKSRC
781 select SAMSUNG_GPIOLIB_4BIT
782 select SAMSUNG_IRQ_VIC_TIMER
783 select USB_ARCH_HAS_OHCI
785 Samsung S3C64XX series based systems
788 bool "Samsung S5P6440 S5P6450"
792 select GENERIC_CLOCKEVENTS
794 select HAVE_S3C2410_I2C if I2C
795 select HAVE_S3C2410_WATCHDOG if WATCHDOG
796 select HAVE_S3C_RTC if RTC_CLASS
797 select NEED_MACH_GPIO_H
799 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
803 bool "Samsung S5PC100"
804 select ARCH_USES_GETTIMEOFFSET
808 select HAVE_S3C2410_I2C if I2C
809 select HAVE_S3C2410_WATCHDOG if WATCHDOG
810 select HAVE_S3C_RTC if RTC_CLASS
811 select NEED_MACH_GPIO_H
813 Samsung S5PC100 series based systems
816 bool "Samsung S5PV210/S5PC110"
817 select ARCH_HAS_CPUFREQ
818 select ARCH_HAS_HOLES_MEMORYMODEL
819 select ARCH_SPARSEMEM_ENABLE
823 select GENERIC_CLOCKEVENTS
825 select HAVE_S3C2410_I2C if I2C
826 select HAVE_S3C2410_WATCHDOG if WATCHDOG
827 select HAVE_S3C_RTC if RTC_CLASS
828 select NEED_MACH_GPIO_H
829 select NEED_MACH_MEMORY_H
831 Samsung S5PV210/S5PC110 series based systems
834 bool "Samsung EXYNOS"
835 select ARCH_HAS_CPUFREQ
836 select ARCH_HAS_HOLES_MEMORYMODEL
837 select ARCH_SPARSEMEM_ENABLE
840 select GENERIC_CLOCKEVENTS
842 select HAVE_S3C2410_I2C if I2C
843 select HAVE_S3C2410_WATCHDOG if WATCHDOG
844 select HAVE_S3C_RTC if RTC_CLASS
845 select NEED_MACH_GPIO_H
846 select NEED_MACH_MEMORY_H
848 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
852 select ARCH_USES_GETTIMEOFFSET
856 select NEED_MACH_MEMORY_H
860 Support for the StrongARM based Digital DNARD machine, also known
861 as "Shark" (<http://www.shark-linux.de/shark.html>).
864 bool "ST-Ericsson U300 Series"
866 select ARCH_REQUIRE_GPIOLIB
868 select ARM_PATCH_PHYS_VIRT
874 select GENERIC_CLOCKEVENTS
878 Support for ST-Ericsson U300 series mobile platforms.
881 bool "ST-Ericsson U8500 Series"
883 select ARCH_HAS_CPUFREQ
884 select ARCH_REQUIRE_GPIOLIB
888 select GENERIC_CLOCKEVENTS
890 select MIGHT_HAVE_CACHE_L2X0
893 Support for ST-Ericsson's Ux500 architecture
896 bool "STMicroelectronics Nomadik"
897 select ARCH_REQUIRE_GPIOLIB
900 select CLKSRC_NOMADIK_MTU
903 select GENERIC_CLOCKEVENTS
904 select MIGHT_HAVE_CACHE_L2X0
907 select PINCTRL_STN8815
910 Support for the Nomadik platform by ST-Ericsson
914 select ARCH_HAS_CPUFREQ
915 select ARCH_REQUIRE_GPIOLIB
920 select GENERIC_CLOCKEVENTS
923 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
927 select ARCH_HAS_HOLES_MEMORYMODEL
928 select ARCH_REQUIRE_GPIOLIB
930 select GENERIC_ALLOCATOR
931 select GENERIC_CLOCKEVENTS
932 select GENERIC_IRQ_CHIP
934 select NEED_MACH_GPIO_H
938 Support for TI's DaVinci platform.
943 select ARCH_HAS_CPUFREQ
944 select ARCH_HAS_HOLES_MEMORYMODEL
946 select ARCH_REQUIRE_GPIOLIB
949 select GENERIC_CLOCKEVENTS
950 select GENERIC_IRQ_CHIP
954 select NEED_MACH_IO_H if PCCARD
955 select NEED_MACH_MEMORY_H
957 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
961 menu "Multiple platform selection"
962 depends on ARCH_MULTIPLATFORM
964 comment "CPU Core family selection"
967 bool "ARMv4 based platforms (FA526, StrongARM)"
968 depends on !ARCH_MULTI_V6_V7
969 select ARCH_MULTI_V4_V5
971 config ARCH_MULTI_V4T
972 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
973 depends on !ARCH_MULTI_V6_V7
974 select ARCH_MULTI_V4_V5
977 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
978 depends on !ARCH_MULTI_V6_V7
979 select ARCH_MULTI_V4_V5
981 config ARCH_MULTI_V4_V5
985 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
986 select ARCH_MULTI_V6_V7
990 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
992 select ARCH_MULTI_V6_V7
996 config ARCH_MULTI_V6_V7
999 config ARCH_MULTI_CPU_AUTO
1000 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1001 select ARCH_MULTI_V5
1006 # This is sorted alphabetically by mach-* pathname. However, plat-*
1007 # Kconfigs may be included either alphabetically (according to the
1008 # plat- suffix) or along side the corresponding mach-* source.
1010 source "arch/arm/mach-mvebu/Kconfig"
1012 source "arch/arm/mach-at91/Kconfig"
1014 source "arch/arm/mach-bcm/Kconfig"
1016 source "arch/arm/mach-clps711x/Kconfig"
1018 source "arch/arm/mach-cns3xxx/Kconfig"
1020 source "arch/arm/mach-davinci/Kconfig"
1022 source "arch/arm/mach-dove/Kconfig"
1024 source "arch/arm/mach-ep93xx/Kconfig"
1026 source "arch/arm/mach-footbridge/Kconfig"
1028 source "arch/arm/mach-gemini/Kconfig"
1030 source "arch/arm/mach-h720x/Kconfig"
1032 source "arch/arm/mach-highbank/Kconfig"
1034 source "arch/arm/mach-integrator/Kconfig"
1036 source "arch/arm/mach-iop32x/Kconfig"
1038 source "arch/arm/mach-iop33x/Kconfig"
1040 source "arch/arm/mach-iop13xx/Kconfig"
1042 source "arch/arm/mach-ixp4xx/Kconfig"
1044 source "arch/arm/mach-kirkwood/Kconfig"
1046 source "arch/arm/mach-ks8695/Kconfig"
1048 source "arch/arm/mach-msm/Kconfig"
1050 source "arch/arm/mach-mv78xx0/Kconfig"
1052 source "arch/arm/mach-imx/Kconfig"
1054 source "arch/arm/mach-mxs/Kconfig"
1056 source "arch/arm/mach-netx/Kconfig"
1058 source "arch/arm/mach-nomadik/Kconfig"
1060 source "arch/arm/plat-omap/Kconfig"
1062 source "arch/arm/mach-omap1/Kconfig"
1064 source "arch/arm/mach-omap2/Kconfig"
1066 source "arch/arm/mach-orion5x/Kconfig"
1068 source "arch/arm/mach-picoxcell/Kconfig"
1070 source "arch/arm/mach-pxa/Kconfig"
1071 source "arch/arm/plat-pxa/Kconfig"
1073 source "arch/arm/mach-mmp/Kconfig"
1075 source "arch/arm/mach-realview/Kconfig"
1077 source "arch/arm/mach-sa1100/Kconfig"
1079 source "arch/arm/plat-samsung/Kconfig"
1081 source "arch/arm/mach-socfpga/Kconfig"
1083 source "arch/arm/plat-spear/Kconfig"
1085 source "arch/arm/mach-s3c24xx/Kconfig"
1088 source "arch/arm/mach-s3c64xx/Kconfig"
1091 source "arch/arm/mach-s5p64x0/Kconfig"
1093 source "arch/arm/mach-s5pc100/Kconfig"
1095 source "arch/arm/mach-s5pv210/Kconfig"
1097 source "arch/arm/mach-exynos/Kconfig"
1099 source "arch/arm/mach-shmobile/Kconfig"
1101 source "arch/arm/mach-sunxi/Kconfig"
1103 source "arch/arm/mach-prima2/Kconfig"
1105 source "arch/arm/mach-tegra/Kconfig"
1107 source "arch/arm/mach-u300/Kconfig"
1109 source "arch/arm/mach-ux500/Kconfig"
1111 source "arch/arm/mach-versatile/Kconfig"
1113 source "arch/arm/mach-vexpress/Kconfig"
1114 source "arch/arm/plat-versatile/Kconfig"
1116 source "arch/arm/mach-virt/Kconfig"
1118 source "arch/arm/mach-vt8500/Kconfig"
1120 source "arch/arm/mach-w90x900/Kconfig"
1122 source "arch/arm/mach-zynq/Kconfig"
1124 # Definitions to make life easier
1130 select GENERIC_CLOCKEVENTS
1136 select GENERIC_IRQ_CHIP
1139 config PLAT_ORION_LEGACY
1146 config PLAT_VERSATILE
1149 config ARM_TIMER_SP804
1152 select HAVE_SCHED_CLOCK
1154 source arch/arm/mm/Kconfig
1158 default 16 if ARCH_EP93XX
1162 bool "Enable iWMMXt support"
1163 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1164 default y if PXA27x || PXA3xx || ARCH_MMP
1166 Enable support for iWMMXt context switching at run time if
1167 running on a CPU that supports it.
1171 depends on CPU_XSCALE
1174 config MULTI_IRQ_HANDLER
1177 Allow each machine to specify it's own IRQ handler at run time.
1180 source "arch/arm/Kconfig-nommu"
1183 config ARM_ERRATA_326103
1184 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1187 Executing a SWP instruction to read-only memory does not set bit 11
1188 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1189 treat the access as a read, preventing a COW from occurring and
1190 causing the faulting task to livelock.
1192 config ARM_ERRATA_411920
1193 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1194 depends on CPU_V6 || CPU_V6K
1196 Invalidation of the Instruction Cache operation can
1197 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1198 It does not affect the MPCore. This option enables the ARM Ltd.
1199 recommended workaround.
1201 config ARM_ERRATA_430973
1202 bool "ARM errata: Stale prediction on replaced interworking branch"
1205 This option enables the workaround for the 430973 Cortex-A8
1206 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1207 interworking branch is replaced with another code sequence at the
1208 same virtual address, whether due to self-modifying code or virtual
1209 to physical address re-mapping, Cortex-A8 does not recover from the
1210 stale interworking branch prediction. This results in Cortex-A8
1211 executing the new code sequence in the incorrect ARM or Thumb state.
1212 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1213 and also flushes the branch target cache at every context switch.
1214 Note that setting specific bits in the ACTLR register may not be
1215 available in non-secure mode.
1217 config ARM_ERRATA_458693
1218 bool "ARM errata: Processor deadlock when a false hazard is created"
1220 depends on !ARCH_MULTIPLATFORM
1222 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1223 erratum. For very specific sequences of memory operations, it is
1224 possible for a hazard condition intended for a cache line to instead
1225 be incorrectly associated with a different cache line. This false
1226 hazard might then cause a processor deadlock. The workaround enables
1227 the L1 caching of the NEON accesses and disables the PLD instruction
1228 in the ACTLR register. Note that setting specific bits in the ACTLR
1229 register may not be available in non-secure mode.
1231 config ARM_ERRATA_460075
1232 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1234 depends on !ARCH_MULTIPLATFORM
1236 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1237 erratum. Any asynchronous access to the L2 cache may encounter a
1238 situation in which recent store transactions to the L2 cache are lost
1239 and overwritten with stale memory contents from external memory. The
1240 workaround disables the write-allocate mode for the L2 cache via the
1241 ACTLR register. Note that setting specific bits in the ACTLR register
1242 may not be available in non-secure mode.
1244 config ARM_ERRATA_742230
1245 bool "ARM errata: DMB operation may be faulty"
1246 depends on CPU_V7 && SMP
1247 depends on !ARCH_MULTIPLATFORM
1249 This option enables the workaround for the 742230 Cortex-A9
1250 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1251 between two write operations may not ensure the correct visibility
1252 ordering of the two writes. This workaround sets a specific bit in
1253 the diagnostic register of the Cortex-A9 which causes the DMB
1254 instruction to behave as a DSB, ensuring the correct behaviour of
1257 config ARM_ERRATA_742231
1258 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1259 depends on CPU_V7 && SMP
1260 depends on !ARCH_MULTIPLATFORM
1262 This option enables the workaround for the 742231 Cortex-A9
1263 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1264 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1265 accessing some data located in the same cache line, may get corrupted
1266 data due to bad handling of the address hazard when the line gets
1267 replaced from one of the CPUs at the same time as another CPU is
1268 accessing it. This workaround sets specific bits in the diagnostic
1269 register of the Cortex-A9 which reduces the linefill issuing
1270 capabilities of the processor.
1272 config PL310_ERRATA_588369
1273 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1274 depends on CACHE_L2X0
1276 The PL310 L2 cache controller implements three types of Clean &
1277 Invalidate maintenance operations: by Physical Address
1278 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1279 They are architecturally defined to behave as the execution of a
1280 clean operation followed immediately by an invalidate operation,
1281 both performing to the same memory location. This functionality
1282 is not correctly implemented in PL310 as clean lines are not
1283 invalidated as a result of these operations.
1285 config ARM_ERRATA_720789
1286 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1289 This option enables the workaround for the 720789 Cortex-A9 (prior to
1290 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1291 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1292 As a consequence of this erratum, some TLB entries which should be
1293 invalidated are not, resulting in an incoherency in the system page
1294 tables. The workaround changes the TLB flushing routines to invalidate
1295 entries regardless of the ASID.
1297 config PL310_ERRATA_727915
1298 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1299 depends on CACHE_L2X0
1301 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1302 operation (offset 0x7FC). This operation runs in background so that
1303 PL310 can handle normal accesses while it is in progress. Under very
1304 rare circumstances, due to this erratum, write data can be lost when
1305 PL310 treats a cacheable write transaction during a Clean &
1306 Invalidate by Way operation.
1308 config ARM_ERRATA_743622
1309 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1311 depends on !ARCH_MULTIPLATFORM
1313 This option enables the workaround for the 743622 Cortex-A9
1314 (r2p*) erratum. Under very rare conditions, a faulty
1315 optimisation in the Cortex-A9 Store Buffer may lead to data
1316 corruption. This workaround sets a specific bit in the diagnostic
1317 register of the Cortex-A9 which disables the Store Buffer
1318 optimisation, preventing the defect from occurring. This has no
1319 visible impact on the overall performance or power consumption of the
1322 config ARM_ERRATA_751472
1323 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1325 depends on !ARCH_MULTIPLATFORM
1327 This option enables the workaround for the 751472 Cortex-A9 (prior
1328 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1329 completion of a following broadcasted operation if the second
1330 operation is received by a CPU before the ICIALLUIS has completed,
1331 potentially leading to corrupted entries in the cache or TLB.
1333 config PL310_ERRATA_753970
1334 bool "PL310 errata: cache sync operation may be faulty"
1335 depends on CACHE_PL310
1337 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1339 Under some condition the effect of cache sync operation on
1340 the store buffer still remains when the operation completes.
1341 This means that the store buffer is always asked to drain and
1342 this prevents it from merging any further writes. The workaround
1343 is to replace the normal offset of cache sync operation (0x730)
1344 by another offset targeting an unmapped PL310 register 0x740.
1345 This has the same effect as the cache sync operation: store buffer
1346 drain and waiting for all buffers empty.
1348 config ARM_ERRATA_754322
1349 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1352 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1353 r3p*) erratum. A speculative memory access may cause a page table walk
1354 which starts prior to an ASID switch but completes afterwards. This
1355 can populate the micro-TLB with a stale entry which may be hit with
1356 the new ASID. This workaround places two dsb instructions in the mm
1357 switching code so that no page table walks can cross the ASID switch.
1359 config ARM_ERRATA_754327
1360 bool "ARM errata: no automatic Store Buffer drain"
1361 depends on CPU_V7 && SMP
1363 This option enables the workaround for the 754327 Cortex-A9 (prior to
1364 r2p0) erratum. The Store Buffer does not have any automatic draining
1365 mechanism and therefore a livelock may occur if an external agent
1366 continuously polls a memory location waiting to observe an update.
1367 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1368 written polling loops from denying visibility of updates to memory.
1370 config ARM_ERRATA_364296
1371 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1372 depends on CPU_V6 && !SMP
1374 This options enables the workaround for the 364296 ARM1136
1375 r0p2 erratum (possible cache data corruption with
1376 hit-under-miss enabled). It sets the undocumented bit 31 in
1377 the auxiliary control register and the FI bit in the control
1378 register, thus disabling hit-under-miss without putting the
1379 processor into full low interrupt latency mode. ARM11MPCore
1382 config ARM_ERRATA_764369
1383 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1384 depends on CPU_V7 && SMP
1386 This option enables the workaround for erratum 764369
1387 affecting Cortex-A9 MPCore with two or more processors (all
1388 current revisions). Under certain timing circumstances, a data
1389 cache line maintenance operation by MVA targeting an Inner
1390 Shareable memory region may fail to proceed up to either the
1391 Point of Coherency or to the Point of Unification of the
1392 system. This workaround adds a DSB instruction before the
1393 relevant cache maintenance functions and sets a specific bit
1394 in the diagnostic control register of the SCU.
1396 config PL310_ERRATA_769419
1397 bool "PL310 errata: no automatic Store Buffer drain"
1398 depends on CACHE_L2X0
1400 On revisions of the PL310 prior to r3p2, the Store Buffer does
1401 not automatically drain. This can cause normal, non-cacheable
1402 writes to be retained when the memory system is idle, leading
1403 to suboptimal I/O performance for drivers using coherent DMA.
1404 This option adds a write barrier to the cpu_idle loop so that,
1405 on systems with an outer cache, the store buffer is drained
1408 config ARM_ERRATA_775420
1409 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1412 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1413 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1414 operation aborts with MMU exception, it might cause the processor
1415 to deadlock. This workaround puts DSB before executing ISB if
1416 an abort may occur on cache maintenance.
1420 source "arch/arm/common/Kconfig"
1430 Find out whether you have ISA slots on your motherboard. ISA is the
1431 name of a bus system, i.e. the way the CPU talks to the other stuff
1432 inside your box. Other bus systems are PCI, EISA, MicroChannel
1433 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1434 newer boards don't support it. If you have ISA, say Y, otherwise N.
1436 # Select ISA DMA controller support
1441 config ARCH_NO_VIRT_TO_BUS
1443 depends on !ARCH_RPC && !ARCH_NETWINDER && !ARCH_SHARK
1445 # Select ISA DMA interface
1450 bool "PCI support" if MIGHT_HAVE_PCI
1452 Find out whether you have a PCI motherboard. PCI is the name of a
1453 bus system, i.e. the way the CPU talks to the other stuff inside
1454 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1455 VESA. If you have PCI, say Y, otherwise N.
1461 config PCI_NANOENGINE
1462 bool "BSE nanoEngine PCI support"
1463 depends on SA1100_NANOENGINE
1465 Enable PCI on the BSE nanoEngine board.
1470 # Select the host bridge type
1471 config PCI_HOST_VIA82C505
1473 depends on PCI && ARCH_SHARK
1476 config PCI_HOST_ITE8152
1478 depends on PCI && MACH_ARMCORE
1482 source "drivers/pci/Kconfig"
1484 source "drivers/pcmcia/Kconfig"
1488 menu "Kernel Features"
1493 This option should be selected by machines which have an SMP-
1496 The only effect of this option is to make the SMP-related
1497 options available to the user for configuration.
1500 bool "Symmetric Multi-Processing"
1501 depends on CPU_V6K || CPU_V7
1502 depends on GENERIC_CLOCKEVENTS
1505 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1506 select USE_GENERIC_SMP_HELPERS
1508 This enables support for systems with more than one CPU. If you have
1509 a system with only one CPU, like most personal computers, say N. If
1510 you have a system with more than one CPU, say Y.
1512 If you say N here, the kernel will run on single and multiprocessor
1513 machines, but will use only one CPU of a multiprocessor machine. If
1514 you say Y here, the kernel will run on many, but not all, single
1515 processor machines. On a single processor machine, the kernel will
1516 run faster if you say N here.
1518 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1519 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1520 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1522 If you don't know what to do here, say N.
1525 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1526 depends on SMP && !XIP_KERNEL
1529 SMP kernels contain instructions which fail on non-SMP processors.
1530 Enabling this option allows the kernel to modify itself to make
1531 these instructions safe. Disabling it allows about 1K of space
1534 If you don't know what to do here, say Y.
1536 config ARM_CPU_TOPOLOGY
1537 bool "Support cpu topology definition"
1538 depends on SMP && CPU_V7
1541 Support ARM cpu topology definition. The MPIDR register defines
1542 affinity between processors which is then used to describe the cpu
1543 topology of an ARM System.
1546 bool "Multi-core scheduler support"
1547 depends on ARM_CPU_TOPOLOGY
1549 Multi-core scheduler support improves the CPU scheduler's decision
1550 making when dealing with multi-core CPU chips at a cost of slightly
1551 increased overhead in some places. If unsure say N here.
1554 bool "SMT scheduler support"
1555 depends on ARM_CPU_TOPOLOGY
1557 Improves the CPU scheduler's decision making when dealing with
1558 MultiThreading at a cost of slightly increased overhead in some
1559 places. If unsure say N here.
1564 This option enables support for the ARM system coherency unit
1566 config HAVE_ARM_ARCH_TIMER
1567 bool "Architected timer support"
1569 select ARM_ARCH_TIMER
1571 This option enables support for the ARM architected timer
1577 This options enables support for the ARM timer and watchdog unit
1580 prompt "Memory split"
1583 Select the desired split between kernel and user memory.
1585 If you are not absolutely sure what you are doing, leave this
1589 bool "3G/1G user/kernel split"
1591 bool "2G/2G user/kernel split"
1593 bool "1G/3G user/kernel split"
1598 default 0x40000000 if VMSPLIT_1G
1599 default 0x80000000 if VMSPLIT_2G
1603 int "Maximum number of CPUs (2-32)"
1609 bool "Support for hot-pluggable CPUs"
1610 depends on SMP && HOTPLUG
1612 Say Y here to experiment with turning CPUs off and on. CPUs
1613 can be controlled through /sys/devices/system/cpu.
1616 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1619 Say Y here if you want Linux to communicate with system firmware
1620 implementing the PSCI specification for CPU-centric power
1621 management operations described in ARM document number ARM DEN
1622 0022A ("Power State Coordination Interface System Software on
1626 bool "Use local timer interrupts"
1629 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1631 Enable support for local timers on SMP platforms, rather then the
1632 legacy IPI broadcast method. Local timers allows the system
1633 accounting to be spread across the timer interval, preventing a
1634 "thundering herd" at every timer tick.
1638 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1639 default 355 if ARCH_U8500
1640 default 264 if MACH_H4700
1641 default 512 if SOC_OMAP5
1642 default 288 if ARCH_VT8500 || ARCH_SUNXI
1645 Maximum number of GPIOs in the system.
1647 If unsure, leave the default value.
1649 source kernel/Kconfig.preempt
1653 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1654 ARCH_S5PV210 || ARCH_EXYNOS4
1655 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1656 default AT91_TIMER_HZ if ARCH_AT91
1657 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1661 def_bool HIGH_RES_TIMERS
1663 config THUMB2_KERNEL
1664 bool "Compile the kernel in Thumb-2 mode"
1665 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1667 select ARM_ASM_UNIFIED
1670 By enabling this option, the kernel will be compiled in
1671 Thumb-2 mode. A compiler/assembler that understand the unified
1672 ARM-Thumb syntax is needed.
1676 config THUMB2_AVOID_R_ARM_THM_JUMP11
1677 bool "Work around buggy Thumb-2 short branch relocations in gas"
1678 depends on THUMB2_KERNEL && MODULES
1681 Various binutils versions can resolve Thumb-2 branches to
1682 locally-defined, preemptible global symbols as short-range "b.n"
1683 branch instructions.
1685 This is a problem, because there's no guarantee the final
1686 destination of the symbol, or any candidate locations for a
1687 trampoline, are within range of the branch. For this reason, the
1688 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1689 relocation in modules at all, and it makes little sense to add
1692 The symptom is that the kernel fails with an "unsupported
1693 relocation" error when loading some modules.
1695 Until fixed tools are available, passing
1696 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1697 code which hits this problem, at the cost of a bit of extra runtime
1698 stack usage in some cases.
1700 The problem is described in more detail at:
1701 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1703 Only Thumb-2 kernels are affected.
1705 Unless you are sure your tools don't have this problem, say Y.
1707 config ARM_ASM_UNIFIED
1711 bool "Use the ARM EABI to compile the kernel"
1713 This option allows for the kernel to be compiled using the latest
1714 ARM ABI (aka EABI). This is only useful if you are using a user
1715 space environment that is also compiled with EABI.
1717 Since there are major incompatibilities between the legacy ABI and
1718 EABI, especially with regard to structure member alignment, this
1719 option also changes the kernel syscall calling convention to
1720 disambiguate both ABIs and allow for backward compatibility support
1721 (selected with CONFIG_OABI_COMPAT).
1723 To use this you need GCC version 4.0.0 or later.
1726 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1727 depends on AEABI && !THUMB2_KERNEL
1730 This option preserves the old syscall interface along with the
1731 new (ARM EABI) one. It also provides a compatibility layer to
1732 intercept syscalls that have structure arguments which layout
1733 in memory differs between the legacy ABI and the new ARM EABI
1734 (only for non "thumb" binaries). This option adds a tiny
1735 overhead to all syscalls and produces a slightly larger kernel.
1736 If you know you'll be using only pure EABI user space then you
1737 can say N here. If this option is not selected and you attempt
1738 to execute a legacy ABI binary then the result will be
1739 UNPREDICTABLE (in fact it can be predicted that it won't work
1740 at all). If in doubt say Y.
1742 config ARCH_HAS_HOLES_MEMORYMODEL
1745 config ARCH_SPARSEMEM_ENABLE
1748 config ARCH_SPARSEMEM_DEFAULT
1749 def_bool ARCH_SPARSEMEM_ENABLE
1751 config ARCH_SELECT_MEMORY_MODEL
1752 def_bool ARCH_SPARSEMEM_ENABLE
1754 config HAVE_ARCH_PFN_VALID
1755 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1758 bool "High Memory Support"
1761 The address space of ARM processors is only 4 Gigabytes large
1762 and it has to accommodate user address space, kernel address
1763 space as well as some memory mapped IO. That means that, if you
1764 have a large amount of physical memory and/or IO, not all of the
1765 memory can be "permanently mapped" by the kernel. The physical
1766 memory that is not permanently mapped is called "high memory".
1768 Depending on the selected kernel/user memory split, minimum
1769 vmalloc space and actual amount of RAM, you may not need this
1770 option which should result in a slightly faster kernel.
1775 bool "Allocate 2nd-level pagetables from highmem"
1778 config HW_PERF_EVENTS
1779 bool "Enable hardware performance counter support for perf events"
1780 depends on PERF_EVENTS
1783 Enable hardware performance counter support for perf events. If
1784 disabled, perf events will use software events only.
1788 config FORCE_MAX_ZONEORDER
1789 int "Maximum zone order" if ARCH_SHMOBILE
1790 range 11 64 if ARCH_SHMOBILE
1791 default "12" if SOC_AM33XX
1792 default "9" if SA1111
1795 The kernel memory allocator divides physically contiguous memory
1796 blocks into "zones", where each zone is a power of two number of
1797 pages. This option selects the largest power of two that the kernel
1798 keeps in the memory allocator. If you need to allocate very large
1799 blocks of physically contiguous memory, then you may need to
1800 increase this value.
1802 This config option is actually maximum order plus one. For example,
1803 a value of 11 means that the largest free memory block is 2^10 pages.
1805 config ALIGNMENT_TRAP
1807 depends on CPU_CP15_MMU
1808 default y if !ARCH_EBSA110
1809 select HAVE_PROC_CPU if PROC_FS
1811 ARM processors cannot fetch/store information which is not
1812 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1813 address divisible by 4. On 32-bit ARM processors, these non-aligned
1814 fetch/store instructions will be emulated in software if you say
1815 here, which has a severe performance impact. This is necessary for
1816 correct operation of some network protocols. With an IP-only
1817 configuration it is safe to say N, otherwise say Y.
1819 config UACCESS_WITH_MEMCPY
1820 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1822 default y if CPU_FEROCEON
1824 Implement faster copy_to_user and clear_user methods for CPU
1825 cores where a 8-word STM instruction give significantly higher
1826 memory write throughput than a sequence of individual 32bit stores.
1828 A possible side effect is a slight increase in scheduling latency
1829 between threads sharing the same address space if they invoke
1830 such copy operations with large buffers.
1832 However, if the CPU data cache is using a write-allocate mode,
1833 this option is unlikely to provide any performance gain.
1837 prompt "Enable seccomp to safely compute untrusted bytecode"
1839 This kernel feature is useful for number crunching applications
1840 that may need to compute untrusted bytecode during their
1841 execution. By using pipes or other transports made available to
1842 the process as file descriptors supporting the read/write
1843 syscalls, it's possible to isolate those applications in
1844 their own address space using seccomp. Once seccomp is
1845 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1846 and the task is only allowed to execute a few safe syscalls
1847 defined by each seccomp mode.
1849 config CC_STACKPROTECTOR
1850 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1852 This option turns on the -fstack-protector GCC feature. This
1853 feature puts, at the beginning of functions, a canary value on
1854 the stack just before the return address, and validates
1855 the value just before actually returning. Stack based buffer
1856 overflows (that need to overwrite this return address) now also
1857 overwrite the canary, which gets detected and the attack is then
1858 neutralized via a kernel panic.
1859 This feature requires gcc version 4.2 or above.
1866 bool "Xen guest support on ARM (EXPERIMENTAL)"
1867 depends on ARM && OF
1868 depends on CPU_V7 && !CPU_V6
1870 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1877 bool "Flattened Device Tree support"
1880 select OF_EARLY_FLATTREE
1882 Include support for flattened device tree machine descriptions.
1885 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1888 This is the traditional way of passing data to the kernel at boot
1889 time. If you are solely relying on the flattened device tree (or
1890 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1891 to remove ATAGS support from your kernel binary. If unsure,
1894 config DEPRECATED_PARAM_STRUCT
1895 bool "Provide old way to pass kernel parameters"
1898 This was deprecated in 2001 and announced to live on for 5 years.
1899 Some old boot loaders still use this way.
1901 # Compressed boot loader in ROM. Yes, we really want to ask about
1902 # TEXT and BSS so we preserve their values in the config files.
1903 config ZBOOT_ROM_TEXT
1904 hex "Compressed ROM boot loader base address"
1907 The physical address at which the ROM-able zImage is to be
1908 placed in the target. Platforms which normally make use of
1909 ROM-able zImage formats normally set this to a suitable
1910 value in their defconfig file.
1912 If ZBOOT_ROM is not enabled, this has no effect.
1914 config ZBOOT_ROM_BSS
1915 hex "Compressed ROM boot loader BSS address"
1918 The base address of an area of read/write memory in the target
1919 for the ROM-able zImage which must be available while the
1920 decompressor is running. It must be large enough to hold the
1921 entire decompressed kernel plus an additional 128 KiB.
1922 Platforms which normally make use of ROM-able zImage formats
1923 normally set this to a suitable value in their defconfig file.
1925 If ZBOOT_ROM is not enabled, this has no effect.
1928 bool "Compressed boot loader in ROM/flash"
1929 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1931 Say Y here if you intend to execute your compressed kernel image
1932 (zImage) directly from ROM or flash. If unsure, say N.
1935 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1936 depends on ZBOOT_ROM && ARCH_SH7372
1937 default ZBOOT_ROM_NONE
1939 Include experimental SD/MMC loading code in the ROM-able zImage.
1940 With this enabled it is possible to write the ROM-able zImage
1941 kernel image to an MMC or SD card and boot the kernel straight
1942 from the reset vector. At reset the processor Mask ROM will load
1943 the first part of the ROM-able zImage which in turn loads the
1944 rest the kernel image to RAM.
1946 config ZBOOT_ROM_NONE
1947 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1949 Do not load image from SD or MMC
1951 config ZBOOT_ROM_MMCIF
1952 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1954 Load image from MMCIF hardware block.
1956 config ZBOOT_ROM_SH_MOBILE_SDHI
1957 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1959 Load image from SDHI hardware block
1963 config ARM_APPENDED_DTB
1964 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1965 depends on OF && !ZBOOT_ROM
1967 With this option, the boot code will look for a device tree binary
1968 (DTB) appended to zImage
1969 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1971 This is meant as a backward compatibility convenience for those
1972 systems with a bootloader that can't be upgraded to accommodate
1973 the documented boot protocol using a device tree.
1975 Beware that there is very little in terms of protection against
1976 this option being confused by leftover garbage in memory that might
1977 look like a DTB header after a reboot if no actual DTB is appended
1978 to zImage. Do not leave this option active in a production kernel
1979 if you don't intend to always append a DTB. Proper passing of the
1980 location into r2 of a bootloader provided DTB is always preferable
1983 config ARM_ATAG_DTB_COMPAT
1984 bool "Supplement the appended DTB with traditional ATAG information"
1985 depends on ARM_APPENDED_DTB
1987 Some old bootloaders can't be updated to a DTB capable one, yet
1988 they provide ATAGs with memory configuration, the ramdisk address,
1989 the kernel cmdline string, etc. Such information is dynamically
1990 provided by the bootloader and can't always be stored in a static
1991 DTB. To allow a device tree enabled kernel to be used with such
1992 bootloaders, this option allows zImage to extract the information
1993 from the ATAG list and store it at run time into the appended DTB.
1996 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1997 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1999 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2000 bool "Use bootloader kernel arguments if available"
2002 Uses the command-line options passed by the boot loader instead of
2003 the device tree bootargs property. If the boot loader doesn't provide
2004 any, the device tree bootargs property will be used.
2006 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2007 bool "Extend with bootloader kernel arguments"
2009 The command-line arguments provided by the boot loader will be
2010 appended to the the device tree bootargs property.
2015 string "Default kernel command string"
2018 On some architectures (EBSA110 and CATS), there is currently no way
2019 for the boot loader to pass arguments to the kernel. For these
2020 architectures, you should supply some command-line options at build
2021 time by entering them here. As a minimum, you should specify the
2022 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2025 prompt "Kernel command line type" if CMDLINE != ""
2026 default CMDLINE_FROM_BOOTLOADER
2029 config CMDLINE_FROM_BOOTLOADER
2030 bool "Use bootloader kernel arguments if available"
2032 Uses the command-line options passed by the boot loader. If
2033 the boot loader doesn't provide any, the default kernel command
2034 string provided in CMDLINE will be used.
2036 config CMDLINE_EXTEND
2037 bool "Extend bootloader kernel arguments"
2039 The command-line arguments provided by the boot loader will be
2040 appended to the default kernel command string.
2042 config CMDLINE_FORCE
2043 bool "Always use the default kernel command string"
2045 Always use the default kernel command string, even if the boot
2046 loader passes other arguments to the kernel.
2047 This is useful if you cannot or don't want to change the
2048 command-line options your boot loader passes to the kernel.
2052 bool "Kernel Execute-In-Place from ROM"
2053 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2055 Execute-In-Place allows the kernel to run from non-volatile storage
2056 directly addressable by the CPU, such as NOR flash. This saves RAM
2057 space since the text section of the kernel is not loaded from flash
2058 to RAM. Read-write sections, such as the data section and stack,
2059 are still copied to RAM. The XIP kernel is not compressed since
2060 it has to run directly from flash, so it will take more space to
2061 store it. The flash address used to link the kernel object files,
2062 and for storing it, is configuration dependent. Therefore, if you
2063 say Y here, you must know the proper physical address where to
2064 store the kernel image depending on your own flash memory usage.
2066 Also note that the make target becomes "make xipImage" rather than
2067 "make zImage" or "make Image". The final kernel binary to put in
2068 ROM memory will be arch/arm/boot/xipImage.
2072 config XIP_PHYS_ADDR
2073 hex "XIP Kernel Physical Location"
2074 depends on XIP_KERNEL
2075 default "0x00080000"
2077 This is the physical address in your flash memory the kernel will
2078 be linked for and stored to. This address is dependent on your
2082 bool "Kexec system call (EXPERIMENTAL)"
2083 depends on (!SMP || HOTPLUG_CPU)
2085 kexec is a system call that implements the ability to shutdown your
2086 current kernel, and to start another kernel. It is like a reboot
2087 but it is independent of the system firmware. And like a reboot
2088 you can start any kernel with it, not just Linux.
2090 It is an ongoing process to be certain the hardware in a machine
2091 is properly shutdown, so do not be surprised if this code does not
2092 initially work for you. It may help to enable device hotplugging
2096 bool "Export atags in procfs"
2097 depends on ATAGS && KEXEC
2100 Should the atags used to boot the kernel be exported in an "atags"
2101 file in procfs. Useful with kexec.
2104 bool "Build kdump crash kernel (EXPERIMENTAL)"
2106 Generate crash dump after being started by kexec. This should
2107 be normally only set in special crash dump kernels which are
2108 loaded in the main kernel with kexec-tools into a specially
2109 reserved region and then later executed after a crash by
2110 kdump/kexec. The crash dump kernel must be compiled to a
2111 memory address not used by the main kernel
2113 For more details see Documentation/kdump/kdump.txt
2115 config AUTO_ZRELADDR
2116 bool "Auto calculation of the decompressed kernel image address"
2117 depends on !ZBOOT_ROM && !ARCH_U300
2119 ZRELADDR is the physical address where the decompressed kernel
2120 image will be placed. If AUTO_ZRELADDR is selected, the address
2121 will be determined at run-time by masking the current IP with
2122 0xf8000000. This assumes the zImage being placed in the first 128MB
2123 from start of memory.
2127 menu "CPU Power Management"
2131 source "drivers/cpufreq/Kconfig"
2134 tristate "CPUfreq driver for i.MX CPUs"
2135 depends on ARCH_MXC && CPU_FREQ
2136 select CPU_FREQ_TABLE
2138 This enables the CPUfreq driver for i.MX CPUs.
2140 config CPU_FREQ_SA1100
2143 config CPU_FREQ_SA1110
2146 config CPU_FREQ_INTEGRATOR
2147 tristate "CPUfreq driver for ARM Integrator CPUs"
2148 depends on ARCH_INTEGRATOR && CPU_FREQ
2151 This enables the CPUfreq driver for ARM Integrator CPUs.
2153 For details, take a look at <file:Documentation/cpu-freq>.
2159 depends on CPU_FREQ && ARCH_PXA && PXA25x
2161 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2162 select CPU_FREQ_TABLE
2167 Internal configuration node for common cpufreq on Samsung SoC
2169 config CPU_FREQ_S3C24XX
2170 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2171 depends on ARCH_S3C24XX && CPU_FREQ
2174 This enables the CPUfreq driver for the Samsung S3C24XX family
2177 For details, take a look at <file:Documentation/cpu-freq>.
2181 config CPU_FREQ_S3C24XX_PLL
2182 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2183 depends on CPU_FREQ_S3C24XX
2185 Compile in support for changing the PLL frequency from the
2186 S3C24XX series CPUfreq driver. The PLL takes time to settle
2187 after a frequency change, so by default it is not enabled.
2189 This also means that the PLL tables for the selected CPU(s) will
2190 be built which may increase the size of the kernel image.
2192 config CPU_FREQ_S3C24XX_DEBUG
2193 bool "Debug CPUfreq Samsung driver core"
2194 depends on CPU_FREQ_S3C24XX
2196 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2198 config CPU_FREQ_S3C24XX_IODEBUG
2199 bool "Debug CPUfreq Samsung driver IO timing"
2200 depends on CPU_FREQ_S3C24XX
2202 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2204 config CPU_FREQ_S3C24XX_DEBUGFS
2205 bool "Export debugfs for CPUFreq"
2206 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2208 Export status information via debugfs.
2212 source "drivers/cpuidle/Kconfig"
2216 menu "Floating point emulation"
2218 comment "At least one emulation must be selected"
2221 bool "NWFPE math emulation"
2222 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2224 Say Y to include the NWFPE floating point emulator in the kernel.
2225 This is necessary to run most binaries. Linux does not currently
2226 support floating point hardware so you need to say Y here even if
2227 your machine has an FPA or floating point co-processor podule.
2229 You may say N here if you are going to load the Acorn FPEmulator
2230 early in the bootup.
2233 bool "Support extended precision"
2234 depends on FPE_NWFPE
2236 Say Y to include 80-bit support in the kernel floating-point
2237 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2238 Note that gcc does not generate 80-bit operations by default,
2239 so in most cases this option only enlarges the size of the
2240 floating point emulator without any good reason.
2242 You almost surely want to say N here.
2245 bool "FastFPE math emulation (EXPERIMENTAL)"
2246 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2248 Say Y here to include the FAST floating point emulator in the kernel.
2249 This is an experimental much faster emulator which now also has full
2250 precision for the mantissa. It does not support any exceptions.
2251 It is very simple, and approximately 3-6 times faster than NWFPE.
2253 It should be sufficient for most programs. It may be not suitable
2254 for scientific calculations, but you have to check this for yourself.
2255 If you do not feel you need a faster FP emulation you should better
2259 bool "VFP-format floating point maths"
2260 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2262 Say Y to include VFP support code in the kernel. This is needed
2263 if your hardware includes a VFP unit.
2265 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2266 release notes and additional status information.
2268 Say N if your target does not have VFP hardware.
2276 bool "Advanced SIMD (NEON) Extension support"
2277 depends on VFPv3 && CPU_V7
2279 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2284 menu "Userspace binary formats"
2286 source "fs/Kconfig.binfmt"
2289 tristate "RISC OS personality"
2292 Say Y here to include the kernel code necessary if you want to run
2293 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2294 experimental; if this sounds frightening, say N and sleep in peace.
2295 You can also say M here to compile this support as a module (which
2296 will be called arthur).
2300 menu "Power management options"
2302 source "kernel/power/Kconfig"
2304 config ARCH_SUSPEND_POSSIBLE
2305 depends on !ARCH_S5PC100
2306 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2307 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2310 config ARM_CPU_SUSPEND
2315 source "net/Kconfig"
2317 source "drivers/Kconfig"
2321 source "arch/arm/Kconfig.debug"
2323 source "security/Kconfig"
2325 source "crypto/Kconfig"
2327 source "lib/Kconfig"
2329 source "arch/arm/kvm/Kconfig"