5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
40 config ARM_HAS_SG_CHAIN
49 config SYS_SUPPORTS_APM_EMULATION
52 config HAVE_SCHED_CLOCK
58 config ARCH_USES_GETTIMEOFFSET
62 config GENERIC_CLOCKEVENTS
65 config GENERIC_CLOCKEVENTS_BROADCAST
67 depends on GENERIC_CLOCKEVENTS
76 select GENERIC_ALLOCATOR
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
95 Say Y here if you are building a kernel for an EISA-based machine.
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config HARDIRQS_SW_RESEND
131 config GENERIC_IRQ_PROBE
135 config GENERIC_LOCKBREAK
138 depends on SMP && PREEMPT
140 config RWSEM_GENERIC_SPINLOCK
144 config RWSEM_XCHGADD_ALGORITHM
147 config ARCH_HAS_ILOG2_U32
150 config ARCH_HAS_ILOG2_U64
153 config ARCH_HAS_CPUFREQ
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
160 config ARCH_HAS_CPU_IDLE_WAIT
163 config GENERIC_HWEIGHT
167 config GENERIC_CALIBRATE_DELAY
171 config ARCH_MAY_HAVE_PC_FDC
177 config NEED_DMA_MAP_STATE
180 config GENERIC_ISA_DMA
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime"
199 depends on !XIP_KERNEL && MMU
200 depends on !ARCH_REALVIEW || !SPARSEMEM
202 Patch phys-to-virt and virt-to-phys translation functions at
203 boot and module load time according to the position of the
204 kernel in system memory.
206 This can only be used with non-XIP MMU kernels where the base
207 of physical memory is at a 16MB boundary, or theoretically 64K
208 for the MSM machine class.
210 config ARM_PATCH_PHYS_VIRT_16BIT
212 depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
214 This option extends the physical to virtual translation patching
215 to allow physical memory down to a theoretical minimum of 64K
218 source "init/Kconfig"
220 source "kernel/Kconfig.freezer"
225 bool "MMU-based Paged Memory Management Support"
228 Select if you want MMU-based virtualised addressing space
229 support by paged memory management. If unsure, say 'Y'.
232 # The "ARM system type" choice list is ordered alphabetically by option
233 # text. Please add new entries in the option alphabetic order.
236 prompt "ARM system type"
237 default ARCH_VERSATILE
239 config ARCH_INTEGRATOR
240 bool "ARM Ltd. Integrator family"
242 select ARCH_HAS_CPUFREQ
244 select HAVE_MACH_CLKDEV
246 select GENERIC_CLOCKEVENTS
247 select PLAT_VERSATILE
248 select PLAT_VERSATILE_FPGA_IRQ
250 Support for ARM's Integrator platform.
253 bool "ARM Ltd. RealView family"
256 select HAVE_MACH_CLKDEV
258 select GENERIC_CLOCKEVENTS
259 select ARCH_WANT_OPTIONAL_GPIOLIB
260 select PLAT_VERSATILE
261 select PLAT_VERSATILE_CLCD
262 select ARM_TIMER_SP804
263 select GPIO_PL061 if GPIOLIB
265 This enables support for ARM Ltd RealView boards.
267 config ARCH_VERSATILE
268 bool "ARM Ltd. Versatile family"
272 select HAVE_MACH_CLKDEV
274 select GENERIC_CLOCKEVENTS
275 select ARCH_WANT_OPTIONAL_GPIOLIB
276 select PLAT_VERSATILE
277 select PLAT_VERSATILE_CLCD
278 select PLAT_VERSATILE_FPGA_IRQ
279 select ARM_TIMER_SP804
281 This enables support for ARM Ltd Versatile board.
284 bool "ARM Ltd. Versatile Express family"
285 select ARCH_WANT_OPTIONAL_GPIOLIB
287 select ARM_TIMER_SP804
289 select HAVE_MACH_CLKDEV
290 select GENERIC_CLOCKEVENTS
292 select HAVE_PATA_PLATFORM
294 select PLAT_VERSATILE
295 select PLAT_VERSATILE_CLCD
297 This enables support for the ARM Ltd Versatile Express boards.
301 select ARCH_REQUIRE_GPIOLIB
304 select ARM_PATCH_PHYS_VIRT if MMU
306 This enables support for systems based on the Atmel AT91RM9200,
307 AT91SAM9 and AT91CAP9 processors.
310 bool "Broadcom BCMRING"
314 select ARM_TIMER_SP804
316 select GENERIC_CLOCKEVENTS
317 select ARCH_WANT_OPTIONAL_GPIOLIB
319 Support for Broadcom's BCMRing platform.
322 bool "Cirrus Logic CLPS711x/EP721x-based"
324 select ARCH_USES_GETTIMEOFFSET
326 Support for Cirrus Logic 711x/721x based boards.
329 bool "Cavium Networks CNS3XXX family"
331 select GENERIC_CLOCKEVENTS
333 select MIGHT_HAVE_PCI
334 select PCI_DOMAINS if PCI
336 Support for Cavium Networks CNS3XXX platform.
339 bool "Cortina Systems Gemini"
341 select ARCH_REQUIRE_GPIOLIB
342 select ARCH_USES_GETTIMEOFFSET
344 Support for the Cortina Systems Gemini family SoCs
347 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
351 select GENERIC_CLOCKEVENTS
353 select GENERIC_IRQ_CHIP
357 Support for CSR SiRFSoC ARM Cortex A9 Platform
364 select ARCH_USES_GETTIMEOFFSET
366 This is an evaluation board for the StrongARM processor available
367 from Digital. It has limited hardware on-board, including an
368 Ethernet interface, two PCMCIA sockets, two serial ports and a
377 select ARCH_REQUIRE_GPIOLIB
378 select ARCH_HAS_HOLES_MEMORYMODEL
379 select ARCH_USES_GETTIMEOFFSET
381 This enables support for the Cirrus EP93xx series of CPUs.
383 config ARCH_FOOTBRIDGE
387 select GENERIC_CLOCKEVENTS
389 Support for systems based on the DC21285 companion chip
390 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
393 bool "Freescale MXC/iMX-based"
394 select GENERIC_CLOCKEVENTS
395 select ARCH_REQUIRE_GPIOLIB
398 select GENERIC_IRQ_CHIP
399 select HAVE_SCHED_CLOCK
400 select MULTI_IRQ_HANDLER
402 Support for Freescale MXC/iMX-based family of processors
405 bool "Freescale MXS-based"
406 select GENERIC_CLOCKEVENTS
407 select ARCH_REQUIRE_GPIOLIB
411 Support for Freescale MXS-based family of processors
414 bool "Hilscher NetX based"
418 select GENERIC_CLOCKEVENTS
420 This enables support for systems based on the Hilscher NetX Soc
423 bool "Hynix HMS720x-based"
426 select ARCH_USES_GETTIMEOFFSET
428 This enables support for systems based on the Hynix HMS720x
436 select ARCH_SUPPORTS_MSI
439 Support for Intel's IOP13XX (XScale) family of processors.
447 select ARCH_REQUIRE_GPIOLIB
449 Support for Intel's 80219 and IOP32X (XScale) family of
458 select ARCH_REQUIRE_GPIOLIB
460 Support for Intel's IOP33X (XScale) family of processors.
467 select ARCH_USES_GETTIMEOFFSET
469 Support for Intel's IXP23xx (XScale) family of processors.
472 bool "IXP2400/2800-based"
476 select ARCH_USES_GETTIMEOFFSET
478 Support for Intel's IXP2400/2800 (XScale) family of processors.
486 select GENERIC_CLOCKEVENTS
487 select HAVE_SCHED_CLOCK
488 select MIGHT_HAVE_PCI
489 select DMABOUNCE if PCI
491 Support for Intel's IXP4XX (XScale) family of processors.
497 select ARCH_REQUIRE_GPIOLIB
498 select GENERIC_CLOCKEVENTS
501 Support for the Marvell Dove SoC 88AP510
504 bool "Marvell Kirkwood"
507 select ARCH_REQUIRE_GPIOLIB
508 select GENERIC_CLOCKEVENTS
511 Support for the following Marvell Kirkwood series SoCs:
512 88F6180, 88F6192 and 88F6281.
518 select ARCH_REQUIRE_GPIOLIB
521 select USB_ARCH_HAS_OHCI
524 select GENERIC_CLOCKEVENTS
526 Support for the NXP LPC32XX family of processors
529 bool "Marvell MV78xx0"
532 select ARCH_REQUIRE_GPIOLIB
533 select GENERIC_CLOCKEVENTS
536 Support for the following Marvell MV78xx0 series SoCs:
544 select ARCH_REQUIRE_GPIOLIB
545 select GENERIC_CLOCKEVENTS
548 Support for the following Marvell Orion 5x series SoCs:
549 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
550 Orion-2 (5281), Orion-1-90 (6183).
553 bool "Marvell PXA168/910/MMP2"
555 select ARCH_REQUIRE_GPIOLIB
557 select GENERIC_CLOCKEVENTS
558 select HAVE_SCHED_CLOCK
563 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
566 bool "Micrel/Kendin KS8695"
568 select ARCH_REQUIRE_GPIOLIB
569 select ARCH_USES_GETTIMEOFFSET
571 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
572 System-on-Chip devices.
575 bool "Nuvoton W90X900 CPU"
577 select ARCH_REQUIRE_GPIOLIB
580 select GENERIC_CLOCKEVENTS
582 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
583 At present, the w90x900 has been renamed nuc900, regarding
584 the ARM series product line, you can login the following
585 link address to know more.
587 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
588 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
591 bool "Nuvoton NUC93X CPU"
595 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
596 low-power and high performance MPEG-4/JPEG multimedia controller chip.
603 select GENERIC_CLOCKEVENTS
606 select HAVE_SCHED_CLOCK
607 select ARCH_HAS_CPUFREQ
609 This enables support for NVIDIA Tegra based systems (Tegra APX,
610 Tegra 6xx and Tegra 2 series).
613 bool "Philips Nexperia PNX4008 Mobile"
616 select ARCH_USES_GETTIMEOFFSET
618 This enables support for Philips PNX4008 mobile platform.
621 bool "PXA2xx/PXA3xx-based"
624 select ARCH_HAS_CPUFREQ
627 select ARCH_REQUIRE_GPIOLIB
628 select GENERIC_CLOCKEVENTS
629 select HAVE_SCHED_CLOCK
634 select MULTI_IRQ_HANDLER
636 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
641 select GENERIC_CLOCKEVENTS
642 select ARCH_REQUIRE_GPIOLIB
645 Support for Qualcomm MSM/QSD based systems. This runs on the
646 apps processor of the MSM/QSD and depends on a shared memory
647 interface to the modem processor which runs the baseband
648 stack and controls some vital subsystems
649 (clock and power control, etc).
652 bool "Renesas SH-Mobile / R-Mobile"
655 select HAVE_MACH_CLKDEV
656 select GENERIC_CLOCKEVENTS
659 select MULTI_IRQ_HANDLER
660 select PM_GENERIC_DOMAINS if PM
662 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
669 select ARCH_MAY_HAVE_PC_FDC
670 select HAVE_PATA_PLATFORM
673 select ARCH_SPARSEMEM_ENABLE
674 select ARCH_USES_GETTIMEOFFSET
676 On the Acorn Risc-PC, Linux can support the internal IDE disk and
677 CD-ROM interface, serial and parallel port, and the floppy drive.
684 select ARCH_SPARSEMEM_ENABLE
686 select ARCH_HAS_CPUFREQ
688 select GENERIC_CLOCKEVENTS
690 select HAVE_SCHED_CLOCK
692 select ARCH_REQUIRE_GPIOLIB
694 Support for StrongARM 11x0 based boards.
697 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
699 select ARCH_HAS_CPUFREQ
702 select ARCH_USES_GETTIMEOFFSET
703 select HAVE_S3C2410_I2C if I2C
705 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
706 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
707 the Samsung SMDK2410 development board (and derivatives).
709 Note, the S3C2416 and the S3C2450 are so close that they even share
710 the same SoC ID code. This means that there is no separate machine
711 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
714 bool "Samsung S3C64XX"
721 select ARCH_USES_GETTIMEOFFSET
722 select ARCH_HAS_CPUFREQ
723 select ARCH_REQUIRE_GPIOLIB
724 select SAMSUNG_CLKSRC
725 select SAMSUNG_IRQ_VIC_TIMER
726 select SAMSUNG_IRQ_UART
727 select S3C_GPIO_TRACK
728 select S3C_GPIO_PULL_UPDOWN
729 select S3C_GPIO_CFG_S3C24XX
730 select S3C_GPIO_CFG_S3C64XX
732 select USB_ARCH_HAS_OHCI
733 select SAMSUNG_GPIOLIB_4BIT
734 select HAVE_S3C2410_I2C if I2C
735 select HAVE_S3C2410_WATCHDOG if WATCHDOG
737 Samsung S3C64XX series based systems
740 bool "Samsung S5P6440 S5P6450"
746 select HAVE_S3C2410_WATCHDOG if WATCHDOG
747 select GENERIC_CLOCKEVENTS
748 select HAVE_SCHED_CLOCK
749 select HAVE_S3C2410_I2C if I2C
750 select HAVE_S3C_RTC if RTC_CLASS
752 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
756 bool "Samsung S5PC100"
761 select ARM_L1_CACHE_SHIFT_6
762 select ARCH_USES_GETTIMEOFFSET
763 select HAVE_S3C2410_I2C if I2C
764 select HAVE_S3C_RTC if RTC_CLASS
765 select HAVE_S3C2410_WATCHDOG if WATCHDOG
767 Samsung S5PC100 series based systems
770 bool "Samsung S5PV210/S5PC110"
772 select ARCH_SPARSEMEM_ENABLE
773 select ARCH_HAS_HOLES_MEMORYMODEL
778 select ARM_L1_CACHE_SHIFT_6
779 select ARCH_HAS_CPUFREQ
780 select GENERIC_CLOCKEVENTS
781 select HAVE_SCHED_CLOCK
782 select HAVE_S3C2410_I2C if I2C
783 select HAVE_S3C_RTC if RTC_CLASS
784 select HAVE_S3C2410_WATCHDOG if WATCHDOG
786 Samsung S5PV210/S5PC110 series based systems
789 bool "Samsung EXYNOS4"
791 select ARCH_SPARSEMEM_ENABLE
792 select ARCH_HAS_HOLES_MEMORYMODEL
796 select ARCH_HAS_CPUFREQ
797 select GENERIC_CLOCKEVENTS
798 select HAVE_S3C_RTC if RTC_CLASS
799 select HAVE_S3C2410_I2C if I2C
800 select HAVE_S3C2410_WATCHDOG if WATCHDOG
802 Samsung EXYNOS4 series based systems
811 select ARCH_USES_GETTIMEOFFSET
813 Support for the StrongARM based Digital DNARD machine, also known
814 as "Shark" (<http://www.shark-linux.de/shark.html>).
817 bool "Telechips TCC ARM926-based systems"
822 select GENERIC_CLOCKEVENTS
824 Support for Telechips TCC ARM926-based systems.
827 bool "ST-Ericsson U300 Series"
831 select HAVE_SCHED_CLOCK
835 select GENERIC_CLOCKEVENTS
837 select HAVE_MACH_CLKDEV
840 Support for ST-Ericsson U300 series mobile platforms.
843 bool "ST-Ericsson U8500 Series"
846 select GENERIC_CLOCKEVENTS
848 select ARCH_REQUIRE_GPIOLIB
849 select ARCH_HAS_CPUFREQ
851 Support for ST-Ericsson's Ux500 architecture
854 bool "STMicroelectronics Nomadik"
859 select GENERIC_CLOCKEVENTS
860 select ARCH_REQUIRE_GPIOLIB
862 Support for the Nomadik platform by ST-Ericsson
866 select GENERIC_CLOCKEVENTS
867 select ARCH_REQUIRE_GPIOLIB
871 select GENERIC_ALLOCATOR
872 select GENERIC_IRQ_CHIP
873 select ARCH_HAS_HOLES_MEMORYMODEL
875 Support for TI's DaVinci platform.
880 select ARCH_REQUIRE_GPIOLIB
881 select ARCH_HAS_CPUFREQ
883 select GENERIC_CLOCKEVENTS
884 select HAVE_SCHED_CLOCK
885 select ARCH_HAS_HOLES_MEMORYMODEL
887 Support for TI's OMAP platform (OMAP1/2/3/4).
892 select ARCH_REQUIRE_GPIOLIB
895 select GENERIC_CLOCKEVENTS
898 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
901 bool "VIA/WonderMedia 85xx"
904 select ARCH_HAS_CPUFREQ
905 select GENERIC_CLOCKEVENTS
906 select ARCH_REQUIRE_GPIOLIB
909 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
912 bool "Xilinx Zynq ARM Cortex A9 Platform"
915 select GENERIC_CLOCKEVENTS
922 Support for Xilinx Zynq ARM Cortex A9 Platform
926 # This is sorted alphabetically by mach-* pathname. However, plat-*
927 # Kconfigs may be included either alphabetically (according to the
928 # plat- suffix) or along side the corresponding mach-* source.
930 source "arch/arm/mach-at91/Kconfig"
932 source "arch/arm/mach-bcmring/Kconfig"
934 source "arch/arm/mach-clps711x/Kconfig"
936 source "arch/arm/mach-cns3xxx/Kconfig"
938 source "arch/arm/mach-davinci/Kconfig"
940 source "arch/arm/mach-dove/Kconfig"
942 source "arch/arm/mach-ep93xx/Kconfig"
944 source "arch/arm/mach-footbridge/Kconfig"
946 source "arch/arm/mach-gemini/Kconfig"
948 source "arch/arm/mach-h720x/Kconfig"
950 source "arch/arm/mach-integrator/Kconfig"
952 source "arch/arm/mach-iop32x/Kconfig"
954 source "arch/arm/mach-iop33x/Kconfig"
956 source "arch/arm/mach-iop13xx/Kconfig"
958 source "arch/arm/mach-ixp4xx/Kconfig"
960 source "arch/arm/mach-ixp2000/Kconfig"
962 source "arch/arm/mach-ixp23xx/Kconfig"
964 source "arch/arm/mach-kirkwood/Kconfig"
966 source "arch/arm/mach-ks8695/Kconfig"
968 source "arch/arm/mach-lpc32xx/Kconfig"
970 source "arch/arm/mach-msm/Kconfig"
972 source "arch/arm/mach-mv78xx0/Kconfig"
974 source "arch/arm/plat-mxc/Kconfig"
976 source "arch/arm/mach-mxs/Kconfig"
978 source "arch/arm/mach-netx/Kconfig"
980 source "arch/arm/mach-nomadik/Kconfig"
981 source "arch/arm/plat-nomadik/Kconfig"
983 source "arch/arm/mach-nuc93x/Kconfig"
985 source "arch/arm/plat-omap/Kconfig"
987 source "arch/arm/mach-omap1/Kconfig"
989 source "arch/arm/mach-omap2/Kconfig"
991 source "arch/arm/mach-orion5x/Kconfig"
993 source "arch/arm/mach-pxa/Kconfig"
994 source "arch/arm/plat-pxa/Kconfig"
996 source "arch/arm/mach-mmp/Kconfig"
998 source "arch/arm/mach-realview/Kconfig"
1000 source "arch/arm/mach-sa1100/Kconfig"
1002 source "arch/arm/plat-samsung/Kconfig"
1003 source "arch/arm/plat-s3c24xx/Kconfig"
1004 source "arch/arm/plat-s5p/Kconfig"
1006 source "arch/arm/plat-spear/Kconfig"
1008 source "arch/arm/plat-tcc/Kconfig"
1011 source "arch/arm/mach-s3c2410/Kconfig"
1012 source "arch/arm/mach-s3c2412/Kconfig"
1013 source "arch/arm/mach-s3c2416/Kconfig"
1014 source "arch/arm/mach-s3c2440/Kconfig"
1015 source "arch/arm/mach-s3c2443/Kconfig"
1019 source "arch/arm/mach-s3c64xx/Kconfig"
1022 source "arch/arm/mach-s5p64x0/Kconfig"
1024 source "arch/arm/mach-s5pc100/Kconfig"
1026 source "arch/arm/mach-s5pv210/Kconfig"
1028 source "arch/arm/mach-exynos4/Kconfig"
1030 source "arch/arm/mach-shmobile/Kconfig"
1032 source "arch/arm/mach-tegra/Kconfig"
1034 source "arch/arm/mach-u300/Kconfig"
1036 source "arch/arm/mach-ux500/Kconfig"
1038 source "arch/arm/mach-versatile/Kconfig"
1040 source "arch/arm/mach-vexpress/Kconfig"
1041 source "arch/arm/plat-versatile/Kconfig"
1043 source "arch/arm/mach-vt8500/Kconfig"
1045 source "arch/arm/mach-w90x900/Kconfig"
1047 # Definitions to make life easier
1053 select GENERIC_CLOCKEVENTS
1054 select HAVE_SCHED_CLOCK
1059 select GENERIC_IRQ_CHIP
1060 select HAVE_SCHED_CLOCK
1065 config PLAT_VERSATILE
1068 config ARM_TIMER_SP804
1072 source arch/arm/mm/Kconfig
1075 bool "Enable iWMMXt support"
1076 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1077 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1079 Enable support for iWMMXt context switching at run time if
1080 running on a CPU that supports it.
1082 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1085 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1089 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1090 (!ARCH_OMAP3 || OMAP3_EMU)
1094 config MULTI_IRQ_HANDLER
1097 Allow each machine to specify it's own IRQ handler at run time.
1100 source "arch/arm/Kconfig-nommu"
1103 config ARM_ERRATA_411920
1104 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1105 depends on CPU_V6 || CPU_V6K
1107 Invalidation of the Instruction Cache operation can
1108 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1109 It does not affect the MPCore. This option enables the ARM Ltd.
1110 recommended workaround.
1112 config ARM_ERRATA_430973
1113 bool "ARM errata: Stale prediction on replaced interworking branch"
1116 This option enables the workaround for the 430973 Cortex-A8
1117 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1118 interworking branch is replaced with another code sequence at the
1119 same virtual address, whether due to self-modifying code or virtual
1120 to physical address re-mapping, Cortex-A8 does not recover from the
1121 stale interworking branch prediction. This results in Cortex-A8
1122 executing the new code sequence in the incorrect ARM or Thumb state.
1123 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1124 and also flushes the branch target cache at every context switch.
1125 Note that setting specific bits in the ACTLR register may not be
1126 available in non-secure mode.
1128 config ARM_ERRATA_458693
1129 bool "ARM errata: Processor deadlock when a false hazard is created"
1132 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1133 erratum. For very specific sequences of memory operations, it is
1134 possible for a hazard condition intended for a cache line to instead
1135 be incorrectly associated with a different cache line. This false
1136 hazard might then cause a processor deadlock. The workaround enables
1137 the L1 caching of the NEON accesses and disables the PLD instruction
1138 in the ACTLR register. Note that setting specific bits in the ACTLR
1139 register may not be available in non-secure mode.
1141 config ARM_ERRATA_460075
1142 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1145 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1146 erratum. Any asynchronous access to the L2 cache may encounter a
1147 situation in which recent store transactions to the L2 cache are lost
1148 and overwritten with stale memory contents from external memory. The
1149 workaround disables the write-allocate mode for the L2 cache via the
1150 ACTLR register. Note that setting specific bits in the ACTLR register
1151 may not be available in non-secure mode.
1153 config ARM_ERRATA_742230
1154 bool "ARM errata: DMB operation may be faulty"
1155 depends on CPU_V7 && SMP
1157 This option enables the workaround for the 742230 Cortex-A9
1158 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1159 between two write operations may not ensure the correct visibility
1160 ordering of the two writes. This workaround sets a specific bit in
1161 the diagnostic register of the Cortex-A9 which causes the DMB
1162 instruction to behave as a DSB, ensuring the correct behaviour of
1165 config ARM_ERRATA_742231
1166 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1167 depends on CPU_V7 && SMP
1169 This option enables the workaround for the 742231 Cortex-A9
1170 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1171 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1172 accessing some data located in the same cache line, may get corrupted
1173 data due to bad handling of the address hazard when the line gets
1174 replaced from one of the CPUs at the same time as another CPU is
1175 accessing it. This workaround sets specific bits in the diagnostic
1176 register of the Cortex-A9 which reduces the linefill issuing
1177 capabilities of the processor.
1179 config PL310_ERRATA_588369
1180 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1181 depends on CACHE_L2X0
1183 The PL310 L2 cache controller implements three types of Clean &
1184 Invalidate maintenance operations: by Physical Address
1185 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1186 They are architecturally defined to behave as the execution of a
1187 clean operation followed immediately by an invalidate operation,
1188 both performing to the same memory location. This functionality
1189 is not correctly implemented in PL310 as clean lines are not
1190 invalidated as a result of these operations.
1192 config ARM_ERRATA_720789
1193 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1194 depends on CPU_V7 && SMP
1196 This option enables the workaround for the 720789 Cortex-A9 (prior to
1197 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1198 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1199 As a consequence of this erratum, some TLB entries which should be
1200 invalidated are not, resulting in an incoherency in the system page
1201 tables. The workaround changes the TLB flushing routines to invalidate
1202 entries regardless of the ASID.
1204 config PL310_ERRATA_727915
1205 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1206 depends on CACHE_L2X0
1208 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1209 operation (offset 0x7FC). This operation runs in background so that
1210 PL310 can handle normal accesses while it is in progress. Under very
1211 rare circumstances, due to this erratum, write data can be lost when
1212 PL310 treats a cacheable write transaction during a Clean &
1213 Invalidate by Way operation.
1215 config ARM_ERRATA_743622
1216 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1219 This option enables the workaround for the 743622 Cortex-A9
1220 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1221 optimisation in the Cortex-A9 Store Buffer may lead to data
1222 corruption. This workaround sets a specific bit in the diagnostic
1223 register of the Cortex-A9 which disables the Store Buffer
1224 optimisation, preventing the defect from occurring. This has no
1225 visible impact on the overall performance or power consumption of the
1228 config ARM_ERRATA_751472
1229 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1230 depends on CPU_V7 && SMP
1232 This option enables the workaround for the 751472 Cortex-A9 (prior
1233 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1234 completion of a following broadcasted operation if the second
1235 operation is received by a CPU before the ICIALLUIS has completed,
1236 potentially leading to corrupted entries in the cache or TLB.
1238 config ARM_ERRATA_753970
1239 bool "ARM errata: cache sync operation may be faulty"
1240 depends on CACHE_PL310
1242 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1244 Under some condition the effect of cache sync operation on
1245 the store buffer still remains when the operation completes.
1246 This means that the store buffer is always asked to drain and
1247 this prevents it from merging any further writes. The workaround
1248 is to replace the normal offset of cache sync operation (0x730)
1249 by another offset targeting an unmapped PL310 register 0x740.
1250 This has the same effect as the cache sync operation: store buffer
1251 drain and waiting for all buffers empty.
1253 config ARM_ERRATA_754322
1254 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1257 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1258 r3p*) erratum. A speculative memory access may cause a page table walk
1259 which starts prior to an ASID switch but completes afterwards. This
1260 can populate the micro-TLB with a stale entry which may be hit with
1261 the new ASID. This workaround places two dsb instructions in the mm
1262 switching code so that no page table walks can cross the ASID switch.
1264 config ARM_ERRATA_754327
1265 bool "ARM errata: no automatic Store Buffer drain"
1266 depends on CPU_V7 && SMP
1268 This option enables the workaround for the 754327 Cortex-A9 (prior to
1269 r2p0) erratum. The Store Buffer does not have any automatic draining
1270 mechanism and therefore a livelock may occur if an external agent
1271 continuously polls a memory location waiting to observe an update.
1272 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1273 written polling loops from denying visibility of updates to memory.
1275 config ARM_ERRATA_364296
1276 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1277 depends on CPU_V6 && !SMP
1279 This options enables the workaround for the 364296 ARM1136
1280 r0p2 erratum (possible cache data corruption with
1281 hit-under-miss enabled). It sets the undocumented bit 31 in
1282 the auxiliary control register and the FI bit in the control
1283 register, thus disabling hit-under-miss without putting the
1284 processor into full low interrupt latency mode. ARM11MPCore
1287 config ARM_ERRATA_764369
1288 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1289 depends on CPU_V7 && SMP
1291 This option enables the workaround for erratum 764369
1292 affecting Cortex-A9 MPCore with two or more processors (all
1293 current revisions). Under certain timing circumstances, a data
1294 cache line maintenance operation by MVA targeting an Inner
1295 Shareable memory region may fail to proceed up to either the
1296 Point of Coherency or to the Point of Unification of the
1297 system. This workaround adds a DSB instruction before the
1298 relevant cache maintenance functions and sets a specific bit
1299 in the diagnostic control register of the SCU.
1303 source "arch/arm/common/Kconfig"
1313 Find out whether you have ISA slots on your motherboard. ISA is the
1314 name of a bus system, i.e. the way the CPU talks to the other stuff
1315 inside your box. Other bus systems are PCI, EISA, MicroChannel
1316 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1317 newer boards don't support it. If you have ISA, say Y, otherwise N.
1319 # Select ISA DMA controller support
1324 # Select ISA DMA interface
1329 bool "PCI support" if MIGHT_HAVE_PCI
1331 Find out whether you have a PCI motherboard. PCI is the name of a
1332 bus system, i.e. the way the CPU talks to the other stuff inside
1333 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1334 VESA. If you have PCI, say Y, otherwise N.
1340 config PCI_NANOENGINE
1341 bool "BSE nanoEngine PCI support"
1342 depends on SA1100_NANOENGINE
1344 Enable PCI on the BSE nanoEngine board.
1349 # Select the host bridge type
1350 config PCI_HOST_VIA82C505
1352 depends on PCI && ARCH_SHARK
1355 config PCI_HOST_ITE8152
1357 depends on PCI && MACH_ARMCORE
1361 source "drivers/pci/Kconfig"
1363 source "drivers/pcmcia/Kconfig"
1367 menu "Kernel Features"
1369 source "kernel/time/Kconfig"
1372 bool "Symmetric Multi-Processing"
1373 depends on CPU_V6K || CPU_V7
1374 depends on GENERIC_CLOCKEVENTS
1375 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1376 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1377 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1378 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1379 select USE_GENERIC_SMP_HELPERS
1380 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1382 This enables support for systems with more than one CPU. If you have
1383 a system with only one CPU, like most personal computers, say N. If
1384 you have a system with more than one CPU, say Y.
1386 If you say N here, the kernel will run on single and multiprocessor
1387 machines, but will use only one CPU of a multiprocessor machine. If
1388 you say Y here, the kernel will run on many, but not all, single
1389 processor machines. On a single processor machine, the kernel will
1390 run faster if you say N here.
1392 See also <file:Documentation/i386/IO-APIC.txt>,
1393 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1394 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1396 If you don't know what to do here, say N.
1399 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1400 depends on EXPERIMENTAL
1401 depends on SMP && !XIP_KERNEL
1404 SMP kernels contain instructions which fail on non-SMP processors.
1405 Enabling this option allows the kernel to modify itself to make
1406 these instructions safe. Disabling it allows about 1K of space
1409 If you don't know what to do here, say Y.
1414 This option enables support for the ARM system coherency unit
1421 This options enables support for the ARM timer and watchdog unit
1424 prompt "Memory split"
1427 Select the desired split between kernel and user memory.
1429 If you are not absolutely sure what you are doing, leave this
1433 bool "3G/1G user/kernel split"
1435 bool "2G/2G user/kernel split"
1437 bool "1G/3G user/kernel split"
1442 default 0x40000000 if VMSPLIT_1G
1443 default 0x80000000 if VMSPLIT_2G
1447 int "Maximum number of CPUs (2-32)"
1453 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1454 depends on SMP && HOTPLUG && EXPERIMENTAL
1456 Say Y here to experiment with turning CPUs off and on. CPUs
1457 can be controlled through /sys/devices/system/cpu.
1460 bool "Use local timer interrupts"
1463 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1465 Enable support for local timers on SMP platforms, rather then the
1466 legacy IPI broadcast method. Local timers allows the system
1467 accounting to be spread across the timer interval, preventing a
1468 "thundering herd" at every timer tick.
1470 source kernel/Kconfig.preempt
1474 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1475 ARCH_S5PV210 || ARCH_EXYNOS4
1476 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1477 default AT91_TIMER_HZ if ARCH_AT91
1478 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1481 config THUMB2_KERNEL
1482 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1483 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1485 select ARM_ASM_UNIFIED
1487 By enabling this option, the kernel will be compiled in
1488 Thumb-2 mode. A compiler/assembler that understand the unified
1489 ARM-Thumb syntax is needed.
1493 config THUMB2_AVOID_R_ARM_THM_JUMP11
1494 bool "Work around buggy Thumb-2 short branch relocations in gas"
1495 depends on THUMB2_KERNEL && MODULES
1498 Various binutils versions can resolve Thumb-2 branches to
1499 locally-defined, preemptible global symbols as short-range "b.n"
1500 branch instructions.
1502 This is a problem, because there's no guarantee the final
1503 destination of the symbol, or any candidate locations for a
1504 trampoline, are within range of the branch. For this reason, the
1505 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1506 relocation in modules at all, and it makes little sense to add
1509 The symptom is that the kernel fails with an "unsupported
1510 relocation" error when loading some modules.
1512 Until fixed tools are available, passing
1513 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1514 code which hits this problem, at the cost of a bit of extra runtime
1515 stack usage in some cases.
1517 The problem is described in more detail at:
1518 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1520 Only Thumb-2 kernels are affected.
1522 Unless you are sure your tools don't have this problem, say Y.
1524 config ARM_ASM_UNIFIED
1528 bool "Use the ARM EABI to compile the kernel"
1530 This option allows for the kernel to be compiled using the latest
1531 ARM ABI (aka EABI). This is only useful if you are using a user
1532 space environment that is also compiled with EABI.
1534 Since there are major incompatibilities between the legacy ABI and
1535 EABI, especially with regard to structure member alignment, this
1536 option also changes the kernel syscall calling convention to
1537 disambiguate both ABIs and allow for backward compatibility support
1538 (selected with CONFIG_OABI_COMPAT).
1540 To use this you need GCC version 4.0.0 or later.
1543 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1544 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1547 This option preserves the old syscall interface along with the
1548 new (ARM EABI) one. It also provides a compatibility layer to
1549 intercept syscalls that have structure arguments which layout
1550 in memory differs between the legacy ABI and the new ARM EABI
1551 (only for non "thumb" binaries). This option adds a tiny
1552 overhead to all syscalls and produces a slightly larger kernel.
1553 If you know you'll be using only pure EABI user space then you
1554 can say N here. If this option is not selected and you attempt
1555 to execute a legacy ABI binary then the result will be
1556 UNPREDICTABLE (in fact it can be predicted that it won't work
1557 at all). If in doubt say Y.
1559 config ARCH_HAS_HOLES_MEMORYMODEL
1562 config ARCH_SPARSEMEM_ENABLE
1565 config ARCH_SPARSEMEM_DEFAULT
1566 def_bool ARCH_SPARSEMEM_ENABLE
1568 config ARCH_SELECT_MEMORY_MODEL
1569 def_bool ARCH_SPARSEMEM_ENABLE
1571 config HAVE_ARCH_PFN_VALID
1572 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1575 bool "High Memory Support"
1578 The address space of ARM processors is only 4 Gigabytes large
1579 and it has to accommodate user address space, kernel address
1580 space as well as some memory mapped IO. That means that, if you
1581 have a large amount of physical memory and/or IO, not all of the
1582 memory can be "permanently mapped" by the kernel. The physical
1583 memory that is not permanently mapped is called "high memory".
1585 Depending on the selected kernel/user memory split, minimum
1586 vmalloc space and actual amount of RAM, you may not need this
1587 option which should result in a slightly faster kernel.
1592 bool "Allocate 2nd-level pagetables from highmem"
1595 config HW_PERF_EVENTS
1596 bool "Enable hardware performance counter support for perf events"
1597 depends on PERF_EVENTS && CPU_HAS_PMU
1600 Enable hardware performance counter support for perf events. If
1601 disabled, perf events will use software events only.
1605 config FORCE_MAX_ZONEORDER
1606 int "Maximum zone order" if ARCH_SHMOBILE
1607 range 11 64 if ARCH_SHMOBILE
1608 default "9" if SA1111
1611 The kernel memory allocator divides physically contiguous memory
1612 blocks into "zones", where each zone is a power of two number of
1613 pages. This option selects the largest power of two that the kernel
1614 keeps in the memory allocator. If you need to allocate very large
1615 blocks of physically contiguous memory, then you may need to
1616 increase this value.
1618 This config option is actually maximum order plus one. For example,
1619 a value of 11 means that the largest free memory block is 2^10 pages.
1622 bool "Timer and CPU usage LEDs"
1623 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1624 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1625 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1626 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1627 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1628 ARCH_AT91 || ARCH_DAVINCI || \
1629 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1631 If you say Y here, the LEDs on your machine will be used
1632 to provide useful information about your current system status.
1634 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1635 be able to select which LEDs are active using the options below. If
1636 you are compiling a kernel for the EBSA-110 or the LART however, the
1637 red LED will simply flash regularly to indicate that the system is
1638 still functional. It is safe to say Y here if you have a CATS
1639 system, but the driver will do nothing.
1642 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1643 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1644 || MACH_OMAP_PERSEUS2
1646 depends on !GENERIC_CLOCKEVENTS
1647 default y if ARCH_EBSA110
1649 If you say Y here, one of the system LEDs (the green one on the
1650 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1651 will flash regularly to indicate that the system is still
1652 operational. This is mainly useful to kernel hackers who are
1653 debugging unstable kernels.
1655 The LART uses the same LED for both Timer LED and CPU usage LED
1656 functions. You may choose to use both, but the Timer LED function
1657 will overrule the CPU usage LED.
1660 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1662 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1663 || MACH_OMAP_PERSEUS2
1666 If you say Y here, the red LED will be used to give a good real
1667 time indication of CPU usage, by lighting whenever the idle task
1668 is not currently executing.
1670 The LART uses the same LED for both Timer LED and CPU usage LED
1671 functions. You may choose to use both, but the Timer LED function
1672 will overrule the CPU usage LED.
1674 config ALIGNMENT_TRAP
1676 depends on CPU_CP15_MMU
1677 default y if !ARCH_EBSA110
1678 select HAVE_PROC_CPU if PROC_FS
1680 ARM processors cannot fetch/store information which is not
1681 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1682 address divisible by 4. On 32-bit ARM processors, these non-aligned
1683 fetch/store instructions will be emulated in software if you say
1684 here, which has a severe performance impact. This is necessary for
1685 correct operation of some network protocols. With an IP-only
1686 configuration it is safe to say N, otherwise say Y.
1688 config UACCESS_WITH_MEMCPY
1689 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1690 depends on MMU && EXPERIMENTAL
1691 default y if CPU_FEROCEON
1693 Implement faster copy_to_user and clear_user methods for CPU
1694 cores where a 8-word STM instruction give significantly higher
1695 memory write throughput than a sequence of individual 32bit stores.
1697 A possible side effect is a slight increase in scheduling latency
1698 between threads sharing the same address space if they invoke
1699 such copy operations with large buffers.
1701 However, if the CPU data cache is using a write-allocate mode,
1702 this option is unlikely to provide any performance gain.
1706 prompt "Enable seccomp to safely compute untrusted bytecode"
1708 This kernel feature is useful for number crunching applications
1709 that may need to compute untrusted bytecode during their
1710 execution. By using pipes or other transports made available to
1711 the process as file descriptors supporting the read/write
1712 syscalls, it's possible to isolate those applications in
1713 their own address space using seccomp. Once seccomp is
1714 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1715 and the task is only allowed to execute a few safe syscalls
1716 defined by each seccomp mode.
1718 config CC_STACKPROTECTOR
1719 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1720 depends on EXPERIMENTAL
1722 This option turns on the -fstack-protector GCC feature. This
1723 feature puts, at the beginning of functions, a canary value on
1724 the stack just before the return address, and validates
1725 the value just before actually returning. Stack based buffer
1726 overflows (that need to overwrite this return address) now also
1727 overwrite the canary, which gets detected and the attack is then
1728 neutralized via a kernel panic.
1729 This feature requires gcc version 4.2 or above.
1731 config DEPRECATED_PARAM_STRUCT
1732 bool "Provide old way to pass kernel parameters"
1734 This was deprecated in 2001 and announced to live on for 5 years.
1735 Some old boot loaders still use this way.
1742 bool "Flattened Device Tree support"
1744 select OF_EARLY_FLATTREE
1747 Include support for flattened device tree machine descriptions.
1749 # Compressed boot loader in ROM. Yes, we really want to ask about
1750 # TEXT and BSS so we preserve their values in the config files.
1751 config ZBOOT_ROM_TEXT
1752 hex "Compressed ROM boot loader base address"
1755 The physical address at which the ROM-able zImage is to be
1756 placed in the target. Platforms which normally make use of
1757 ROM-able zImage formats normally set this to a suitable
1758 value in their defconfig file.
1760 If ZBOOT_ROM is not enabled, this has no effect.
1762 config ZBOOT_ROM_BSS
1763 hex "Compressed ROM boot loader BSS address"
1766 The base address of an area of read/write memory in the target
1767 for the ROM-able zImage which must be available while the
1768 decompressor is running. It must be large enough to hold the
1769 entire decompressed kernel plus an additional 128 KiB.
1770 Platforms which normally make use of ROM-able zImage formats
1771 normally set this to a suitable value in their defconfig file.
1773 If ZBOOT_ROM is not enabled, this has no effect.
1776 bool "Compressed boot loader in ROM/flash"
1777 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1779 Say Y here if you intend to execute your compressed kernel image
1780 (zImage) directly from ROM or flash. If unsure, say N.
1783 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1784 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1785 default ZBOOT_ROM_NONE
1787 Include experimental SD/MMC loading code in the ROM-able zImage.
1788 With this enabled it is possible to write the the ROM-able zImage
1789 kernel image to an MMC or SD card and boot the kernel straight
1790 from the reset vector. At reset the processor Mask ROM will load
1791 the first part of the the ROM-able zImage which in turn loads the
1792 rest the kernel image to RAM.
1794 config ZBOOT_ROM_NONE
1795 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1797 Do not load image from SD or MMC
1799 config ZBOOT_ROM_MMCIF
1800 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1802 Load image from MMCIF hardware block.
1804 config ZBOOT_ROM_SH_MOBILE_SDHI
1805 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1807 Load image from SDHI hardware block
1812 string "Default kernel command string"
1815 On some architectures (EBSA110 and CATS), there is currently no way
1816 for the boot loader to pass arguments to the kernel. For these
1817 architectures, you should supply some command-line options at build
1818 time by entering them here. As a minimum, you should specify the
1819 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1822 prompt "Kernel command line type" if CMDLINE != ""
1823 default CMDLINE_FROM_BOOTLOADER
1825 config CMDLINE_FROM_BOOTLOADER
1826 bool "Use bootloader kernel arguments if available"
1828 Uses the command-line options passed by the boot loader. If
1829 the boot loader doesn't provide any, the default kernel command
1830 string provided in CMDLINE will be used.
1832 config CMDLINE_EXTEND
1833 bool "Extend bootloader kernel arguments"
1835 The command-line arguments provided by the boot loader will be
1836 appended to the default kernel command string.
1838 config CMDLINE_FORCE
1839 bool "Always use the default kernel command string"
1841 Always use the default kernel command string, even if the boot
1842 loader passes other arguments to the kernel.
1843 This is useful if you cannot or don't want to change the
1844 command-line options your boot loader passes to the kernel.
1848 bool "Kernel Execute-In-Place from ROM"
1849 depends on !ZBOOT_ROM
1851 Execute-In-Place allows the kernel to run from non-volatile storage
1852 directly addressable by the CPU, such as NOR flash. This saves RAM
1853 space since the text section of the kernel is not loaded from flash
1854 to RAM. Read-write sections, such as the data section and stack,
1855 are still copied to RAM. The XIP kernel is not compressed since
1856 it has to run directly from flash, so it will take more space to
1857 store it. The flash address used to link the kernel object files,
1858 and for storing it, is configuration dependent. Therefore, if you
1859 say Y here, you must know the proper physical address where to
1860 store the kernel image depending on your own flash memory usage.
1862 Also note that the make target becomes "make xipImage" rather than
1863 "make zImage" or "make Image". The final kernel binary to put in
1864 ROM memory will be arch/arm/boot/xipImage.
1868 config XIP_PHYS_ADDR
1869 hex "XIP Kernel Physical Location"
1870 depends on XIP_KERNEL
1871 default "0x00080000"
1873 This is the physical address in your flash memory the kernel will
1874 be linked for and stored to. This address is dependent on your
1878 bool "Kexec system call (EXPERIMENTAL)"
1879 depends on EXPERIMENTAL
1881 kexec is a system call that implements the ability to shutdown your
1882 current kernel, and to start another kernel. It is like a reboot
1883 but it is independent of the system firmware. And like a reboot
1884 you can start any kernel with it, not just Linux.
1886 It is an ongoing process to be certain the hardware in a machine
1887 is properly shutdown, so do not be surprised if this code does not
1888 initially work for you. It may help to enable device hotplugging
1892 bool "Export atags in procfs"
1896 Should the atags used to boot the kernel be exported in an "atags"
1897 file in procfs. Useful with kexec.
1900 bool "Build kdump crash kernel (EXPERIMENTAL)"
1901 depends on EXPERIMENTAL
1903 Generate crash dump after being started by kexec. This should
1904 be normally only set in special crash dump kernels which are
1905 loaded in the main kernel with kexec-tools into a specially
1906 reserved region and then later executed after a crash by
1907 kdump/kexec. The crash dump kernel must be compiled to a
1908 memory address not used by the main kernel
1910 For more details see Documentation/kdump/kdump.txt
1912 config AUTO_ZRELADDR
1913 bool "Auto calculation of the decompressed kernel image address"
1914 depends on !ZBOOT_ROM && !ARCH_U300
1916 ZRELADDR is the physical address where the decompressed kernel
1917 image will be placed. If AUTO_ZRELADDR is selected, the address
1918 will be determined at run-time by masking the current IP with
1919 0xf8000000. This assumes the zImage being placed in the first 128MB
1920 from start of memory.
1924 menu "CPU Power Management"
1928 source "drivers/cpufreq/Kconfig"
1931 tristate "CPUfreq driver for i.MX CPUs"
1932 depends on ARCH_MXC && CPU_FREQ
1934 This enables the CPUfreq driver for i.MX CPUs.
1936 config CPU_FREQ_SA1100
1939 config CPU_FREQ_SA1110
1942 config CPU_FREQ_INTEGRATOR
1943 tristate "CPUfreq driver for ARM Integrator CPUs"
1944 depends on ARCH_INTEGRATOR && CPU_FREQ
1947 This enables the CPUfreq driver for ARM Integrator CPUs.
1949 For details, take a look at <file:Documentation/cpu-freq>.
1955 depends on CPU_FREQ && ARCH_PXA && PXA25x
1957 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1962 Internal configuration node for common cpufreq on Samsung SoC
1964 config CPU_FREQ_S3C24XX
1965 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1966 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1969 This enables the CPUfreq driver for the Samsung S3C24XX family
1972 For details, take a look at <file:Documentation/cpu-freq>.
1976 config CPU_FREQ_S3C24XX_PLL
1977 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1978 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1980 Compile in support for changing the PLL frequency from the
1981 S3C24XX series CPUfreq driver. The PLL takes time to settle
1982 after a frequency change, so by default it is not enabled.
1984 This also means that the PLL tables for the selected CPU(s) will
1985 be built which may increase the size of the kernel image.
1987 config CPU_FREQ_S3C24XX_DEBUG
1988 bool "Debug CPUfreq Samsung driver core"
1989 depends on CPU_FREQ_S3C24XX
1991 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1993 config CPU_FREQ_S3C24XX_IODEBUG
1994 bool "Debug CPUfreq Samsung driver IO timing"
1995 depends on CPU_FREQ_S3C24XX
1997 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1999 config CPU_FREQ_S3C24XX_DEBUGFS
2000 bool "Export debugfs for CPUFreq"
2001 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2003 Export status information via debugfs.
2007 source "drivers/cpuidle/Kconfig"
2011 menu "Floating point emulation"
2013 comment "At least one emulation must be selected"
2016 bool "NWFPE math emulation"
2017 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2019 Say Y to include the NWFPE floating point emulator in the kernel.
2020 This is necessary to run most binaries. Linux does not currently
2021 support floating point hardware so you need to say Y here even if
2022 your machine has an FPA or floating point co-processor podule.
2024 You may say N here if you are going to load the Acorn FPEmulator
2025 early in the bootup.
2028 bool "Support extended precision"
2029 depends on FPE_NWFPE
2031 Say Y to include 80-bit support in the kernel floating-point
2032 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2033 Note that gcc does not generate 80-bit operations by default,
2034 so in most cases this option only enlarges the size of the
2035 floating point emulator without any good reason.
2037 You almost surely want to say N here.
2040 bool "FastFPE math emulation (EXPERIMENTAL)"
2041 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2043 Say Y here to include the FAST floating point emulator in the kernel.
2044 This is an experimental much faster emulator which now also has full
2045 precision for the mantissa. It does not support any exceptions.
2046 It is very simple, and approximately 3-6 times faster than NWFPE.
2048 It should be sufficient for most programs. It may be not suitable
2049 for scientific calculations, but you have to check this for yourself.
2050 If you do not feel you need a faster FP emulation you should better
2054 bool "VFP-format floating point maths"
2055 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2057 Say Y to include VFP support code in the kernel. This is needed
2058 if your hardware includes a VFP unit.
2060 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2061 release notes and additional status information.
2063 Say N if your target does not have VFP hardware.
2071 bool "Advanced SIMD (NEON) Extension support"
2072 depends on VFPv3 && CPU_V7
2074 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2079 menu "Userspace binary formats"
2081 source "fs/Kconfig.binfmt"
2084 tristate "RISC OS personality"
2087 Say Y here to include the kernel code necessary if you want to run
2088 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2089 experimental; if this sounds frightening, say N and sleep in peace.
2090 You can also say M here to compile this support as a module (which
2091 will be called arthur).
2095 menu "Power management options"
2097 source "kernel/power/Kconfig"
2099 config ARCH_SUSPEND_POSSIBLE
2100 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2101 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2102 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2107 source "net/Kconfig"
2109 source "drivers/Kconfig"
2113 source "arch/arm/Kconfig.debug"
2115 source "security/Kconfig"
2117 source "crypto/Kconfig"
2119 source "lib/Kconfig"