5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
12 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
14 select HAVE_KPROBES if !XIP_KERNEL
15 select HAVE_KRETPROBES if (HAVE_KPROBES)
16 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
17 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
18 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
19 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
20 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
21 select HAVE_GENERIC_DMA_COHERENT
22 select HAVE_KERNEL_GZIP
23 select HAVE_KERNEL_LZO
24 select HAVE_KERNEL_LZMA
27 select HAVE_PERF_EVENTS
28 select PERF_USE_VMALLOC
29 select HAVE_REGS_AND_STACK_ACCESS_API
30 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
31 select HAVE_C_RECORDMCOUNT
32 select HAVE_GENERIC_HARDIRQS
33 select GENERIC_IRQ_SHOW
34 select CPU_PM if (SUSPEND || CPU_IDLE)
35 select GENERIC_PCI_IOMAP
36 select HAVE_BPF_JIT if NET
38 The ARM series is a line of low-power-consumption RISC chip designs
39 licensed by ARM Ltd and targeted at embedded applications and
40 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
41 manufactured, but legacy ARM-based PC hardware remains popular in
42 Europe. There is an ARM Linux project with a web page at
43 <http://www.arm.linux.org.uk/>.
45 config ARM_HAS_SG_CHAIN
54 config SYS_SUPPORTS_APM_EMULATION
60 config ARCH_USES_GETTIMEOFFSET
64 config GENERIC_CLOCKEVENTS
67 config GENERIC_CLOCKEVENTS_BROADCAST
69 depends on GENERIC_CLOCKEVENTS
78 select GENERIC_ALLOCATOR
89 The Extended Industry Standard Architecture (EISA) bus was
90 developed as an open alternative to the IBM MicroChannel bus.
92 The EISA bus provided some of the features of the IBM MicroChannel
93 bus while maintaining backward compatibility with cards made for
94 the older ISA bus. The EISA bus saw limited use between 1988 and
95 1995 when it was made obsolete by the PCI bus.
97 Say Y here if you are building a kernel for an EISA-based machine.
104 config STACKTRACE_SUPPORT
108 config HAVE_LATENCYTOP_SUPPORT
113 config LOCKDEP_SUPPORT
117 config TRACE_IRQFLAGS_SUPPORT
121 config HARDIRQS_SW_RESEND
125 config GENERIC_IRQ_PROBE
129 config GENERIC_LOCKBREAK
132 depends on SMP && PREEMPT
134 config RWSEM_GENERIC_SPINLOCK
138 config RWSEM_XCHGADD_ALGORITHM
141 config ARCH_HAS_ILOG2_U32
144 config ARCH_HAS_ILOG2_U64
147 config ARCH_HAS_CPUFREQ
150 Internal node to signify that the ARCH has CPUFREQ support
151 and that the relevant menu configurations are displayed for
154 config ARCH_HAS_CPU_IDLE_WAIT
157 config GENERIC_HWEIGHT
161 config GENERIC_CALIBRATE_DELAY
165 config ARCH_MAY_HAVE_PC_FDC
171 config NEED_DMA_MAP_STATE
174 config ARCH_HAS_DMA_SET_COHERENT_MASK
177 config GENERIC_ISA_DMA
183 config NEED_RET_TO_USER
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime" if EMBEDDED
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary.
210 Only disable this option if you know that you do not require
211 this feature (eg, building a kernel for a single machine) and
212 you need to shrink the kernel to the minimal size.
214 config NEED_MACH_IO_H
217 Select this when mach/io.h is required to provide special
218 definitions for this platform. The need for mach/io.h should
219 be avoided when possible.
221 config NEED_MACH_MEMORY_H
224 Select this when mach/memory.h is required to provide special
225 definitions for this platform. The need for mach/memory.h should
226 be avoided when possible.
229 hex "Physical address of main memory" if MMU
230 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
231 default DRAM_BASE if !MMU
233 Please provide the physical address corresponding to the
234 location of main memory in your system.
240 source "init/Kconfig"
242 source "kernel/Kconfig.freezer"
247 bool "MMU-based Paged Memory Management Support"
250 Select if you want MMU-based virtualised addressing space
251 support by paged memory management. If unsure, say 'Y'.
254 # The "ARM system type" choice list is ordered alphabetically by option
255 # text. Please add new entries in the option alphabetic order.
258 prompt "ARM system type"
259 default ARCH_VERSATILE
261 config ARCH_INTEGRATOR
262 bool "ARM Ltd. Integrator family"
264 select ARCH_HAS_CPUFREQ
266 select HAVE_MACH_CLKDEV
269 select GENERIC_CLOCKEVENTS
270 select PLAT_VERSATILE
271 select PLAT_VERSATILE_FPGA_IRQ
272 select NEED_MACH_IO_H
273 select NEED_MACH_MEMORY_H
276 Support for ARM's Integrator platform.
279 bool "ARM Ltd. RealView family"
282 select HAVE_MACH_CLKDEV
284 select GENERIC_CLOCKEVENTS
285 select ARCH_WANT_OPTIONAL_GPIOLIB
286 select PLAT_VERSATILE
287 select PLAT_VERSATILE_CLCD
288 select ARM_TIMER_SP804
289 select GPIO_PL061 if GPIOLIB
290 select NEED_MACH_MEMORY_H
292 This enables support for ARM Ltd RealView boards.
294 config ARCH_VERSATILE
295 bool "ARM Ltd. Versatile family"
299 select HAVE_MACH_CLKDEV
301 select GENERIC_CLOCKEVENTS
302 select ARCH_WANT_OPTIONAL_GPIOLIB
303 select PLAT_VERSATILE
304 select PLAT_VERSATILE_CLCD
305 select PLAT_VERSATILE_FPGA_IRQ
306 select ARM_TIMER_SP804
308 This enables support for ARM Ltd Versatile board.
311 bool "ARM Ltd. Versatile Express family"
312 select ARCH_WANT_OPTIONAL_GPIOLIB
314 select ARM_TIMER_SP804
316 select HAVE_MACH_CLKDEV
317 select GENERIC_CLOCKEVENTS
319 select HAVE_PATA_PLATFORM
322 select PLAT_VERSATILE
323 select PLAT_VERSATILE_CLCD
325 This enables support for the ARM Ltd Versatile Express boards.
329 select ARCH_REQUIRE_GPIOLIB
333 select NEED_MACH_IO_H if PCCARD
335 This enables support for systems based on the Atmel AT91RM9200,
339 bool "Broadcom BCMRING"
343 select ARM_TIMER_SP804
345 select GENERIC_CLOCKEVENTS
346 select ARCH_WANT_OPTIONAL_GPIOLIB
348 Support for Broadcom's BCMRing platform.
351 bool "Calxeda Highbank-based"
352 select ARCH_WANT_OPTIONAL_GPIOLIB
355 select ARM_TIMER_SP804
359 select GENERIC_CLOCKEVENTS
365 Support for the Calxeda Highbank SoC based boards.
368 bool "Cirrus Logic CLPS711x/EP721x-based"
370 select ARCH_USES_GETTIMEOFFSET
371 select NEED_MACH_MEMORY_H
373 Support for Cirrus Logic 711x/721x based boards.
376 bool "Cavium Networks CNS3XXX family"
378 select GENERIC_CLOCKEVENTS
380 select MIGHT_HAVE_CACHE_L2X0
381 select MIGHT_HAVE_PCI
382 select PCI_DOMAINS if PCI
384 Support for Cavium Networks CNS3XXX platform.
387 bool "Cortina Systems Gemini"
389 select ARCH_REQUIRE_GPIOLIB
390 select ARCH_USES_GETTIMEOFFSET
392 Support for the Cortina Systems Gemini family SoCs
395 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
398 select GENERIC_CLOCKEVENTS
400 select GENERIC_IRQ_CHIP
401 select MIGHT_HAVE_CACHE_L2X0
405 Support for CSR SiRFSoC ARM Cortex A9 Platform
412 select ARCH_USES_GETTIMEOFFSET
413 select NEED_MACH_IO_H
414 select NEED_MACH_MEMORY_H
416 This is an evaluation board for the StrongARM processor available
417 from Digital. It has limited hardware on-board, including an
418 Ethernet interface, two PCMCIA sockets, two serial ports and a
427 select ARCH_REQUIRE_GPIOLIB
428 select ARCH_HAS_HOLES_MEMORYMODEL
429 select ARCH_USES_GETTIMEOFFSET
430 select NEED_MACH_MEMORY_H
432 This enables support for the Cirrus EP93xx series of CPUs.
434 config ARCH_FOOTBRIDGE
438 select GENERIC_CLOCKEVENTS
440 select NEED_MACH_IO_H
441 select NEED_MACH_MEMORY_H
443 Support for systems based on the DC21285 companion chip
444 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
447 bool "Freescale MXC/iMX-based"
448 select GENERIC_CLOCKEVENTS
449 select ARCH_REQUIRE_GPIOLIB
452 select GENERIC_IRQ_CHIP
453 select MULTI_IRQ_HANDLER
455 Support for Freescale MXC/iMX-based family of processors
458 bool "Freescale MXS-based"
459 select GENERIC_CLOCKEVENTS
460 select ARCH_REQUIRE_GPIOLIB
463 select HAVE_CLK_PREPARE
465 Support for Freescale MXS-based family of processors
468 bool "Hilscher NetX based"
472 select GENERIC_CLOCKEVENTS
474 This enables support for systems based on the Hilscher NetX Soc
477 bool "Hynix HMS720x-based"
480 select ARCH_USES_GETTIMEOFFSET
482 This enables support for systems based on the Hynix HMS720x
490 select ARCH_SUPPORTS_MSI
492 select NEED_MACH_IO_H
493 select NEED_MACH_MEMORY_H
494 select NEED_RET_TO_USER
496 Support for Intel's IOP13XX (XScale) family of processors.
502 select NEED_MACH_IO_H
503 select NEED_RET_TO_USER
506 select ARCH_REQUIRE_GPIOLIB
508 Support for Intel's 80219 and IOP32X (XScale) family of
515 select NEED_MACH_IO_H
516 select NEED_RET_TO_USER
519 select ARCH_REQUIRE_GPIOLIB
521 Support for Intel's IOP33X (XScale) family of processors.
528 select ARCH_USES_GETTIMEOFFSET
529 select NEED_MACH_IO_H
530 select NEED_MACH_MEMORY_H
532 Support for Intel's IXP23xx (XScale) family of processors.
535 bool "IXP2400/2800-based"
539 select ARCH_USES_GETTIMEOFFSET
540 select NEED_MACH_IO_H
541 select NEED_MACH_MEMORY_H
543 Support for Intel's IXP2400/2800 (XScale) family of processors.
548 select ARCH_HAS_DMA_SET_COHERENT_MASK
552 select GENERIC_CLOCKEVENTS
553 select MIGHT_HAVE_PCI
554 select NEED_MACH_IO_H
555 select DMABOUNCE if PCI
557 Support for Intel's IXP4XX (XScale) family of processors.
563 select ARCH_REQUIRE_GPIOLIB
564 select GENERIC_CLOCKEVENTS
565 select NEED_MACH_IO_H
568 Support for the Marvell Dove SoC 88AP510
571 bool "Marvell Kirkwood"
574 select ARCH_REQUIRE_GPIOLIB
575 select GENERIC_CLOCKEVENTS
576 select NEED_MACH_IO_H
579 Support for the following Marvell Kirkwood series SoCs:
580 88F6180, 88F6192 and 88F6281.
586 select ARCH_REQUIRE_GPIOLIB
589 select USB_ARCH_HAS_OHCI
591 select GENERIC_CLOCKEVENTS
593 Support for the NXP LPC32XX family of processors
596 bool "Marvell MV78xx0"
599 select ARCH_REQUIRE_GPIOLIB
600 select GENERIC_CLOCKEVENTS
601 select NEED_MACH_IO_H
604 Support for the following Marvell MV78xx0 series SoCs:
612 select ARCH_REQUIRE_GPIOLIB
613 select GENERIC_CLOCKEVENTS
616 Support for the following Marvell Orion 5x series SoCs:
617 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
618 Orion-2 (5281), Orion-1-90 (6183).
621 bool "Marvell PXA168/910/MMP2"
623 select ARCH_REQUIRE_GPIOLIB
625 select GENERIC_CLOCKEVENTS
630 select GENERIC_ALLOCATOR
632 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
635 bool "Micrel/Kendin KS8695"
637 select ARCH_REQUIRE_GPIOLIB
638 select ARCH_USES_GETTIMEOFFSET
639 select NEED_MACH_MEMORY_H
641 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
642 System-on-Chip devices.
645 bool "Nuvoton W90X900 CPU"
647 select ARCH_REQUIRE_GPIOLIB
650 select GENERIC_CLOCKEVENTS
652 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
653 At present, the w90x900 has been renamed nuc900, regarding
654 the ARM series product line, you can login the following
655 link address to know more.
657 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
658 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
664 select GENERIC_CLOCKEVENTS
668 select MIGHT_HAVE_CACHE_L2X0
669 select NEED_MACH_IO_H if PCI
670 select ARCH_HAS_CPUFREQ
672 This enables support for NVIDIA Tegra based systems (Tegra APX,
673 Tegra 6xx and Tegra 2 series).
675 config ARCH_PICOXCELL
676 bool "Picochip picoXcell"
677 select ARCH_REQUIRE_GPIOLIB
678 select ARM_PATCH_PHYS_VIRT
682 select GENERIC_CLOCKEVENTS
689 This enables support for systems based on the Picochip picoXcell
690 family of Femtocell devices. The picoxcell support requires device tree
694 bool "Philips Nexperia PNX4008 Mobile"
697 select ARCH_USES_GETTIMEOFFSET
699 This enables support for Philips PNX4008 mobile platform.
702 bool "PXA2xx/PXA3xx-based"
705 select ARCH_HAS_CPUFREQ
708 select ARCH_REQUIRE_GPIOLIB
709 select GENERIC_CLOCKEVENTS
715 select MULTI_IRQ_HANDLER
716 select ARM_CPU_SUSPEND if PM
719 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
724 select GENERIC_CLOCKEVENTS
725 select ARCH_REQUIRE_GPIOLIB
728 Support for Qualcomm MSM/QSD based systems. This runs on the
729 apps processor of the MSM/QSD and depends on a shared memory
730 interface to the modem processor which runs the baseband
731 stack and controls some vital subsystems
732 (clock and power control, etc).
735 bool "Renesas SH-Mobile / R-Mobile"
738 select HAVE_MACH_CLKDEV
740 select GENERIC_CLOCKEVENTS
741 select MIGHT_HAVE_CACHE_L2X0
744 select MULTI_IRQ_HANDLER
745 select PM_GENERIC_DOMAINS if PM
746 select NEED_MACH_MEMORY_H
748 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
754 select ARCH_MAY_HAVE_PC_FDC
755 select HAVE_PATA_PLATFORM
758 select ARCH_SPARSEMEM_ENABLE
759 select ARCH_USES_GETTIMEOFFSET
761 select NEED_MACH_IO_H
762 select NEED_MACH_MEMORY_H
764 On the Acorn Risc-PC, Linux can support the internal IDE disk and
765 CD-ROM interface, serial and parallel port, and the floppy drive.
772 select ARCH_SPARSEMEM_ENABLE
774 select ARCH_HAS_CPUFREQ
776 select GENERIC_CLOCKEVENTS
779 select ARCH_REQUIRE_GPIOLIB
781 select NEED_MACH_MEMORY_H
784 Support for StrongARM 11x0 based boards.
787 bool "Samsung S3C24XX SoCs"
789 select ARCH_HAS_CPUFREQ
792 select ARCH_USES_GETTIMEOFFSET
793 select HAVE_S3C2410_I2C if I2C
794 select HAVE_S3C_RTC if RTC_CLASS
795 select HAVE_S3C2410_WATCHDOG if WATCHDOG
796 select NEED_MACH_IO_H
798 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
799 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
800 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
801 Samsung SMDK2410 development board (and derivatives).
804 bool "Samsung S3C64XX"
812 select ARCH_USES_GETTIMEOFFSET
813 select ARCH_HAS_CPUFREQ
814 select ARCH_REQUIRE_GPIOLIB
815 select SAMSUNG_CLKSRC
816 select SAMSUNG_IRQ_VIC_TIMER
817 select S3C_GPIO_TRACK
819 select USB_ARCH_HAS_OHCI
820 select SAMSUNG_GPIOLIB_4BIT
821 select HAVE_S3C2410_I2C if I2C
822 select HAVE_S3C2410_WATCHDOG if WATCHDOG
824 Samsung S3C64XX series based systems
827 bool "Samsung S5P6440 S5P6450"
833 select HAVE_S3C2410_WATCHDOG if WATCHDOG
834 select GENERIC_CLOCKEVENTS
835 select HAVE_S3C2410_I2C if I2C
836 select HAVE_S3C_RTC if RTC_CLASS
838 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
842 bool "Samsung S5PC100"
847 select ARCH_USES_GETTIMEOFFSET
848 select HAVE_S3C2410_I2C if I2C
849 select HAVE_S3C_RTC if RTC_CLASS
850 select HAVE_S3C2410_WATCHDOG if WATCHDOG
852 Samsung S5PC100 series based systems
855 bool "Samsung S5PV210/S5PC110"
857 select ARCH_SPARSEMEM_ENABLE
858 select ARCH_HAS_HOLES_MEMORYMODEL
863 select ARCH_HAS_CPUFREQ
864 select GENERIC_CLOCKEVENTS
865 select HAVE_S3C2410_I2C if I2C
866 select HAVE_S3C_RTC if RTC_CLASS
867 select HAVE_S3C2410_WATCHDOG if WATCHDOG
868 select NEED_MACH_MEMORY_H
870 Samsung S5PV210/S5PC110 series based systems
873 bool "SAMSUNG EXYNOS"
875 select ARCH_SPARSEMEM_ENABLE
876 select ARCH_HAS_HOLES_MEMORYMODEL
880 select ARCH_HAS_CPUFREQ
881 select GENERIC_CLOCKEVENTS
882 select HAVE_S3C_RTC if RTC_CLASS
883 select HAVE_S3C2410_I2C if I2C
884 select HAVE_S3C2410_WATCHDOG if WATCHDOG
885 select NEED_MACH_MEMORY_H
887 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
896 select ARCH_USES_GETTIMEOFFSET
897 select NEED_MACH_MEMORY_H
898 select NEED_MACH_IO_H
900 Support for the StrongARM based Digital DNARD machine, also known
901 as "Shark" (<http://www.shark-linux.de/shark.html>).
904 bool "ST-Ericsson U300 Series"
910 select ARM_PATCH_PHYS_VIRT
912 select GENERIC_CLOCKEVENTS
914 select HAVE_MACH_CLKDEV
916 select ARCH_REQUIRE_GPIOLIB
918 Support for ST-Ericsson U300 series mobile platforms.
921 bool "ST-Ericsson U8500 Series"
925 select GENERIC_CLOCKEVENTS
927 select ARCH_REQUIRE_GPIOLIB
928 select ARCH_HAS_CPUFREQ
930 select MIGHT_HAVE_CACHE_L2X0
932 Support for ST-Ericsson's Ux500 architecture
935 bool "STMicroelectronics Nomadik"
940 select GENERIC_CLOCKEVENTS
941 select MIGHT_HAVE_CACHE_L2X0
942 select ARCH_REQUIRE_GPIOLIB
944 Support for the Nomadik platform by ST-Ericsson
948 select GENERIC_CLOCKEVENTS
949 select ARCH_REQUIRE_GPIOLIB
953 select GENERIC_ALLOCATOR
954 select GENERIC_IRQ_CHIP
955 select ARCH_HAS_HOLES_MEMORYMODEL
957 Support for TI's DaVinci platform.
962 select ARCH_REQUIRE_GPIOLIB
963 select ARCH_HAS_CPUFREQ
965 select GENERIC_CLOCKEVENTS
966 select ARCH_HAS_HOLES_MEMORYMODEL
968 Support for TI's OMAP platform (OMAP1/2/3/4).
973 select ARCH_REQUIRE_GPIOLIB
976 select GENERIC_CLOCKEVENTS
979 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
982 bool "VIA/WonderMedia 85xx"
985 select ARCH_HAS_CPUFREQ
986 select GENERIC_CLOCKEVENTS
987 select ARCH_REQUIRE_GPIOLIB
990 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
993 bool "Xilinx Zynq ARM Cortex A9 Platform"
995 select GENERIC_CLOCKEVENTS
1000 select MIGHT_HAVE_CACHE_L2X0
1003 Support for Xilinx Zynq ARM Cortex A9 Platform
1007 # This is sorted alphabetically by mach-* pathname. However, plat-*
1008 # Kconfigs may be included either alphabetically (according to the
1009 # plat- suffix) or along side the corresponding mach-* source.
1011 source "arch/arm/mach-at91/Kconfig"
1013 source "arch/arm/mach-bcmring/Kconfig"
1015 source "arch/arm/mach-clps711x/Kconfig"
1017 source "arch/arm/mach-cns3xxx/Kconfig"
1019 source "arch/arm/mach-davinci/Kconfig"
1021 source "arch/arm/mach-dove/Kconfig"
1023 source "arch/arm/mach-ep93xx/Kconfig"
1025 source "arch/arm/mach-footbridge/Kconfig"
1027 source "arch/arm/mach-gemini/Kconfig"
1029 source "arch/arm/mach-h720x/Kconfig"
1031 source "arch/arm/mach-integrator/Kconfig"
1033 source "arch/arm/mach-iop32x/Kconfig"
1035 source "arch/arm/mach-iop33x/Kconfig"
1037 source "arch/arm/mach-iop13xx/Kconfig"
1039 source "arch/arm/mach-ixp4xx/Kconfig"
1041 source "arch/arm/mach-ixp2000/Kconfig"
1043 source "arch/arm/mach-ixp23xx/Kconfig"
1045 source "arch/arm/mach-kirkwood/Kconfig"
1047 source "arch/arm/mach-ks8695/Kconfig"
1049 source "arch/arm/mach-lpc32xx/Kconfig"
1051 source "arch/arm/mach-msm/Kconfig"
1053 source "arch/arm/mach-mv78xx0/Kconfig"
1055 source "arch/arm/plat-mxc/Kconfig"
1057 source "arch/arm/mach-mxs/Kconfig"
1059 source "arch/arm/mach-netx/Kconfig"
1061 source "arch/arm/mach-nomadik/Kconfig"
1062 source "arch/arm/plat-nomadik/Kconfig"
1064 source "arch/arm/plat-omap/Kconfig"
1066 source "arch/arm/mach-omap1/Kconfig"
1068 source "arch/arm/mach-omap2/Kconfig"
1070 source "arch/arm/mach-orion5x/Kconfig"
1072 source "arch/arm/mach-pxa/Kconfig"
1073 source "arch/arm/plat-pxa/Kconfig"
1075 source "arch/arm/mach-mmp/Kconfig"
1077 source "arch/arm/mach-realview/Kconfig"
1079 source "arch/arm/mach-sa1100/Kconfig"
1081 source "arch/arm/plat-samsung/Kconfig"
1082 source "arch/arm/plat-s3c24xx/Kconfig"
1083 source "arch/arm/plat-s5p/Kconfig"
1085 source "arch/arm/plat-spear/Kconfig"
1087 source "arch/arm/mach-s3c24xx/Kconfig"
1089 source "arch/arm/mach-s3c2412/Kconfig"
1090 source "arch/arm/mach-s3c2440/Kconfig"
1094 source "arch/arm/mach-s3c64xx/Kconfig"
1097 source "arch/arm/mach-s5p64x0/Kconfig"
1099 source "arch/arm/mach-s5pc100/Kconfig"
1101 source "arch/arm/mach-s5pv210/Kconfig"
1103 source "arch/arm/mach-exynos/Kconfig"
1105 source "arch/arm/mach-shmobile/Kconfig"
1107 source "arch/arm/mach-tegra/Kconfig"
1109 source "arch/arm/mach-u300/Kconfig"
1111 source "arch/arm/mach-ux500/Kconfig"
1113 source "arch/arm/mach-versatile/Kconfig"
1115 source "arch/arm/mach-vexpress/Kconfig"
1116 source "arch/arm/plat-versatile/Kconfig"
1118 source "arch/arm/mach-vt8500/Kconfig"
1120 source "arch/arm/mach-w90x900/Kconfig"
1122 # Definitions to make life easier
1128 select GENERIC_CLOCKEVENTS
1133 select GENERIC_IRQ_CHIP
1138 config PLAT_VERSATILE
1141 config ARM_TIMER_SP804
1144 select HAVE_SCHED_CLOCK
1146 source arch/arm/mm/Kconfig
1150 default 16 if ARCH_EP93XX
1154 bool "Enable iWMMXt support"
1155 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1156 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1158 Enable support for iWMMXt context switching at run time if
1159 running on a CPU that supports it.
1163 depends on CPU_XSCALE
1167 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1168 (!ARCH_OMAP3 || OMAP3_EMU)
1172 config MULTI_IRQ_HANDLER
1175 Allow each machine to specify it's own IRQ handler at run time.
1178 source "arch/arm/Kconfig-nommu"
1181 config ARM_ERRATA_326103
1182 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1185 Executing a SWP instruction to read-only memory does not set bit 11
1186 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1187 treat the access as a read, preventing a COW from occurring and
1188 causing the faulting task to livelock.
1190 config ARM_ERRATA_411920
1191 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1192 depends on CPU_V6 || CPU_V6K
1194 Invalidation of the Instruction Cache operation can
1195 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1196 It does not affect the MPCore. This option enables the ARM Ltd.
1197 recommended workaround.
1199 config ARM_ERRATA_430973
1200 bool "ARM errata: Stale prediction on replaced interworking branch"
1203 This option enables the workaround for the 430973 Cortex-A8
1204 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1205 interworking branch is replaced with another code sequence at the
1206 same virtual address, whether due to self-modifying code or virtual
1207 to physical address re-mapping, Cortex-A8 does not recover from the
1208 stale interworking branch prediction. This results in Cortex-A8
1209 executing the new code sequence in the incorrect ARM or Thumb state.
1210 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1211 and also flushes the branch target cache at every context switch.
1212 Note that setting specific bits in the ACTLR register may not be
1213 available in non-secure mode.
1215 config ARM_ERRATA_458693
1216 bool "ARM errata: Processor deadlock when a false hazard is created"
1219 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1220 erratum. For very specific sequences of memory operations, it is
1221 possible for a hazard condition intended for a cache line to instead
1222 be incorrectly associated with a different cache line. This false
1223 hazard might then cause a processor deadlock. The workaround enables
1224 the L1 caching of the NEON accesses and disables the PLD instruction
1225 in the ACTLR register. Note that setting specific bits in the ACTLR
1226 register may not be available in non-secure mode.
1228 config ARM_ERRATA_460075
1229 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1232 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1233 erratum. Any asynchronous access to the L2 cache may encounter a
1234 situation in which recent store transactions to the L2 cache are lost
1235 and overwritten with stale memory contents from external memory. The
1236 workaround disables the write-allocate mode for the L2 cache via the
1237 ACTLR register. Note that setting specific bits in the ACTLR register
1238 may not be available in non-secure mode.
1240 config ARM_ERRATA_742230
1241 bool "ARM errata: DMB operation may be faulty"
1242 depends on CPU_V7 && SMP
1244 This option enables the workaround for the 742230 Cortex-A9
1245 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1246 between two write operations may not ensure the correct visibility
1247 ordering of the two writes. This workaround sets a specific bit in
1248 the diagnostic register of the Cortex-A9 which causes the DMB
1249 instruction to behave as a DSB, ensuring the correct behaviour of
1252 config ARM_ERRATA_742231
1253 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1254 depends on CPU_V7 && SMP
1256 This option enables the workaround for the 742231 Cortex-A9
1257 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1258 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1259 accessing some data located in the same cache line, may get corrupted
1260 data due to bad handling of the address hazard when the line gets
1261 replaced from one of the CPUs at the same time as another CPU is
1262 accessing it. This workaround sets specific bits in the diagnostic
1263 register of the Cortex-A9 which reduces the linefill issuing
1264 capabilities of the processor.
1266 config PL310_ERRATA_588369
1267 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1268 depends on CACHE_L2X0
1270 The PL310 L2 cache controller implements three types of Clean &
1271 Invalidate maintenance operations: by Physical Address
1272 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1273 They are architecturally defined to behave as the execution of a
1274 clean operation followed immediately by an invalidate operation,
1275 both performing to the same memory location. This functionality
1276 is not correctly implemented in PL310 as clean lines are not
1277 invalidated as a result of these operations.
1279 config ARM_ERRATA_720789
1280 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1283 This option enables the workaround for the 720789 Cortex-A9 (prior to
1284 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1285 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1286 As a consequence of this erratum, some TLB entries which should be
1287 invalidated are not, resulting in an incoherency in the system page
1288 tables. The workaround changes the TLB flushing routines to invalidate
1289 entries regardless of the ASID.
1291 config PL310_ERRATA_727915
1292 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1293 depends on CACHE_L2X0
1295 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1296 operation (offset 0x7FC). This operation runs in background so that
1297 PL310 can handle normal accesses while it is in progress. Under very
1298 rare circumstances, due to this erratum, write data can be lost when
1299 PL310 treats a cacheable write transaction during a Clean &
1300 Invalidate by Way operation.
1302 config ARM_ERRATA_743622
1303 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1306 This option enables the workaround for the 743622 Cortex-A9
1307 (r2p*) erratum. Under very rare conditions, a faulty
1308 optimisation in the Cortex-A9 Store Buffer may lead to data
1309 corruption. This workaround sets a specific bit in the diagnostic
1310 register of the Cortex-A9 which disables the Store Buffer
1311 optimisation, preventing the defect from occurring. This has no
1312 visible impact on the overall performance or power consumption of the
1315 config ARM_ERRATA_751472
1316 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1319 This option enables the workaround for the 751472 Cortex-A9 (prior
1320 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1321 completion of a following broadcasted operation if the second
1322 operation is received by a CPU before the ICIALLUIS has completed,
1323 potentially leading to corrupted entries in the cache or TLB.
1325 config PL310_ERRATA_753970
1326 bool "PL310 errata: cache sync operation may be faulty"
1327 depends on CACHE_PL310
1329 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1331 Under some condition the effect of cache sync operation on
1332 the store buffer still remains when the operation completes.
1333 This means that the store buffer is always asked to drain and
1334 this prevents it from merging any further writes. The workaround
1335 is to replace the normal offset of cache sync operation (0x730)
1336 by another offset targeting an unmapped PL310 register 0x740.
1337 This has the same effect as the cache sync operation: store buffer
1338 drain and waiting for all buffers empty.
1340 config ARM_ERRATA_754322
1341 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1344 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1345 r3p*) erratum. A speculative memory access may cause a page table walk
1346 which starts prior to an ASID switch but completes afterwards. This
1347 can populate the micro-TLB with a stale entry which may be hit with
1348 the new ASID. This workaround places two dsb instructions in the mm
1349 switching code so that no page table walks can cross the ASID switch.
1351 config ARM_ERRATA_754327
1352 bool "ARM errata: no automatic Store Buffer drain"
1353 depends on CPU_V7 && SMP
1355 This option enables the workaround for the 754327 Cortex-A9 (prior to
1356 r2p0) erratum. The Store Buffer does not have any automatic draining
1357 mechanism and therefore a livelock may occur if an external agent
1358 continuously polls a memory location waiting to observe an update.
1359 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1360 written polling loops from denying visibility of updates to memory.
1362 config ARM_ERRATA_364296
1363 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1364 depends on CPU_V6 && !SMP
1366 This options enables the workaround for the 364296 ARM1136
1367 r0p2 erratum (possible cache data corruption with
1368 hit-under-miss enabled). It sets the undocumented bit 31 in
1369 the auxiliary control register and the FI bit in the control
1370 register, thus disabling hit-under-miss without putting the
1371 processor into full low interrupt latency mode. ARM11MPCore
1374 config ARM_ERRATA_764369
1375 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1376 depends on CPU_V7 && SMP
1378 This option enables the workaround for erratum 764369
1379 affecting Cortex-A9 MPCore with two or more processors (all
1380 current revisions). Under certain timing circumstances, a data
1381 cache line maintenance operation by MVA targeting an Inner
1382 Shareable memory region may fail to proceed up to either the
1383 Point of Coherency or to the Point of Unification of the
1384 system. This workaround adds a DSB instruction before the
1385 relevant cache maintenance functions and sets a specific bit
1386 in the diagnostic control register of the SCU.
1388 config PL310_ERRATA_769419
1389 bool "PL310 errata: no automatic Store Buffer drain"
1390 depends on CACHE_L2X0
1392 On revisions of the PL310 prior to r3p2, the Store Buffer does
1393 not automatically drain. This can cause normal, non-cacheable
1394 writes to be retained when the memory system is idle, leading
1395 to suboptimal I/O performance for drivers using coherent DMA.
1396 This option adds a write barrier to the cpu_idle loop so that,
1397 on systems with an outer cache, the store buffer is drained
1402 source "arch/arm/common/Kconfig"
1412 Find out whether you have ISA slots on your motherboard. ISA is the
1413 name of a bus system, i.e. the way the CPU talks to the other stuff
1414 inside your box. Other bus systems are PCI, EISA, MicroChannel
1415 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1416 newer boards don't support it. If you have ISA, say Y, otherwise N.
1418 # Select ISA DMA controller support
1423 # Select ISA DMA interface
1428 bool "PCI support" if MIGHT_HAVE_PCI
1430 Find out whether you have a PCI motherboard. PCI is the name of a
1431 bus system, i.e. the way the CPU talks to the other stuff inside
1432 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1433 VESA. If you have PCI, say Y, otherwise N.
1439 config PCI_NANOENGINE
1440 bool "BSE nanoEngine PCI support"
1441 depends on SA1100_NANOENGINE
1443 Enable PCI on the BSE nanoEngine board.
1448 # Select the host bridge type
1449 config PCI_HOST_VIA82C505
1451 depends on PCI && ARCH_SHARK
1454 config PCI_HOST_ITE8152
1456 depends on PCI && MACH_ARMCORE
1460 source "drivers/pci/Kconfig"
1462 source "drivers/pcmcia/Kconfig"
1466 menu "Kernel Features"
1468 source "kernel/time/Kconfig"
1473 This option should be selected by machines which have an SMP-
1476 The only effect of this option is to make the SMP-related
1477 options available to the user for configuration.
1480 bool "Symmetric Multi-Processing"
1481 depends on CPU_V6K || CPU_V7
1482 depends on GENERIC_CLOCKEVENTS
1485 select USE_GENERIC_SMP_HELPERS
1486 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1488 This enables support for systems with more than one CPU. If you have
1489 a system with only one CPU, like most personal computers, say N. If
1490 you have a system with more than one CPU, say Y.
1492 If you say N here, the kernel will run on single and multiprocessor
1493 machines, but will use only one CPU of a multiprocessor machine. If
1494 you say Y here, the kernel will run on many, but not all, single
1495 processor machines. On a single processor machine, the kernel will
1496 run faster if you say N here.
1498 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1499 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1500 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1502 If you don't know what to do here, say N.
1505 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1506 depends on EXPERIMENTAL
1507 depends on SMP && !XIP_KERNEL
1510 SMP kernels contain instructions which fail on non-SMP processors.
1511 Enabling this option allows the kernel to modify itself to make
1512 these instructions safe. Disabling it allows about 1K of space
1515 If you don't know what to do here, say Y.
1517 config ARM_CPU_TOPOLOGY
1518 bool "Support cpu topology definition"
1519 depends on SMP && CPU_V7
1522 Support ARM cpu topology definition. The MPIDR register defines
1523 affinity between processors which is then used to describe the cpu
1524 topology of an ARM System.
1527 bool "Multi-core scheduler support"
1528 depends on ARM_CPU_TOPOLOGY
1530 Multi-core scheduler support improves the CPU scheduler's decision
1531 making when dealing with multi-core CPU chips at a cost of slightly
1532 increased overhead in some places. If unsure say N here.
1535 bool "SMT scheduler support"
1536 depends on ARM_CPU_TOPOLOGY
1538 Improves the CPU scheduler's decision making when dealing with
1539 MultiThreading at a cost of slightly increased overhead in some
1540 places. If unsure say N here.
1545 This option enables support for the ARM system coherency unit
1552 This options enables support for the ARM timer and watchdog unit
1555 prompt "Memory split"
1558 Select the desired split between kernel and user memory.
1560 If you are not absolutely sure what you are doing, leave this
1564 bool "3G/1G user/kernel split"
1566 bool "2G/2G user/kernel split"
1568 bool "1G/3G user/kernel split"
1573 default 0x40000000 if VMSPLIT_1G
1574 default 0x80000000 if VMSPLIT_2G
1578 int "Maximum number of CPUs (2-32)"
1584 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1585 depends on SMP && HOTPLUG && EXPERIMENTAL
1587 Say Y here to experiment with turning CPUs off and on. CPUs
1588 can be controlled through /sys/devices/system/cpu.
1591 bool "Use local timer interrupts"
1594 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1596 Enable support for local timers on SMP platforms, rather then the
1597 legacy IPI broadcast method. Local timers allows the system
1598 accounting to be spread across the timer interval, preventing a
1599 "thundering herd" at every timer tick.
1603 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1604 default 355 if ARCH_U8500
1605 default 264 if MACH_H4700
1608 Maximum number of GPIOs in the system.
1610 If unsure, leave the default value.
1612 source kernel/Kconfig.preempt
1616 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1617 ARCH_S5PV210 || ARCH_EXYNOS4
1618 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1619 default AT91_TIMER_HZ if ARCH_AT91
1620 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1623 config THUMB2_KERNEL
1624 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1625 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1627 select ARM_ASM_UNIFIED
1630 By enabling this option, the kernel will be compiled in
1631 Thumb-2 mode. A compiler/assembler that understand the unified
1632 ARM-Thumb syntax is needed.
1636 config THUMB2_AVOID_R_ARM_THM_JUMP11
1637 bool "Work around buggy Thumb-2 short branch relocations in gas"
1638 depends on THUMB2_KERNEL && MODULES
1641 Various binutils versions can resolve Thumb-2 branches to
1642 locally-defined, preemptible global symbols as short-range "b.n"
1643 branch instructions.
1645 This is a problem, because there's no guarantee the final
1646 destination of the symbol, or any candidate locations for a
1647 trampoline, are within range of the branch. For this reason, the
1648 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1649 relocation in modules at all, and it makes little sense to add
1652 The symptom is that the kernel fails with an "unsupported
1653 relocation" error when loading some modules.
1655 Until fixed tools are available, passing
1656 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1657 code which hits this problem, at the cost of a bit of extra runtime
1658 stack usage in some cases.
1660 The problem is described in more detail at:
1661 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1663 Only Thumb-2 kernels are affected.
1665 Unless you are sure your tools don't have this problem, say Y.
1667 config ARM_ASM_UNIFIED
1671 bool "Use the ARM EABI to compile the kernel"
1673 This option allows for the kernel to be compiled using the latest
1674 ARM ABI (aka EABI). This is only useful if you are using a user
1675 space environment that is also compiled with EABI.
1677 Since there are major incompatibilities between the legacy ABI and
1678 EABI, especially with regard to structure member alignment, this
1679 option also changes the kernel syscall calling convention to
1680 disambiguate both ABIs and allow for backward compatibility support
1681 (selected with CONFIG_OABI_COMPAT).
1683 To use this you need GCC version 4.0.0 or later.
1686 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1687 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1690 This option preserves the old syscall interface along with the
1691 new (ARM EABI) one. It also provides a compatibility layer to
1692 intercept syscalls that have structure arguments which layout
1693 in memory differs between the legacy ABI and the new ARM EABI
1694 (only for non "thumb" binaries). This option adds a tiny
1695 overhead to all syscalls and produces a slightly larger kernel.
1696 If you know you'll be using only pure EABI user space then you
1697 can say N here. If this option is not selected and you attempt
1698 to execute a legacy ABI binary then the result will be
1699 UNPREDICTABLE (in fact it can be predicted that it won't work
1700 at all). If in doubt say Y.
1702 config ARCH_HAS_HOLES_MEMORYMODEL
1705 config ARCH_SPARSEMEM_ENABLE
1708 config ARCH_SPARSEMEM_DEFAULT
1709 def_bool ARCH_SPARSEMEM_ENABLE
1711 config ARCH_SELECT_MEMORY_MODEL
1712 def_bool ARCH_SPARSEMEM_ENABLE
1714 config HAVE_ARCH_PFN_VALID
1715 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1718 bool "High Memory Support"
1721 The address space of ARM processors is only 4 Gigabytes large
1722 and it has to accommodate user address space, kernel address
1723 space as well as some memory mapped IO. That means that, if you
1724 have a large amount of physical memory and/or IO, not all of the
1725 memory can be "permanently mapped" by the kernel. The physical
1726 memory that is not permanently mapped is called "high memory".
1728 Depending on the selected kernel/user memory split, minimum
1729 vmalloc space and actual amount of RAM, you may not need this
1730 option which should result in a slightly faster kernel.
1735 bool "Allocate 2nd-level pagetables from highmem"
1738 config HW_PERF_EVENTS
1739 bool "Enable hardware performance counter support for perf events"
1740 depends on PERF_EVENTS && CPU_HAS_PMU
1743 Enable hardware performance counter support for perf events. If
1744 disabled, perf events will use software events only.
1748 config FORCE_MAX_ZONEORDER
1749 int "Maximum zone order" if ARCH_SHMOBILE
1750 range 11 64 if ARCH_SHMOBILE
1751 default "9" if SA1111
1754 The kernel memory allocator divides physically contiguous memory
1755 blocks into "zones", where each zone is a power of two number of
1756 pages. This option selects the largest power of two that the kernel
1757 keeps in the memory allocator. If you need to allocate very large
1758 blocks of physically contiguous memory, then you may need to
1759 increase this value.
1761 This config option is actually maximum order plus one. For example,
1762 a value of 11 means that the largest free memory block is 2^10 pages.
1765 bool "Timer and CPU usage LEDs"
1766 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1767 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1768 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1769 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1770 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1771 ARCH_AT91 || ARCH_DAVINCI || \
1772 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1774 If you say Y here, the LEDs on your machine will be used
1775 to provide useful information about your current system status.
1777 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1778 be able to select which LEDs are active using the options below. If
1779 you are compiling a kernel for the EBSA-110 or the LART however, the
1780 red LED will simply flash regularly to indicate that the system is
1781 still functional. It is safe to say Y here if you have a CATS
1782 system, but the driver will do nothing.
1785 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1786 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1787 || MACH_OMAP_PERSEUS2
1789 depends on !GENERIC_CLOCKEVENTS
1790 default y if ARCH_EBSA110
1792 If you say Y here, one of the system LEDs (the green one on the
1793 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1794 will flash regularly to indicate that the system is still
1795 operational. This is mainly useful to kernel hackers who are
1796 debugging unstable kernels.
1798 The LART uses the same LED for both Timer LED and CPU usage LED
1799 functions. You may choose to use both, but the Timer LED function
1800 will overrule the CPU usage LED.
1803 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1805 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1806 || MACH_OMAP_PERSEUS2
1809 If you say Y here, the red LED will be used to give a good real
1810 time indication of CPU usage, by lighting whenever the idle task
1811 is not currently executing.
1813 The LART uses the same LED for both Timer LED and CPU usage LED
1814 functions. You may choose to use both, but the Timer LED function
1815 will overrule the CPU usage LED.
1817 config ALIGNMENT_TRAP
1819 depends on CPU_CP15_MMU
1820 default y if !ARCH_EBSA110
1821 select HAVE_PROC_CPU if PROC_FS
1823 ARM processors cannot fetch/store information which is not
1824 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1825 address divisible by 4. On 32-bit ARM processors, these non-aligned
1826 fetch/store instructions will be emulated in software if you say
1827 here, which has a severe performance impact. This is necessary for
1828 correct operation of some network protocols. With an IP-only
1829 configuration it is safe to say N, otherwise say Y.
1831 config UACCESS_WITH_MEMCPY
1832 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1833 depends on MMU && EXPERIMENTAL
1834 default y if CPU_FEROCEON
1836 Implement faster copy_to_user and clear_user methods for CPU
1837 cores where a 8-word STM instruction give significantly higher
1838 memory write throughput than a sequence of individual 32bit stores.
1840 A possible side effect is a slight increase in scheduling latency
1841 between threads sharing the same address space if they invoke
1842 such copy operations with large buffers.
1844 However, if the CPU data cache is using a write-allocate mode,
1845 this option is unlikely to provide any performance gain.
1849 prompt "Enable seccomp to safely compute untrusted bytecode"
1851 This kernel feature is useful for number crunching applications
1852 that may need to compute untrusted bytecode during their
1853 execution. By using pipes or other transports made available to
1854 the process as file descriptors supporting the read/write
1855 syscalls, it's possible to isolate those applications in
1856 their own address space using seccomp. Once seccomp is
1857 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1858 and the task is only allowed to execute a few safe syscalls
1859 defined by each seccomp mode.
1861 config CC_STACKPROTECTOR
1862 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1863 depends on EXPERIMENTAL
1865 This option turns on the -fstack-protector GCC feature. This
1866 feature puts, at the beginning of functions, a canary value on
1867 the stack just before the return address, and validates
1868 the value just before actually returning. Stack based buffer
1869 overflows (that need to overwrite this return address) now also
1870 overwrite the canary, which gets detected and the attack is then
1871 neutralized via a kernel panic.
1872 This feature requires gcc version 4.2 or above.
1874 config DEPRECATED_PARAM_STRUCT
1875 bool "Provide old way to pass kernel parameters"
1877 This was deprecated in 2001 and announced to live on for 5 years.
1878 Some old boot loaders still use this way.
1885 bool "Flattened Device Tree support"
1887 select OF_EARLY_FLATTREE
1890 Include support for flattened device tree machine descriptions.
1892 # Compressed boot loader in ROM. Yes, we really want to ask about
1893 # TEXT and BSS so we preserve their values in the config files.
1894 config ZBOOT_ROM_TEXT
1895 hex "Compressed ROM boot loader base address"
1898 The physical address at which the ROM-able zImage is to be
1899 placed in the target. Platforms which normally make use of
1900 ROM-able zImage formats normally set this to a suitable
1901 value in their defconfig file.
1903 If ZBOOT_ROM is not enabled, this has no effect.
1905 config ZBOOT_ROM_BSS
1906 hex "Compressed ROM boot loader BSS address"
1909 The base address of an area of read/write memory in the target
1910 for the ROM-able zImage which must be available while the
1911 decompressor is running. It must be large enough to hold the
1912 entire decompressed kernel plus an additional 128 KiB.
1913 Platforms which normally make use of ROM-able zImage formats
1914 normally set this to a suitable value in their defconfig file.
1916 If ZBOOT_ROM is not enabled, this has no effect.
1919 bool "Compressed boot loader in ROM/flash"
1920 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1922 Say Y here if you intend to execute your compressed kernel image
1923 (zImage) directly from ROM or flash. If unsure, say N.
1926 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1927 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1928 default ZBOOT_ROM_NONE
1930 Include experimental SD/MMC loading code in the ROM-able zImage.
1931 With this enabled it is possible to write the the ROM-able zImage
1932 kernel image to an MMC or SD card and boot the kernel straight
1933 from the reset vector. At reset the processor Mask ROM will load
1934 the first part of the the ROM-able zImage which in turn loads the
1935 rest the kernel image to RAM.
1937 config ZBOOT_ROM_NONE
1938 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1940 Do not load image from SD or MMC
1942 config ZBOOT_ROM_MMCIF
1943 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1945 Load image from MMCIF hardware block.
1947 config ZBOOT_ROM_SH_MOBILE_SDHI
1948 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1950 Load image from SDHI hardware block
1954 config ARM_APPENDED_DTB
1955 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1956 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1958 With this option, the boot code will look for a device tree binary
1959 (DTB) appended to zImage
1960 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1962 This is meant as a backward compatibility convenience for those
1963 systems with a bootloader that can't be upgraded to accommodate
1964 the documented boot protocol using a device tree.
1966 Beware that there is very little in terms of protection against
1967 this option being confused by leftover garbage in memory that might
1968 look like a DTB header after a reboot if no actual DTB is appended
1969 to zImage. Do not leave this option active in a production kernel
1970 if you don't intend to always append a DTB. Proper passing of the
1971 location into r2 of a bootloader provided DTB is always preferable
1974 config ARM_ATAG_DTB_COMPAT
1975 bool "Supplement the appended DTB with traditional ATAG information"
1976 depends on ARM_APPENDED_DTB
1978 Some old bootloaders can't be updated to a DTB capable one, yet
1979 they provide ATAGs with memory configuration, the ramdisk address,
1980 the kernel cmdline string, etc. Such information is dynamically
1981 provided by the bootloader and can't always be stored in a static
1982 DTB. To allow a device tree enabled kernel to be used with such
1983 bootloaders, this option allows zImage to extract the information
1984 from the ATAG list and store it at run time into the appended DTB.
1987 string "Default kernel command string"
1990 On some architectures (EBSA110 and CATS), there is currently no way
1991 for the boot loader to pass arguments to the kernel. For these
1992 architectures, you should supply some command-line options at build
1993 time by entering them here. As a minimum, you should specify the
1994 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1997 prompt "Kernel command line type" if CMDLINE != ""
1998 default CMDLINE_FROM_BOOTLOADER
2000 config CMDLINE_FROM_BOOTLOADER
2001 bool "Use bootloader kernel arguments if available"
2003 Uses the command-line options passed by the boot loader. If
2004 the boot loader doesn't provide any, the default kernel command
2005 string provided in CMDLINE will be used.
2007 config CMDLINE_EXTEND
2008 bool "Extend bootloader kernel arguments"
2010 The command-line arguments provided by the boot loader will be
2011 appended to the default kernel command string.
2013 config CMDLINE_FORCE
2014 bool "Always use the default kernel command string"
2016 Always use the default kernel command string, even if the boot
2017 loader passes other arguments to the kernel.
2018 This is useful if you cannot or don't want to change the
2019 command-line options your boot loader passes to the kernel.
2023 bool "Kernel Execute-In-Place from ROM"
2024 depends on !ZBOOT_ROM && !ARM_LPAE
2026 Execute-In-Place allows the kernel to run from non-volatile storage
2027 directly addressable by the CPU, such as NOR flash. This saves RAM
2028 space since the text section of the kernel is not loaded from flash
2029 to RAM. Read-write sections, such as the data section and stack,
2030 are still copied to RAM. The XIP kernel is not compressed since
2031 it has to run directly from flash, so it will take more space to
2032 store it. The flash address used to link the kernel object files,
2033 and for storing it, is configuration dependent. Therefore, if you
2034 say Y here, you must know the proper physical address where to
2035 store the kernel image depending on your own flash memory usage.
2037 Also note that the make target becomes "make xipImage" rather than
2038 "make zImage" or "make Image". The final kernel binary to put in
2039 ROM memory will be arch/arm/boot/xipImage.
2043 config XIP_PHYS_ADDR
2044 hex "XIP Kernel Physical Location"
2045 depends on XIP_KERNEL
2046 default "0x00080000"
2048 This is the physical address in your flash memory the kernel will
2049 be linked for and stored to. This address is dependent on your
2053 bool "Kexec system call (EXPERIMENTAL)"
2054 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2056 kexec is a system call that implements the ability to shutdown your
2057 current kernel, and to start another kernel. It is like a reboot
2058 but it is independent of the system firmware. And like a reboot
2059 you can start any kernel with it, not just Linux.
2061 It is an ongoing process to be certain the hardware in a machine
2062 is properly shutdown, so do not be surprised if this code does not
2063 initially work for you. It may help to enable device hotplugging
2067 bool "Export atags in procfs"
2071 Should the atags used to boot the kernel be exported in an "atags"
2072 file in procfs. Useful with kexec.
2075 bool "Build kdump crash kernel (EXPERIMENTAL)"
2076 depends on EXPERIMENTAL
2078 Generate crash dump after being started by kexec. This should
2079 be normally only set in special crash dump kernels which are
2080 loaded in the main kernel with kexec-tools into a specially
2081 reserved region and then later executed after a crash by
2082 kdump/kexec. The crash dump kernel must be compiled to a
2083 memory address not used by the main kernel
2085 For more details see Documentation/kdump/kdump.txt
2087 config AUTO_ZRELADDR
2088 bool "Auto calculation of the decompressed kernel image address"
2089 depends on !ZBOOT_ROM && !ARCH_U300
2091 ZRELADDR is the physical address where the decompressed kernel
2092 image will be placed. If AUTO_ZRELADDR is selected, the address
2093 will be determined at run-time by masking the current IP with
2094 0xf8000000. This assumes the zImage being placed in the first 128MB
2095 from start of memory.
2099 menu "CPU Power Management"
2103 source "drivers/cpufreq/Kconfig"
2106 tristate "CPUfreq driver for i.MX CPUs"
2107 depends on ARCH_MXC && CPU_FREQ
2109 This enables the CPUfreq driver for i.MX CPUs.
2111 config CPU_FREQ_SA1100
2114 config CPU_FREQ_SA1110
2117 config CPU_FREQ_INTEGRATOR
2118 tristate "CPUfreq driver for ARM Integrator CPUs"
2119 depends on ARCH_INTEGRATOR && CPU_FREQ
2122 This enables the CPUfreq driver for ARM Integrator CPUs.
2124 For details, take a look at <file:Documentation/cpu-freq>.
2130 depends on CPU_FREQ && ARCH_PXA && PXA25x
2132 select CPU_FREQ_TABLE
2133 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2138 Internal configuration node for common cpufreq on Samsung SoC
2140 config CPU_FREQ_S3C24XX
2141 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2142 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2145 This enables the CPUfreq driver for the Samsung S3C24XX family
2148 For details, take a look at <file:Documentation/cpu-freq>.
2152 config CPU_FREQ_S3C24XX_PLL
2153 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2154 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2156 Compile in support for changing the PLL frequency from the
2157 S3C24XX series CPUfreq driver. The PLL takes time to settle
2158 after a frequency change, so by default it is not enabled.
2160 This also means that the PLL tables for the selected CPU(s) will
2161 be built which may increase the size of the kernel image.
2163 config CPU_FREQ_S3C24XX_DEBUG
2164 bool "Debug CPUfreq Samsung driver core"
2165 depends on CPU_FREQ_S3C24XX
2167 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2169 config CPU_FREQ_S3C24XX_IODEBUG
2170 bool "Debug CPUfreq Samsung driver IO timing"
2171 depends on CPU_FREQ_S3C24XX
2173 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2175 config CPU_FREQ_S3C24XX_DEBUGFS
2176 bool "Export debugfs for CPUFreq"
2177 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2179 Export status information via debugfs.
2183 source "drivers/cpuidle/Kconfig"
2187 menu "Floating point emulation"
2189 comment "At least one emulation must be selected"
2192 bool "NWFPE math emulation"
2193 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2195 Say Y to include the NWFPE floating point emulator in the kernel.
2196 This is necessary to run most binaries. Linux does not currently
2197 support floating point hardware so you need to say Y here even if
2198 your machine has an FPA or floating point co-processor podule.
2200 You may say N here if you are going to load the Acorn FPEmulator
2201 early in the bootup.
2204 bool "Support extended precision"
2205 depends on FPE_NWFPE
2207 Say Y to include 80-bit support in the kernel floating-point
2208 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2209 Note that gcc does not generate 80-bit operations by default,
2210 so in most cases this option only enlarges the size of the
2211 floating point emulator without any good reason.
2213 You almost surely want to say N here.
2216 bool "FastFPE math emulation (EXPERIMENTAL)"
2217 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2219 Say Y here to include the FAST floating point emulator in the kernel.
2220 This is an experimental much faster emulator which now also has full
2221 precision for the mantissa. It does not support any exceptions.
2222 It is very simple, and approximately 3-6 times faster than NWFPE.
2224 It should be sufficient for most programs. It may be not suitable
2225 for scientific calculations, but you have to check this for yourself.
2226 If you do not feel you need a faster FP emulation you should better
2230 bool "VFP-format floating point maths"
2231 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2233 Say Y to include VFP support code in the kernel. This is needed
2234 if your hardware includes a VFP unit.
2236 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2237 release notes and additional status information.
2239 Say N if your target does not have VFP hardware.
2247 bool "Advanced SIMD (NEON) Extension support"
2248 depends on VFPv3 && CPU_V7
2250 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2255 menu "Userspace binary formats"
2257 source "fs/Kconfig.binfmt"
2260 tristate "RISC OS personality"
2263 Say Y here to include the kernel code necessary if you want to run
2264 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2265 experimental; if this sounds frightening, say N and sleep in peace.
2266 You can also say M here to compile this support as a module (which
2267 will be called arthur).
2271 menu "Power management options"
2273 source "kernel/power/Kconfig"
2275 config ARCH_SUSPEND_POSSIBLE
2276 depends on !ARCH_S5PC100
2277 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2278 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2281 config ARM_CPU_SUSPEND
2286 source "net/Kconfig"
2288 source "drivers/Kconfig"
2292 source "arch/arm/Kconfig.debug"
2294 source "security/Kconfig"
2296 source "crypto/Kconfig"
2298 source "lib/Kconfig"