4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_ELF_RANDOMIZE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_USE_BUILTIN_BSWAP
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_EXTABLE_SORT if MMU
15 select CLONE_BACKWARDS
16 select CPU_PM if (SUSPEND || CPU_IDLE)
17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
19 select EDAC_ATOMIC_SCRUB
20 select GENERIC_ALLOCATOR
21 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
22 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
23 select GENERIC_IDLE_POLL_SETUP
24 select GENERIC_IRQ_PROBE
25 select GENERIC_IRQ_SHOW
26 select GENERIC_IRQ_SHOW_LEVEL
27 select GENERIC_PCI_IOMAP
28 select GENERIC_SCHED_CLOCK
29 select GENERIC_SMP_IDLE_THREAD
30 select GENERIC_STRNCPY_FROM_USER
31 select GENERIC_STRNLEN_USER
32 select HANDLE_DOMAIN_IRQ
33 select HARDIRQS_SW_RESEND
34 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
35 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
36 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32
37 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32
38 select HAVE_ARCH_MMAP_RND_BITS if MMU
39 select HAVE_ARCH_HARDENED_USERCOPY
40 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
41 select HAVE_ARCH_TRACEHOOK
42 select HAVE_ARM_SMCCC if CPU_V7
44 select HAVE_CC_STACKPROTECTOR
45 select HAVE_CONTEXT_TRACKING
46 select HAVE_C_RECORDMCOUNT
47 select HAVE_DEBUG_KMEMLEAK
48 select HAVE_DMA_API_DEBUG
50 select HAVE_DMA_CONTIGUOUS if MMU
51 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32
52 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
53 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
54 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
55 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
56 select HAVE_GENERIC_DMA_COHERENT
57 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
58 select HAVE_IDE if PCI || ISA || PCMCIA
59 select HAVE_IRQ_TIME_ACCOUNTING
60 select HAVE_KERNEL_GZIP
61 select HAVE_KERNEL_LZ4
62 select HAVE_KERNEL_LZMA
63 select HAVE_KERNEL_LZO
65 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
66 select HAVE_KRETPROBES if (HAVE_KPROBES)
68 select HAVE_MOD_ARCH_SPECIFIC
69 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
70 select HAVE_OPTPROBES if !THUMB2_KERNEL
71 select HAVE_PERF_EVENTS
73 select HAVE_PERF_USER_STACK_DUMP
74 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
75 select HAVE_REGS_AND_STACK_ACCESS_API
76 select HAVE_SYSCALL_TRACEPOINTS
78 select HAVE_VIRT_CPU_ACCOUNTING_GEN
79 select IRQ_FORCED_THREADING
80 select MODULES_USE_ELF_REL
82 select OF_EARLY_FLATTREE if OF
83 select OF_RESERVED_MEM if OF
85 select OLD_SIGSUSPEND3
86 select PERF_USE_VMALLOC
88 select SYS_SUPPORTS_APM_EMULATION
89 # Above selects are sorted alphabetically; please add new ones
90 # according to that. Thanks.
92 The ARM series is a line of low-power-consumption RISC chip designs
93 licensed by ARM Ltd and targeted at embedded applications and
94 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
95 manufactured, but legacy ARM-based PC hardware remains popular in
96 Europe. There is an ARM Linux project with a web page at
97 <http://www.arm.linux.org.uk/>.
99 config ARM_HAS_SG_CHAIN
100 select ARCH_HAS_SG_CHAIN
103 config NEED_SG_DMA_LENGTH
106 config ARM_DMA_USE_IOMMU
108 select ARM_HAS_SG_CHAIN
109 select NEED_SG_DMA_LENGTH
112 config MIGHT_HAVE_PCI
115 config SYS_SUPPORTS_APM_EMULATION
120 select GENERIC_ALLOCATOR
131 The Extended Industry Standard Architecture (EISA) bus was
132 developed as an open alternative to the IBM MicroChannel bus.
134 The EISA bus provided some of the features of the IBM MicroChannel
135 bus while maintaining backward compatibility with cards made for
136 the older ISA bus. The EISA bus saw limited use between 1988 and
137 1995 when it was made obsolete by the PCI bus.
139 Say Y here if you are building a kernel for an EISA-based machine.
146 config STACKTRACE_SUPPORT
150 config HAVE_LATENCYTOP_SUPPORT
155 config LOCKDEP_SUPPORT
159 config TRACE_IRQFLAGS_SUPPORT
163 config RWSEM_XCHGADD_ALGORITHM
167 config ARCH_HAS_ILOG2_U32
170 config ARCH_HAS_ILOG2_U64
173 config ARCH_HAS_BANDGAP
176 config FIX_EARLYCON_MEM
179 config GENERIC_HWEIGHT
183 config GENERIC_CALIBRATE_DELAY
187 config ARCH_MAY_HAVE_PC_FDC
193 config NEED_DMA_MAP_STATE
196 config ARCH_SUPPORTS_UPROBES
199 config ARCH_HAS_DMA_SET_COHERENT_MASK
202 config GENERIC_ISA_DMA
208 config NEED_RET_TO_USER
216 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
217 default DRAM_BASE if REMAP_VECTORS_TO_RAM
220 The base address of exception vectors. This must be two pages
223 config ARM_PATCH_PHYS_VIRT
224 bool "Patch physical to virtual translations at runtime" if EMBEDDED
226 depends on !XIP_KERNEL && MMU
227 depends on !ARCH_REALVIEW || !SPARSEMEM
229 Patch phys-to-virt and virt-to-phys translation functions at
230 boot and module load time according to the position of the
231 kernel in system memory.
233 This can only be used with non-XIP MMU kernels where the base
234 of physical memory is at a 16MB boundary.
236 Only disable this option if you know that you do not require
237 this feature (eg, building a kernel for a single machine) and
238 you need to shrink the kernel to the minimal size.
240 config NEED_MACH_IO_H
243 Select this when mach/io.h is required to provide special
244 definitions for this platform. The need for mach/io.h should
245 be avoided when possible.
247 config NEED_MACH_MEMORY_H
250 Select this when mach/memory.h is required to provide special
251 definitions for this platform. The need for mach/memory.h should
252 be avoided when possible.
255 hex "Physical address of main memory" if MMU
256 depends on !ARM_PATCH_PHYS_VIRT
257 default DRAM_BASE if !MMU
258 default 0x00000000 if ARCH_EBSA110 || \
263 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
264 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
265 default 0x20000000 if ARCH_S5PV210
266 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
267 default 0xc0000000 if ARCH_SA1100
269 Please provide the physical address corresponding to the
270 location of main memory in your system.
276 config PGTABLE_LEVELS
278 default 3 if ARM_LPAE
281 source "init/Kconfig"
283 source "kernel/Kconfig.freezer"
288 bool "MMU-based Paged Memory Management Support"
291 Select if you want MMU-based virtualised addressing space
292 support by paged memory management. If unsure, say 'Y'.
294 config ARCH_MMAP_RND_BITS_MIN
297 config ARCH_MMAP_RND_BITS_MAX
298 default 14 if PAGE_OFFSET=0x40000000
299 default 15 if PAGE_OFFSET=0x80000000
303 # The "ARM system type" choice list is ordered alphabetically by option
304 # text. Please add new entries in the option alphabetic order.
307 prompt "ARM system type"
308 default ARCH_VERSATILE if !MMU
309 default ARCH_MULTIPLATFORM if MMU
311 config ARCH_MULTIPLATFORM
312 bool "Allow multiple platforms to be selected"
314 select ARCH_WANT_OPTIONAL_GPIOLIB
315 select ARM_HAS_SG_CHAIN
316 select ARM_PATCH_PHYS_VIRT
320 select GENERIC_CLOCKEVENTS
321 select MIGHT_HAVE_PCI
322 select MULTI_IRQ_HANDLER
326 config ARM_SINGLE_ARMV7M
327 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
329 select ARCH_WANT_OPTIONAL_GPIOLIB
335 select GENERIC_CLOCKEVENTS
341 bool "ARM Ltd. RealView family"
342 select ARCH_WANT_OPTIONAL_GPIOLIB
344 select ARM_TIMER_SP804
346 select COMMON_CLK_VERSATILE
347 select GENERIC_CLOCKEVENTS
348 select GPIO_PL061 if GPIOLIB
350 select NEED_MACH_MEMORY_H
351 select PLAT_VERSATILE
352 select PLAT_VERSATILE_SCHED_CLOCK
354 This enables support for ARM Ltd RealView boards.
356 config ARCH_VERSATILE
357 bool "ARM Ltd. Versatile family"
358 select ARCH_WANT_OPTIONAL_GPIOLIB
360 select ARM_TIMER_SP804
363 select GENERIC_CLOCKEVENTS
364 select HAVE_MACH_CLKDEV
366 select PLAT_VERSATILE
367 select PLAT_VERSATILE_CLOCK
368 select PLAT_VERSATILE_SCHED_CLOCK
369 select VERSATILE_FPGA_IRQ
371 This enables support for ARM Ltd Versatile board.
374 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
375 select ARCH_REQUIRE_GPIOLIB
380 select GENERIC_CLOCKEVENTS
384 Support for Cirrus Logic 711x/721x/731x based boards.
387 bool "Cortina Systems Gemini"
388 select ARCH_REQUIRE_GPIOLIB
391 select GENERIC_CLOCKEVENTS
393 Support for the Cortina Systems Gemini family SoCs
397 select ARCH_USES_GETTIMEOFFSET
400 select NEED_MACH_IO_H
401 select NEED_MACH_MEMORY_H
404 This is an evaluation board for the StrongARM processor available
405 from Digital. It has limited hardware on-board, including an
406 Ethernet interface, two PCMCIA sockets, two serial ports and a
411 select ARCH_HAS_HOLES_MEMORYMODEL
412 select ARCH_REQUIRE_GPIOLIB
414 select ARM_PATCH_PHYS_VIRT
420 select GENERIC_CLOCKEVENTS
422 This enables support for the Cirrus EP93xx series of CPUs.
424 config ARCH_FOOTBRIDGE
428 select GENERIC_CLOCKEVENTS
430 select NEED_MACH_IO_H if !MMU
431 select NEED_MACH_MEMORY_H
433 Support for systems based on the DC21285 companion chip
434 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
437 bool "Hilscher NetX based"
441 select GENERIC_CLOCKEVENTS
443 This enables support for systems based on the Hilscher NetX Soc
449 select NEED_MACH_MEMORY_H
450 select NEED_RET_TO_USER
456 Support for Intel's IOP13XX (XScale) family of processors.
461 select ARCH_REQUIRE_GPIOLIB
464 select NEED_RET_TO_USER
468 Support for Intel's 80219 and IOP32X (XScale) family of
474 select ARCH_REQUIRE_GPIOLIB
477 select NEED_RET_TO_USER
481 Support for Intel's IOP33X (XScale) family of processors.
486 select ARCH_HAS_DMA_SET_COHERENT_MASK
487 select ARCH_REQUIRE_GPIOLIB
488 select ARCH_SUPPORTS_BIG_ENDIAN
491 select DMABOUNCE if PCI
492 select GENERIC_CLOCKEVENTS
493 select MIGHT_HAVE_PCI
494 select NEED_MACH_IO_H
495 select USB_EHCI_BIG_ENDIAN_DESC
496 select USB_EHCI_BIG_ENDIAN_MMIO
498 Support for Intel's IXP4XX (XScale) family of processors.
502 select ARCH_REQUIRE_GPIOLIB
504 select GENERIC_CLOCKEVENTS
505 select MIGHT_HAVE_PCI
509 select PLAT_ORION_LEGACY
511 Support for the Marvell Dove SoC 88AP510
514 bool "Marvell MV78xx0"
515 select ARCH_REQUIRE_GPIOLIB
517 select GENERIC_CLOCKEVENTS
520 select PLAT_ORION_LEGACY
522 Support for the following Marvell MV78xx0 series SoCs:
528 select ARCH_REQUIRE_GPIOLIB
530 select GENERIC_CLOCKEVENTS
533 select PLAT_ORION_LEGACY
534 select MULTI_IRQ_HANDLER
536 Support for the following Marvell Orion 5x series SoCs:
537 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
538 Orion-2 (5281), Orion-1-90 (6183).
541 bool "Marvell PXA168/910/MMP2"
543 select ARCH_REQUIRE_GPIOLIB
545 select GENERIC_ALLOCATOR
546 select GENERIC_CLOCKEVENTS
549 select MULTI_IRQ_HANDLER
554 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
557 bool "Micrel/Kendin KS8695"
558 select ARCH_REQUIRE_GPIOLIB
561 select GENERIC_CLOCKEVENTS
562 select NEED_MACH_MEMORY_H
564 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
565 System-on-Chip devices.
568 bool "Nuvoton W90X900 CPU"
569 select ARCH_REQUIRE_GPIOLIB
573 select GENERIC_CLOCKEVENTS
575 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
576 At present, the w90x900 has been renamed nuc900, regarding
577 the ARM series product line, you can login the following
578 link address to know more.
580 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
581 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
585 select ARCH_REQUIRE_GPIOLIB
590 select GENERIC_CLOCKEVENTS
594 Support for the NXP LPC32XX family of processors
597 bool "PXA2xx/PXA3xx-based"
600 select ARCH_REQUIRE_GPIOLIB
601 select ARM_CPU_SUSPEND if PM
607 select GENERIC_CLOCKEVENTS
611 select MULTI_IRQ_HANDLER
615 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
621 select ARCH_MAY_HAVE_PC_FDC
622 select ARCH_SPARSEMEM_ENABLE
623 select ARCH_USES_GETTIMEOFFSET
627 select HAVE_PATA_PLATFORM
629 select NEED_MACH_IO_H
630 select NEED_MACH_MEMORY_H
634 On the Acorn Risc-PC, Linux can support the internal IDE disk and
635 CD-ROM interface, serial and parallel port, and the floppy drive.
640 select ARCH_REQUIRE_GPIOLIB
641 select ARCH_SPARSEMEM_ENABLE
646 select GENERIC_CLOCKEVENTS
650 select MULTI_IRQ_HANDLER
651 select NEED_MACH_MEMORY_H
654 Support for StrongARM 11x0 based boards.
657 bool "Samsung S3C24XX SoCs"
658 select ARCH_REQUIRE_GPIOLIB
661 select CLKSRC_SAMSUNG_PWM
662 select GENERIC_CLOCKEVENTS
664 select HAVE_S3C2410_I2C if I2C
665 select HAVE_S3C2410_WATCHDOG if WATCHDOG
666 select HAVE_S3C_RTC if RTC_CLASS
667 select MULTI_IRQ_HANDLER
668 select NEED_MACH_IO_H
671 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
672 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
673 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
674 Samsung SMDK2410 development board (and derivatives).
677 bool "Samsung S3C64XX"
678 select ARCH_REQUIRE_GPIOLIB
683 select CLKSRC_SAMSUNG_PWM
684 select COMMON_CLK_SAMSUNG
686 select GENERIC_CLOCKEVENTS
688 select HAVE_S3C2410_I2C if I2C
689 select HAVE_S3C2410_WATCHDOG if WATCHDOG
693 select PM_GENERIC_DOMAINS if PM
695 select S3C_GPIO_TRACK
697 select SAMSUNG_WAKEMASK
698 select SAMSUNG_WDT_RESET
700 Samsung S3C64XX series based systems
704 select ARCH_HAS_HOLES_MEMORYMODEL
705 select ARCH_REQUIRE_GPIOLIB
707 select GENERIC_ALLOCATOR
708 select GENERIC_CLOCKEVENTS
709 select GENERIC_IRQ_CHIP
714 Support for TI's DaVinci platform.
719 select ARCH_HAS_HOLES_MEMORYMODEL
721 select ARCH_REQUIRE_GPIOLIB
724 select GENERIC_CLOCKEVENTS
725 select GENERIC_IRQ_CHIP
728 select MULTI_IRQ_HANDLER
729 select NEED_MACH_IO_H if PCCARD
730 select NEED_MACH_MEMORY_H
733 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
737 menu "Multiple platform selection"
738 depends on ARCH_MULTIPLATFORM
740 comment "CPU Core family selection"
743 bool "ARMv4 based platforms (FA526)"
744 depends on !ARCH_MULTI_V6_V7
745 select ARCH_MULTI_V4_V5
748 config ARCH_MULTI_V4T
749 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
750 depends on !ARCH_MULTI_V6_V7
751 select ARCH_MULTI_V4_V5
752 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
753 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
754 CPU_ARM925T || CPU_ARM940T)
757 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
758 depends on !ARCH_MULTI_V6_V7
759 select ARCH_MULTI_V4_V5
760 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
761 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
762 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
764 config ARCH_MULTI_V4_V5
768 bool "ARMv6 based platforms (ARM11)"
769 select ARCH_MULTI_V6_V7
773 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
775 select ARCH_MULTI_V6_V7
779 config ARCH_MULTI_V6_V7
781 select MIGHT_HAVE_CACHE_L2X0
783 config ARCH_MULTI_CPU_AUTO
784 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
790 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
795 select HAVE_ARM_ARCH_TIMER
798 # This is sorted alphabetically by mach-* pathname. However, plat-*
799 # Kconfigs may be included either alphabetically (according to the
800 # plat- suffix) or along side the corresponding mach-* source.
802 source "arch/arm/mach-mvebu/Kconfig"
804 source "arch/arm/mach-alpine/Kconfig"
806 source "arch/arm/mach-asm9260/Kconfig"
808 source "arch/arm/mach-at91/Kconfig"
810 source "arch/arm/mach-axxia/Kconfig"
812 source "arch/arm/mach-bcm/Kconfig"
814 source "arch/arm/mach-berlin/Kconfig"
816 source "arch/arm/mach-clps711x/Kconfig"
818 source "arch/arm/mach-cns3xxx/Kconfig"
820 source "arch/arm/mach-davinci/Kconfig"
822 source "arch/arm/mach-digicolor/Kconfig"
824 source "arch/arm/mach-dove/Kconfig"
826 source "arch/arm/mach-ep93xx/Kconfig"
828 source "arch/arm/mach-footbridge/Kconfig"
830 source "arch/arm/mach-gemini/Kconfig"
832 source "arch/arm/mach-highbank/Kconfig"
834 source "arch/arm/mach-hisi/Kconfig"
836 source "arch/arm/mach-integrator/Kconfig"
838 source "arch/arm/mach-iop32x/Kconfig"
840 source "arch/arm/mach-iop33x/Kconfig"
842 source "arch/arm/mach-iop13xx/Kconfig"
844 source "arch/arm/mach-ixp4xx/Kconfig"
846 source "arch/arm/mach-keystone/Kconfig"
848 source "arch/arm/mach-ks8695/Kconfig"
850 source "arch/arm/mach-meson/Kconfig"
852 source "arch/arm/mach-moxart/Kconfig"
854 source "arch/arm/mach-mv78xx0/Kconfig"
856 source "arch/arm/mach-imx/Kconfig"
858 source "arch/arm/mach-mediatek/Kconfig"
860 source "arch/arm/mach-mxs/Kconfig"
862 source "arch/arm/mach-netx/Kconfig"
864 source "arch/arm/mach-nomadik/Kconfig"
866 source "arch/arm/mach-nspire/Kconfig"
868 source "arch/arm/plat-omap/Kconfig"
870 source "arch/arm/mach-omap1/Kconfig"
872 source "arch/arm/mach-omap2/Kconfig"
874 source "arch/arm/mach-orion5x/Kconfig"
876 source "arch/arm/mach-picoxcell/Kconfig"
878 source "arch/arm/mach-pxa/Kconfig"
879 source "arch/arm/plat-pxa/Kconfig"
881 source "arch/arm/mach-mmp/Kconfig"
883 source "arch/arm/mach-qcom/Kconfig"
885 source "arch/arm/mach-realview/Kconfig"
887 source "arch/arm/mach-rockchip/Kconfig"
889 source "arch/arm/mach-sa1100/Kconfig"
891 source "arch/arm/mach-socfpga/Kconfig"
893 source "arch/arm/mach-spear/Kconfig"
895 source "arch/arm/mach-sti/Kconfig"
897 source "arch/arm/mach-s3c24xx/Kconfig"
899 source "arch/arm/mach-s3c64xx/Kconfig"
901 source "arch/arm/mach-s5pv210/Kconfig"
903 source "arch/arm/mach-exynos/Kconfig"
904 source "arch/arm/plat-samsung/Kconfig"
906 source "arch/arm/mach-shmobile/Kconfig"
908 source "arch/arm/mach-sunxi/Kconfig"
910 source "arch/arm/mach-prima2/Kconfig"
912 source "arch/arm/mach-tegra/Kconfig"
914 source "arch/arm/mach-u300/Kconfig"
916 source "arch/arm/mach-uniphier/Kconfig"
918 source "arch/arm/mach-ux500/Kconfig"
920 source "arch/arm/mach-versatile/Kconfig"
922 source "arch/arm/mach-vexpress/Kconfig"
923 source "arch/arm/plat-versatile/Kconfig"
925 source "arch/arm/mach-vt8500/Kconfig"
927 source "arch/arm/mach-w90x900/Kconfig"
929 source "arch/arm/mach-zx/Kconfig"
931 source "arch/arm/mach-zynq/Kconfig"
933 # ARMv7-M architecture
935 bool "Energy Micro efm32"
936 depends on ARM_SINGLE_ARMV7M
937 select ARCH_REQUIRE_GPIOLIB
939 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
943 bool "NXP LPC18xx/LPC43xx"
944 depends on ARM_SINGLE_ARMV7M
945 select ARCH_HAS_RESET_CONTROLLER
947 select CLKSRC_LPC32XX
950 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
951 high performance microcontrollers.
954 bool "STMicrolectronics STM32"
955 depends on ARM_SINGLE_ARMV7M
956 select ARCH_HAS_RESET_CONTROLLER
957 select ARMV7M_SYSTICK
959 select RESET_CONTROLLER
961 Support for STMicroelectronics STM32 processors.
963 # Definitions to make life easier
969 select GENERIC_CLOCKEVENTS
975 select GENERIC_IRQ_CHIP
978 config PLAT_ORION_LEGACY
985 config PLAT_VERSATILE
988 source "arch/arm/firmware/Kconfig"
990 source arch/arm/mm/Kconfig
993 bool "Enable iWMMXt support"
994 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
995 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
997 Enable support for iWMMXt context switching at run time if
998 running on a CPU that supports it.
1000 config MULTI_IRQ_HANDLER
1003 Allow each machine to specify it's own IRQ handler at run time.
1006 source "arch/arm/Kconfig-nommu"
1009 config PJ4B_ERRATA_4742
1010 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1011 depends on CPU_PJ4B && MACH_ARMADA_370
1014 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1015 Event (WFE) IDLE states, a specific timing sensitivity exists between
1016 the retiring WFI/WFE instructions and the newly issued subsequent
1017 instructions. This sensitivity can result in a CPU hang scenario.
1019 The software must insert either a Data Synchronization Barrier (DSB)
1020 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1023 config ARM_ERRATA_326103
1024 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1027 Executing a SWP instruction to read-only memory does not set bit 11
1028 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1029 treat the access as a read, preventing a COW from occurring and
1030 causing the faulting task to livelock.
1032 config ARM_ERRATA_411920
1033 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1034 depends on CPU_V6 || CPU_V6K
1036 Invalidation of the Instruction Cache operation can
1037 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1038 It does not affect the MPCore. This option enables the ARM Ltd.
1039 recommended workaround.
1041 config ARM_ERRATA_430973
1042 bool "ARM errata: Stale prediction on replaced interworking branch"
1045 This option enables the workaround for the 430973 Cortex-A8
1046 r1p* erratum. If a code sequence containing an ARM/Thumb
1047 interworking branch is replaced with another code sequence at the
1048 same virtual address, whether due to self-modifying code or virtual
1049 to physical address re-mapping, Cortex-A8 does not recover from the
1050 stale interworking branch prediction. This results in Cortex-A8
1051 executing the new code sequence in the incorrect ARM or Thumb state.
1052 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1053 and also flushes the branch target cache at every context switch.
1054 Note that setting specific bits in the ACTLR register may not be
1055 available in non-secure mode.
1057 config ARM_ERRATA_458693
1058 bool "ARM errata: Processor deadlock when a false hazard is created"
1060 depends on !ARCH_MULTIPLATFORM
1062 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1063 erratum. For very specific sequences of memory operations, it is
1064 possible for a hazard condition intended for a cache line to instead
1065 be incorrectly associated with a different cache line. This false
1066 hazard might then cause a processor deadlock. The workaround enables
1067 the L1 caching of the NEON accesses and disables the PLD instruction
1068 in the ACTLR register. Note that setting specific bits in the ACTLR
1069 register may not be available in non-secure mode.
1071 config ARM_ERRATA_460075
1072 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1074 depends on !ARCH_MULTIPLATFORM
1076 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1077 erratum. Any asynchronous access to the L2 cache may encounter a
1078 situation in which recent store transactions to the L2 cache are lost
1079 and overwritten with stale memory contents from external memory. The
1080 workaround disables the write-allocate mode for the L2 cache via the
1081 ACTLR register. Note that setting specific bits in the ACTLR register
1082 may not be available in non-secure mode.
1084 config ARM_ERRATA_742230
1085 bool "ARM errata: DMB operation may be faulty"
1086 depends on CPU_V7 && SMP
1087 depends on !ARCH_MULTIPLATFORM
1089 This option enables the workaround for the 742230 Cortex-A9
1090 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1091 between two write operations may not ensure the correct visibility
1092 ordering of the two writes. This workaround sets a specific bit in
1093 the diagnostic register of the Cortex-A9 which causes the DMB
1094 instruction to behave as a DSB, ensuring the correct behaviour of
1097 config ARM_ERRATA_742231
1098 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1099 depends on CPU_V7 && SMP
1100 depends on !ARCH_MULTIPLATFORM
1102 This option enables the workaround for the 742231 Cortex-A9
1103 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1104 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1105 accessing some data located in the same cache line, may get corrupted
1106 data due to bad handling of the address hazard when the line gets
1107 replaced from one of the CPUs at the same time as another CPU is
1108 accessing it. This workaround sets specific bits in the diagnostic
1109 register of the Cortex-A9 which reduces the linefill issuing
1110 capabilities of the processor.
1112 config ARM_ERRATA_643719
1113 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1114 depends on CPU_V7 && SMP
1117 This option enables the workaround for the 643719 Cortex-A9 (prior to
1118 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1119 register returns zero when it should return one. The workaround
1120 corrects this value, ensuring cache maintenance operations which use
1121 it behave as intended and avoiding data corruption.
1123 config ARM_ERRATA_720789
1124 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1127 This option enables the workaround for the 720789 Cortex-A9 (prior to
1128 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1129 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1130 As a consequence of this erratum, some TLB entries which should be
1131 invalidated are not, resulting in an incoherency in the system page
1132 tables. The workaround changes the TLB flushing routines to invalidate
1133 entries regardless of the ASID.
1135 config ARM_ERRATA_743622
1136 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1138 depends on !ARCH_MULTIPLATFORM
1140 This option enables the workaround for the 743622 Cortex-A9
1141 (r2p*) erratum. Under very rare conditions, a faulty
1142 optimisation in the Cortex-A9 Store Buffer may lead to data
1143 corruption. This workaround sets a specific bit in the diagnostic
1144 register of the Cortex-A9 which disables the Store Buffer
1145 optimisation, preventing the defect from occurring. This has no
1146 visible impact on the overall performance or power consumption of the
1149 config ARM_ERRATA_751472
1150 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1152 depends on !ARCH_MULTIPLATFORM
1154 This option enables the workaround for the 751472 Cortex-A9 (prior
1155 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1156 completion of a following broadcasted operation if the second
1157 operation is received by a CPU before the ICIALLUIS has completed,
1158 potentially leading to corrupted entries in the cache or TLB.
1160 config ARM_ERRATA_754322
1161 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1164 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1165 r3p*) erratum. A speculative memory access may cause a page table walk
1166 which starts prior to an ASID switch but completes afterwards. This
1167 can populate the micro-TLB with a stale entry which may be hit with
1168 the new ASID. This workaround places two dsb instructions in the mm
1169 switching code so that no page table walks can cross the ASID switch.
1171 config ARM_ERRATA_754327
1172 bool "ARM errata: no automatic Store Buffer drain"
1173 depends on CPU_V7 && SMP
1175 This option enables the workaround for the 754327 Cortex-A9 (prior to
1176 r2p0) erratum. The Store Buffer does not have any automatic draining
1177 mechanism and therefore a livelock may occur if an external agent
1178 continuously polls a memory location waiting to observe an update.
1179 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1180 written polling loops from denying visibility of updates to memory.
1182 config ARM_ERRATA_364296
1183 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1186 This options enables the workaround for the 364296 ARM1136
1187 r0p2 erratum (possible cache data corruption with
1188 hit-under-miss enabled). It sets the undocumented bit 31 in
1189 the auxiliary control register and the FI bit in the control
1190 register, thus disabling hit-under-miss without putting the
1191 processor into full low interrupt latency mode. ARM11MPCore
1194 config ARM_ERRATA_764369
1195 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1196 depends on CPU_V7 && SMP
1198 This option enables the workaround for erratum 764369
1199 affecting Cortex-A9 MPCore with two or more processors (all
1200 current revisions). Under certain timing circumstances, a data
1201 cache line maintenance operation by MVA targeting an Inner
1202 Shareable memory region may fail to proceed up to either the
1203 Point of Coherency or to the Point of Unification of the
1204 system. This workaround adds a DSB instruction before the
1205 relevant cache maintenance functions and sets a specific bit
1206 in the diagnostic control register of the SCU.
1208 config ARM_ERRATA_775420
1209 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1212 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1213 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1214 operation aborts with MMU exception, it might cause the processor
1215 to deadlock. This workaround puts DSB before executing ISB if
1216 an abort may occur on cache maintenance.
1218 config ARM_ERRATA_798181
1219 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1220 depends on CPU_V7 && SMP
1222 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1223 adequately shooting down all use of the old entries. This
1224 option enables the Linux kernel workaround for this erratum
1225 which sends an IPI to the CPUs that are running the same ASID
1226 as the one being invalidated.
1228 config ARM_ERRATA_773022
1229 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1232 This option enables the workaround for the 773022 Cortex-A15
1233 (up to r0p4) erratum. In certain rare sequences of code, the
1234 loop buffer may deliver incorrect instructions. This
1235 workaround disables the loop buffer to avoid the erratum.
1239 source "arch/arm/common/Kconfig"
1246 Find out whether you have ISA slots on your motherboard. ISA is the
1247 name of a bus system, i.e. the way the CPU talks to the other stuff
1248 inside your box. Other bus systems are PCI, EISA, MicroChannel
1249 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1250 newer boards don't support it. If you have ISA, say Y, otherwise N.
1252 # Select ISA DMA controller support
1257 # Select ISA DMA interface
1262 bool "PCI support" if MIGHT_HAVE_PCI
1264 Find out whether you have a PCI motherboard. PCI is the name of a
1265 bus system, i.e. the way the CPU talks to the other stuff inside
1266 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1267 VESA. If you have PCI, say Y, otherwise N.
1273 config PCI_DOMAINS_GENERIC
1274 def_bool PCI_DOMAINS
1276 config PCI_NANOENGINE
1277 bool "BSE nanoEngine PCI support"
1278 depends on SA1100_NANOENGINE
1280 Enable PCI on the BSE nanoEngine board.
1285 config PCI_HOST_ITE8152
1287 depends on PCI && MACH_ARMCORE
1291 source "drivers/pci/Kconfig"
1292 source "drivers/pci/pcie/Kconfig"
1294 source "drivers/pcmcia/Kconfig"
1298 menu "Kernel Features"
1303 This option should be selected by machines which have an SMP-
1306 The only effect of this option is to make the SMP-related
1307 options available to the user for configuration.
1310 bool "Symmetric Multi-Processing"
1311 depends on CPU_V6K || CPU_V7
1312 depends on GENERIC_CLOCKEVENTS
1314 depends on MMU || ARM_MPU
1317 This enables support for systems with more than one CPU. If you have
1318 a system with only one CPU, say N. If you have a system with more
1319 than one CPU, say Y.
1321 If you say N here, the kernel will run on uni- and multiprocessor
1322 machines, but will use only one CPU of a multiprocessor machine. If
1323 you say Y here, the kernel will run on many, but not all,
1324 uniprocessor machines. On a uniprocessor machine, the kernel
1325 will run faster if you say N here.
1327 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1328 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1329 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1331 If you don't know what to do here, say N.
1334 bool "Allow booting SMP kernel on uniprocessor systems"
1335 depends on SMP && !XIP_KERNEL && MMU
1338 SMP kernels contain instructions which fail on non-SMP processors.
1339 Enabling this option allows the kernel to modify itself to make
1340 these instructions safe. Disabling it allows about 1K of space
1343 If you don't know what to do here, say Y.
1345 config ARM_CPU_TOPOLOGY
1346 bool "Support cpu topology definition"
1347 depends on SMP && CPU_V7
1350 Support ARM cpu topology definition. The MPIDR register defines
1351 affinity between processors which is then used to describe the cpu
1352 topology of an ARM System.
1355 bool "Multi-core scheduler support"
1356 depends on ARM_CPU_TOPOLOGY
1358 Multi-core scheduler support improves the CPU scheduler's decision
1359 making when dealing with multi-core CPU chips at a cost of slightly
1360 increased overhead in some places. If unsure say N here.
1363 bool "SMT scheduler support"
1364 depends on ARM_CPU_TOPOLOGY
1366 Improves the CPU scheduler's decision making when dealing with
1367 MultiThreading at a cost of slightly increased overhead in some
1368 places. If unsure say N here.
1373 This option enables support for the ARM system coherency unit
1375 config HAVE_ARM_ARCH_TIMER
1376 bool "Architected timer support"
1378 select ARM_ARCH_TIMER
1379 select GENERIC_CLOCKEVENTS
1381 This option enables support for the ARM architected timer
1385 select CLKSRC_OF if OF
1387 This options enables support for the ARM timer and watchdog unit
1390 bool "Multi-Cluster Power Management"
1391 depends on CPU_V7 && SMP
1393 This option provides the common power management infrastructure
1394 for (multi-)cluster based systems, such as big.LITTLE based
1397 config MCPM_QUAD_CLUSTER
1401 To avoid wasting resources unnecessarily, MCPM only supports up
1402 to 2 clusters by default.
1403 Platforms with 3 or 4 clusters that use MCPM must select this
1404 option to allow the additional clusters to be managed.
1407 bool "big.LITTLE support (Experimental)"
1408 depends on CPU_V7 && SMP
1411 This option enables support selections for the big.LITTLE
1412 system architecture.
1415 bool "big.LITTLE switcher support"
1416 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1419 The big.LITTLE "switcher" provides the core functionality to
1420 transparently handle transition between a cluster of A15's
1421 and a cluster of A7's in a big.LITTLE system.
1423 config BL_SWITCHER_DUMMY_IF
1424 tristate "Simple big.LITTLE switcher user interface"
1425 depends on BL_SWITCHER && DEBUG_KERNEL
1427 This is a simple and dummy char dev interface to control
1428 the big.LITTLE switcher core code. It is meant for
1429 debugging purposes only.
1432 prompt "Memory split"
1436 Select the desired split between kernel and user memory.
1438 If you are not absolutely sure what you are doing, leave this
1442 bool "3G/1G user/kernel split"
1443 config VMSPLIT_3G_OPT
1444 bool "3G/1G user/kernel split (for full 1G low memory)"
1446 bool "2G/2G user/kernel split"
1448 bool "1G/3G user/kernel split"
1453 default PHYS_OFFSET if !MMU
1454 default 0x40000000 if VMSPLIT_1G
1455 default 0x80000000 if VMSPLIT_2G
1456 default 0xB0000000 if VMSPLIT_3G_OPT
1460 int "Maximum number of CPUs (2-32)"
1466 bool "Support for hot-pluggable CPUs"
1469 Say Y here to experiment with turning CPUs off and on. CPUs
1470 can be controlled through /sys/devices/system/cpu.
1473 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1474 depends on HAVE_ARM_SMCCC
1477 Say Y here if you want Linux to communicate with system firmware
1478 implementing the PSCI specification for CPU-centric power
1479 management operations described in ARM document number ARM DEN
1480 0022A ("Power State Coordination Interface System Software on
1483 # The GPIO number here must be sorted by descending number. In case of
1484 # a multiplatform kernel, we just want the highest value required by the
1485 # selected platforms.
1488 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1490 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1491 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1492 default 416 if ARCH_SUNXI
1493 default 392 if ARCH_U8500
1494 default 352 if ARCH_VT8500
1495 default 288 if ARCH_ROCKCHIP
1496 default 264 if MACH_H4700
1499 Maximum number of GPIOs in the system.
1501 If unsure, leave the default value.
1503 source kernel/Kconfig.preempt
1507 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1508 ARCH_S5PV210 || ARCH_EXYNOS4
1509 default 128 if SOC_AT91RM9200
1513 depends on HZ_FIXED = 0
1514 prompt "Timer frequency"
1538 default HZ_FIXED if HZ_FIXED != 0
1539 default 100 if HZ_100
1540 default 200 if HZ_200
1541 default 250 if HZ_250
1542 default 300 if HZ_300
1543 default 500 if HZ_500
1547 def_bool HIGH_RES_TIMERS
1549 config THUMB2_KERNEL
1550 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1551 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1552 default y if CPU_THUMBONLY
1554 select ARM_ASM_UNIFIED
1557 By enabling this option, the kernel will be compiled in
1558 Thumb-2 mode. A compiler/assembler that understand the unified
1559 ARM-Thumb syntax is needed.
1563 config THUMB2_AVOID_R_ARM_THM_JUMP11
1564 bool "Work around buggy Thumb-2 short branch relocations in gas"
1565 depends on THUMB2_KERNEL && MODULES
1568 Various binutils versions can resolve Thumb-2 branches to
1569 locally-defined, preemptible global symbols as short-range "b.n"
1570 branch instructions.
1572 This is a problem, because there's no guarantee the final
1573 destination of the symbol, or any candidate locations for a
1574 trampoline, are within range of the branch. For this reason, the
1575 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1576 relocation in modules at all, and it makes little sense to add
1579 The symptom is that the kernel fails with an "unsupported
1580 relocation" error when loading some modules.
1582 Until fixed tools are available, passing
1583 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1584 code which hits this problem, at the cost of a bit of extra runtime
1585 stack usage in some cases.
1587 The problem is described in more detail at:
1588 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1590 Only Thumb-2 kernels are affected.
1592 Unless you are sure your tools don't have this problem, say Y.
1594 config ARM_ASM_UNIFIED
1598 bool "Use the ARM EABI to compile the kernel"
1600 This option allows for the kernel to be compiled using the latest
1601 ARM ABI (aka EABI). This is only useful if you are using a user
1602 space environment that is also compiled with EABI.
1604 Since there are major incompatibilities between the legacy ABI and
1605 EABI, especially with regard to structure member alignment, this
1606 option also changes the kernel syscall calling convention to
1607 disambiguate both ABIs and allow for backward compatibility support
1608 (selected with CONFIG_OABI_COMPAT).
1610 To use this you need GCC version 4.0.0 or later.
1613 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1614 depends on AEABI && !THUMB2_KERNEL
1616 This option preserves the old syscall interface along with the
1617 new (ARM EABI) one. It also provides a compatibility layer to
1618 intercept syscalls that have structure arguments which layout
1619 in memory differs between the legacy ABI and the new ARM EABI
1620 (only for non "thumb" binaries). This option adds a tiny
1621 overhead to all syscalls and produces a slightly larger kernel.
1623 The seccomp filter system will not be available when this is
1624 selected, since there is no way yet to sensibly distinguish
1625 between calling conventions during filtering.
1627 If you know you'll be using only pure EABI user space then you
1628 can say N here. If this option is not selected and you attempt
1629 to execute a legacy ABI binary then the result will be
1630 UNPREDICTABLE (in fact it can be predicted that it won't work
1631 at all). If in doubt say N.
1633 config ARCH_HAS_HOLES_MEMORYMODEL
1636 config ARCH_SPARSEMEM_ENABLE
1639 config ARCH_SPARSEMEM_DEFAULT
1640 def_bool ARCH_SPARSEMEM_ENABLE
1642 config ARCH_SELECT_MEMORY_MODEL
1643 def_bool ARCH_SPARSEMEM_ENABLE
1645 config HAVE_ARCH_PFN_VALID
1646 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1648 config HAVE_GENERIC_RCU_GUP
1653 bool "High Memory Support"
1656 The address space of ARM processors is only 4 Gigabytes large
1657 and it has to accommodate user address space, kernel address
1658 space as well as some memory mapped IO. That means that, if you
1659 have a large amount of physical memory and/or IO, not all of the
1660 memory can be "permanently mapped" by the kernel. The physical
1661 memory that is not permanently mapped is called "high memory".
1663 Depending on the selected kernel/user memory split, minimum
1664 vmalloc space and actual amount of RAM, you may not need this
1665 option which should result in a slightly faster kernel.
1670 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1674 The VM uses one page of physical memory for each page table.
1675 For systems with a lot of processes, this can use a lot of
1676 precious low memory, eventually leading to low memory being
1677 consumed by page tables. Setting this option will allow
1678 user-space 2nd level page tables to reside in high memory.
1680 config CPU_SW_DOMAIN_PAN
1681 bool "Enable use of CPU domains to implement privileged no-access"
1682 depends on MMU && !ARM_LPAE
1685 Increase kernel security by ensuring that normal kernel accesses
1686 are unable to access userspace addresses. This can help prevent
1687 use-after-free bugs becoming an exploitable privilege escalation
1688 by ensuring that magic values (such as LIST_POISON) will always
1689 fault when dereferenced.
1691 CPUs with low-vector mappings use a best-efforts implementation.
1692 Their lower 1MB needs to remain accessible for the vectors, but
1693 the remainder of userspace will become appropriately inaccessible.
1695 config HW_PERF_EVENTS
1699 config SYS_SUPPORTS_HUGETLBFS
1703 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1707 config ARCH_WANT_GENERAL_HUGETLB
1710 config ARM_MODULE_PLTS
1711 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1714 Allocate PLTs when loading modules so that jumps and calls whose
1715 targets are too far away for their relative offsets to be encoded
1716 in the instructions themselves can be bounced via veneers in the
1717 module's PLT. This allows modules to be allocated in the generic
1718 vmalloc area after the dedicated module memory area has been
1719 exhausted. The modules will use slightly more memory, but after
1720 rounding up to page size, the actual memory footprint is usually
1723 Say y if you are getting out of memory errors while loading modules
1727 config FORCE_MAX_ZONEORDER
1728 int "Maximum zone order"
1729 default "12" if SOC_AM33XX
1730 default "9" if SA1111 || ARCH_EFM32
1733 The kernel memory allocator divides physically contiguous memory
1734 blocks into "zones", where each zone is a power of two number of
1735 pages. This option selects the largest power of two that the kernel
1736 keeps in the memory allocator. If you need to allocate very large
1737 blocks of physically contiguous memory, then you may need to
1738 increase this value.
1740 This config option is actually maximum order plus one. For example,
1741 a value of 11 means that the largest free memory block is 2^10 pages.
1743 config ALIGNMENT_TRAP
1745 depends on CPU_CP15_MMU
1746 default y if !ARCH_EBSA110
1747 select HAVE_PROC_CPU if PROC_FS
1749 ARM processors cannot fetch/store information which is not
1750 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1751 address divisible by 4. On 32-bit ARM processors, these non-aligned
1752 fetch/store instructions will be emulated in software if you say
1753 here, which has a severe performance impact. This is necessary for
1754 correct operation of some network protocols. With an IP-only
1755 configuration it is safe to say N, otherwise say Y.
1757 config UACCESS_WITH_MEMCPY
1758 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1760 default y if CPU_FEROCEON
1762 Implement faster copy_to_user and clear_user methods for CPU
1763 cores where a 8-word STM instruction give significantly higher
1764 memory write throughput than a sequence of individual 32bit stores.
1766 A possible side effect is a slight increase in scheduling latency
1767 between threads sharing the same address space if they invoke
1768 such copy operations with large buffers.
1770 However, if the CPU data cache is using a write-allocate mode,
1771 this option is unlikely to provide any performance gain.
1775 prompt "Enable seccomp to safely compute untrusted bytecode"
1777 This kernel feature is useful for number crunching applications
1778 that may need to compute untrusted bytecode during their
1779 execution. By using pipes or other transports made available to
1780 the process as file descriptors supporting the read/write
1781 syscalls, it's possible to isolate those applications in
1782 their own address space using seccomp. Once seccomp is
1783 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1784 and the task is only allowed to execute a few safe syscalls
1785 defined by each seccomp mode.
1798 bool "Xen guest support on ARM"
1799 depends on ARM && AEABI && OF
1800 depends on CPU_V7 && !CPU_V6
1801 depends on !GENERIC_ATOMIC64
1803 select ARCH_DMA_ADDR_T_64BIT
1807 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1809 config ARM_FLUSH_CONSOLE_ON_RESTART
1810 bool "Force flush the console on restart"
1812 If the console is locked while the system is rebooted, the messages
1813 in the temporary logbuffer would not have propogated to all the
1814 console drivers. This option forces the console lock to be
1815 released if it failed to be acquired, which will cause all the
1816 pending messages to be flushed.
1823 bool "Flattened Device Tree support"
1827 Include support for flattened device tree machine descriptions.
1830 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1833 This is the traditional way of passing data to the kernel at boot
1834 time. If you are solely relying on the flattened device tree (or
1835 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1836 to remove ATAGS support from your kernel binary. If unsure,
1839 config DEPRECATED_PARAM_STRUCT
1840 bool "Provide old way to pass kernel parameters"
1843 This was deprecated in 2001 and announced to live on for 5 years.
1844 Some old boot loaders still use this way.
1846 config BUILD_ARM_APPENDED_DTB_IMAGE
1847 bool "Build a concatenated zImage/dtb by default"
1850 Enabling this option will cause a concatenated zImage and list of
1851 DTBs to be built by default (instead of a standalone zImage.)
1852 The image will built in arch/arm/boot/zImage-dtb
1854 config BUILD_ARM_APPENDED_DTB_IMAGE_NAMES
1855 string "Default dtb names"
1856 depends on BUILD_ARM_APPENDED_DTB_IMAGE
1858 Space separated list of names of dtbs to append when
1859 building a concatenated zImage-dtb.
1861 # Compressed boot loader in ROM. Yes, we really want to ask about
1862 # TEXT and BSS so we preserve their values in the config files.
1863 config ZBOOT_ROM_TEXT
1864 hex "Compressed ROM boot loader base address"
1867 The physical address at which the ROM-able zImage is to be
1868 placed in the target. Platforms which normally make use of
1869 ROM-able zImage formats normally set this to a suitable
1870 value in their defconfig file.
1872 If ZBOOT_ROM is not enabled, this has no effect.
1874 config ZBOOT_ROM_BSS
1875 hex "Compressed ROM boot loader BSS address"
1878 The base address of an area of read/write memory in the target
1879 for the ROM-able zImage which must be available while the
1880 decompressor is running. It must be large enough to hold the
1881 entire decompressed kernel plus an additional 128 KiB.
1882 Platforms which normally make use of ROM-able zImage formats
1883 normally set this to a suitable value in their defconfig file.
1885 If ZBOOT_ROM is not enabled, this has no effect.
1888 bool "Compressed boot loader in ROM/flash"
1889 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1890 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1892 Say Y here if you intend to execute your compressed kernel image
1893 (zImage) directly from ROM or flash. If unsure, say N.
1895 config ARM_APPENDED_DTB
1896 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1899 With this option, the boot code will look for a device tree binary
1900 (DTB) appended to zImage
1901 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1903 This is meant as a backward compatibility convenience for those
1904 systems with a bootloader that can't be upgraded to accommodate
1905 the documented boot protocol using a device tree.
1907 Beware that there is very little in terms of protection against
1908 this option being confused by leftover garbage in memory that might
1909 look like a DTB header after a reboot if no actual DTB is appended
1910 to zImage. Do not leave this option active in a production kernel
1911 if you don't intend to always append a DTB. Proper passing of the
1912 location into r2 of a bootloader provided DTB is always preferable
1915 config ARM_ATAG_DTB_COMPAT
1916 bool "Supplement the appended DTB with traditional ATAG information"
1917 depends on ARM_APPENDED_DTB
1919 Some old bootloaders can't be updated to a DTB capable one, yet
1920 they provide ATAGs with memory configuration, the ramdisk address,
1921 the kernel cmdline string, etc. Such information is dynamically
1922 provided by the bootloader and can't always be stored in a static
1923 DTB. To allow a device tree enabled kernel to be used with such
1924 bootloaders, this option allows zImage to extract the information
1925 from the ATAG list and store it at run time into the appended DTB.
1928 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1929 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1931 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1932 bool "Use bootloader kernel arguments if available"
1934 Uses the command-line options passed by the boot loader instead of
1935 the device tree bootargs property. If the boot loader doesn't provide
1936 any, the device tree bootargs property will be used.
1938 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1939 bool "Extend with bootloader kernel arguments"
1941 The command-line arguments provided by the boot loader will be
1942 appended to the the device tree bootargs property.
1947 string "Default kernel command string"
1950 On some architectures (EBSA110 and CATS), there is currently no way
1951 for the boot loader to pass arguments to the kernel. For these
1952 architectures, you should supply some command-line options at build
1953 time by entering them here. As a minimum, you should specify the
1954 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1957 prompt "Kernel command line type" if CMDLINE != ""
1958 default CMDLINE_FROM_BOOTLOADER
1961 config CMDLINE_FROM_BOOTLOADER
1962 bool "Use bootloader kernel arguments if available"
1964 Uses the command-line options passed by the boot loader. If
1965 the boot loader doesn't provide any, the default kernel command
1966 string provided in CMDLINE will be used.
1968 config CMDLINE_EXTEND
1969 bool "Extend bootloader kernel arguments"
1971 The command-line arguments provided by the boot loader will be
1972 appended to the default kernel command string.
1974 config CMDLINE_FORCE
1975 bool "Always use the default kernel command string"
1977 Always use the default kernel command string, even if the boot
1978 loader passes other arguments to the kernel.
1979 This is useful if you cannot or don't want to change the
1980 command-line options your boot loader passes to the kernel.
1984 bool "Kernel Execute-In-Place from ROM"
1985 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1987 Execute-In-Place allows the kernel to run from non-volatile storage
1988 directly addressable by the CPU, such as NOR flash. This saves RAM
1989 space since the text section of the kernel is not loaded from flash
1990 to RAM. Read-write sections, such as the data section and stack,
1991 are still copied to RAM. The XIP kernel is not compressed since
1992 it has to run directly from flash, so it will take more space to
1993 store it. The flash address used to link the kernel object files,
1994 and for storing it, is configuration dependent. Therefore, if you
1995 say Y here, you must know the proper physical address where to
1996 store the kernel image depending on your own flash memory usage.
1998 Also note that the make target becomes "make xipImage" rather than
1999 "make zImage" or "make Image". The final kernel binary to put in
2000 ROM memory will be arch/arm/boot/xipImage.
2004 config XIP_PHYS_ADDR
2005 hex "XIP Kernel Physical Location"
2006 depends on XIP_KERNEL
2007 default "0x00080000"
2009 This is the physical address in your flash memory the kernel will
2010 be linked for and stored to. This address is dependent on your
2014 bool "Kexec system call (EXPERIMENTAL)"
2015 depends on (!SMP || PM_SLEEP_SMP)
2019 kexec is a system call that implements the ability to shutdown your
2020 current kernel, and to start another kernel. It is like a reboot
2021 but it is independent of the system firmware. And like a reboot
2022 you can start any kernel with it, not just Linux.
2024 It is an ongoing process to be certain the hardware in a machine
2025 is properly shutdown, so do not be surprised if this code does not
2026 initially work for you.
2029 bool "Export atags in procfs"
2030 depends on ATAGS && KEXEC
2033 Should the atags used to boot the kernel be exported in an "atags"
2034 file in procfs. Useful with kexec.
2037 bool "Build kdump crash kernel (EXPERIMENTAL)"
2039 Generate crash dump after being started by kexec. This should
2040 be normally only set in special crash dump kernels which are
2041 loaded in the main kernel with kexec-tools into a specially
2042 reserved region and then later executed after a crash by
2043 kdump/kexec. The crash dump kernel must be compiled to a
2044 memory address not used by the main kernel
2046 For more details see Documentation/kdump/kdump.txt
2048 config AUTO_ZRELADDR
2049 bool "Auto calculation of the decompressed kernel image address"
2051 ZRELADDR is the physical address where the decompressed kernel
2052 image will be placed. If AUTO_ZRELADDR is selected, the address
2053 will be determined at run-time by masking the current IP with
2054 0xf8000000. This assumes the zImage being placed in the first 128MB
2055 from start of memory.
2059 menu "CPU Power Management"
2061 source "drivers/cpufreq/Kconfig"
2063 source "drivers/cpuidle/Kconfig"
2067 menu "Floating point emulation"
2069 comment "At least one emulation must be selected"
2072 bool "NWFPE math emulation"
2073 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2075 Say Y to include the NWFPE floating point emulator in the kernel.
2076 This is necessary to run most binaries. Linux does not currently
2077 support floating point hardware so you need to say Y here even if
2078 your machine has an FPA or floating point co-processor podule.
2080 You may say N here if you are going to load the Acorn FPEmulator
2081 early in the bootup.
2084 bool "Support extended precision"
2085 depends on FPE_NWFPE
2087 Say Y to include 80-bit support in the kernel floating-point
2088 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2089 Note that gcc does not generate 80-bit operations by default,
2090 so in most cases this option only enlarges the size of the
2091 floating point emulator without any good reason.
2093 You almost surely want to say N here.
2096 bool "FastFPE math emulation (EXPERIMENTAL)"
2097 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2099 Say Y here to include the FAST floating point emulator in the kernel.
2100 This is an experimental much faster emulator which now also has full
2101 precision for the mantissa. It does not support any exceptions.
2102 It is very simple, and approximately 3-6 times faster than NWFPE.
2104 It should be sufficient for most programs. It may be not suitable
2105 for scientific calculations, but you have to check this for yourself.
2106 If you do not feel you need a faster FP emulation you should better
2110 bool "VFP-format floating point maths"
2111 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2113 Say Y to include VFP support code in the kernel. This is needed
2114 if your hardware includes a VFP unit.
2116 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2117 release notes and additional status information.
2119 Say N if your target does not have VFP hardware.
2127 bool "Advanced SIMD (NEON) Extension support"
2128 depends on VFPv3 && CPU_V7
2130 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2133 config KERNEL_MODE_NEON
2134 bool "Support for NEON in kernel mode"
2135 depends on NEON && AEABI
2137 Say Y to include support for NEON in kernel mode.
2141 menu "Userspace binary formats"
2143 source "fs/Kconfig.binfmt"
2147 menu "Power management options"
2149 source "kernel/power/Kconfig"
2151 config ARCH_SUSPEND_POSSIBLE
2152 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2153 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2156 config ARM_CPU_SUSPEND
2157 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2158 depends on ARCH_SUSPEND_POSSIBLE
2160 config ARCH_HIBERNATION_POSSIBLE
2163 default y if ARCH_SUSPEND_POSSIBLE
2167 source "net/Kconfig"
2169 source "drivers/Kconfig"
2171 source "drivers/firmware/Kconfig"
2175 source "arch/arm/Kconfig.debug"
2177 source "security/Kconfig"
2179 source "crypto/Kconfig"
2181 source "arch/arm/crypto/Kconfig"
2184 source "lib/Kconfig"
2186 source "arch/arm/kvm/Kconfig"