4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if (CPU_V6 || CPU_V6K || CPU_V7)
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
18 select HAVE_ARCH_TRACEHOOK
19 select HAVE_KPROBES if !XIP_KERNEL
20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
23 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
24 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
25 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
26 select HAVE_GENERIC_DMA_COHERENT
27 select HAVE_KERNEL_GZIP
28 select HAVE_KERNEL_LZO
29 select HAVE_KERNEL_LZMA
32 select HAVE_PERF_EVENTS
33 select PERF_USE_VMALLOC
34 select HAVE_REGS_AND_STACK_ACCESS_API
35 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_GENERIC_HARDIRQS
38 select HARDIRQS_SW_RESEND
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select GENERIC_IRQ_PROBE
42 select ARCH_WANT_IPC_PARSE_VERSION
43 select HARDIRQS_SW_RESEND
44 select CPU_PM if (SUSPEND || CPU_IDLE)
45 select GENERIC_PCI_IOMAP
47 select GENERIC_SMP_IDLE_THREAD
49 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
50 select GENERIC_STRNCPY_FROM_USER
51 select GENERIC_STRNLEN_USER
52 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
54 The ARM series is a line of low-power-consumption RISC chip designs
55 licensed by ARM Ltd and targeted at embedded applications and
56 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
57 manufactured, but legacy ARM-based PC hardware remains popular in
58 Europe. There is an ARM Linux project with a web page at
59 <http://www.arm.linux.org.uk/>.
61 config ARM_HAS_SG_CHAIN
64 config NEED_SG_DMA_LENGTH
67 config ARM_DMA_USE_IOMMU
68 select NEED_SG_DMA_LENGTH
69 select ARM_HAS_SG_CHAIN
78 config SYS_SUPPORTS_APM_EMULATION
86 select GENERIC_ALLOCATOR
97 The Extended Industry Standard Architecture (EISA) bus was
98 developed as an open alternative to the IBM MicroChannel bus.
100 The EISA bus provided some of the features of the IBM MicroChannel
101 bus while maintaining backward compatibility with cards made for
102 the older ISA bus. The EISA bus saw limited use between 1988 and
103 1995 when it was made obsolete by the PCI bus.
105 Say Y here if you are building a kernel for an EISA-based machine.
112 config STACKTRACE_SUPPORT
116 config HAVE_LATENCYTOP_SUPPORT
121 config LOCKDEP_SUPPORT
125 config TRACE_IRQFLAGS_SUPPORT
129 config GENERIC_LOCKBREAK
132 depends on SMP && PREEMPT
134 config RWSEM_GENERIC_SPINLOCK
138 config RWSEM_XCHGADD_ALGORITHM
141 config ARCH_HAS_ILOG2_U32
144 config ARCH_HAS_ILOG2_U64
147 config ARCH_HAS_CPUFREQ
150 Internal node to signify that the ARCH has CPUFREQ support
151 and that the relevant menu configurations are displayed for
154 config GENERIC_HWEIGHT
158 config GENERIC_CALIBRATE_DELAY
162 config ARCH_MAY_HAVE_PC_FDC
168 config NEED_DMA_MAP_STATE
171 config ARCH_HAS_DMA_SET_COHERENT_MASK
174 config GENERIC_ISA_DMA
180 config NEED_RET_TO_USER
188 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
189 default DRAM_BASE if REMAP_VECTORS_TO_RAM
192 The base address of exception vectors.
194 config ARM_PATCH_PHYS_VIRT
195 bool "Patch physical to virtual translations at runtime" if EMBEDDED
197 depends on !XIP_KERNEL && MMU
198 depends on !ARCH_REALVIEW || !SPARSEMEM
200 Patch phys-to-virt and virt-to-phys translation functions at
201 boot and module load time according to the position of the
202 kernel in system memory.
204 This can only be used with non-XIP MMU kernels where the base
205 of physical memory is at a 16MB boundary.
207 Only disable this option if you know that you do not require
208 this feature (eg, building a kernel for a single machine) and
209 you need to shrink the kernel to the minimal size.
211 config NEED_MACH_IO_H
214 Select this when mach/io.h is required to provide special
215 definitions for this platform. The need for mach/io.h should
216 be avoided when possible.
218 config NEED_MACH_MEMORY_H
221 Select this when mach/memory.h is required to provide special
222 definitions for this platform. The need for mach/memory.h should
223 be avoided when possible.
226 hex "Physical address of main memory" if MMU
227 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
228 default DRAM_BASE if !MMU
230 Please provide the physical address corresponding to the
231 location of main memory in your system.
237 source "init/Kconfig"
239 source "kernel/Kconfig.freezer"
244 bool "MMU-based Paged Memory Management Support"
247 Select if you want MMU-based virtualised addressing space
248 support by paged memory management. If unsure, say 'Y'.
251 # The "ARM system type" choice list is ordered alphabetically by option
252 # text. Please add new entries in the option alphabetic order.
255 prompt "ARM system type"
256 default ARCH_VERSATILE
259 bool "Altera SOCFPGA family"
260 select ARCH_WANT_OPTIONAL_GPIOLIB
268 select DW_APB_TIMER_OF
269 select GENERIC_CLOCKEVENTS
270 select GPIO_PL061 if GPIOLIB
275 This enables support for Altera SOCFPGA Cyclone V platform
277 config ARCH_INTEGRATOR
278 bool "ARM Ltd. Integrator family"
280 select ARCH_HAS_CPUFREQ
285 select GENERIC_CLOCKEVENTS
286 select PLAT_VERSATILE
287 select PLAT_VERSATILE_FPGA_IRQ
288 select NEED_MACH_IO_H
289 select NEED_MACH_MEMORY_H
291 select MULTI_IRQ_HANDLER
293 Support for ARM's Integrator platform.
296 bool "ARM Ltd. RealView family"
299 select HAVE_MACH_CLKDEV
301 select GENERIC_CLOCKEVENTS
302 select ARCH_WANT_OPTIONAL_GPIOLIB
303 select PLAT_VERSATILE
304 select PLAT_VERSATILE_CLOCK
305 select PLAT_VERSATILE_CLCD
306 select ARM_TIMER_SP804
307 select GPIO_PL061 if GPIOLIB
308 select NEED_MACH_MEMORY_H
310 This enables support for ARM Ltd RealView boards.
312 config ARCH_VERSATILE
313 bool "ARM Ltd. Versatile family"
317 select HAVE_MACH_CLKDEV
319 select GENERIC_CLOCKEVENTS
320 select ARCH_WANT_OPTIONAL_GPIOLIB
321 select NEED_MACH_IO_H if PCI
322 select PLAT_VERSATILE
323 select PLAT_VERSATILE_CLOCK
324 select PLAT_VERSATILE_CLCD
325 select PLAT_VERSATILE_FPGA_IRQ
326 select ARM_TIMER_SP804
328 This enables support for ARM Ltd Versatile board.
331 bool "ARM Ltd. Versatile Express family"
332 select ARCH_WANT_OPTIONAL_GPIOLIB
334 select ARM_TIMER_SP804
337 select GENERIC_CLOCKEVENTS
339 select HAVE_PATA_PLATFORM
342 select PLAT_VERSATILE
343 select PLAT_VERSATILE_CLCD
344 select REGULATOR_FIXED_VOLTAGE if REGULATOR
346 This enables support for the ARM Ltd Versatile Express boards.
350 select ARCH_REQUIRE_GPIOLIB
354 select NEED_MACH_IO_H if PCCARD
356 This enables support for systems based on Atmel
357 AT91RM9200 and AT91SAM9* processors.
360 bool "Broadcom BCMRING"
364 select ARM_TIMER_SP804
366 select GENERIC_CLOCKEVENTS
367 select ARCH_WANT_OPTIONAL_GPIOLIB
369 Support for Broadcom's BCMRing platform.
372 bool "Calxeda Highbank-based"
373 select ARCH_WANT_OPTIONAL_GPIOLIB
376 select ARM_TIMER_SP804
381 select GENERIC_CLOCKEVENTS
387 Support for the Calxeda Highbank SoC based boards.
390 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
392 select ARCH_USES_GETTIMEOFFSET
393 select NEED_MACH_MEMORY_H
395 Support for Cirrus Logic 711x/721x/731x based boards.
398 bool "Cavium Networks CNS3XXX family"
400 select GENERIC_CLOCKEVENTS
402 select MIGHT_HAVE_CACHE_L2X0
403 select MIGHT_HAVE_PCI
404 select PCI_DOMAINS if PCI
406 Support for Cavium Networks CNS3XXX platform.
409 bool "Cortina Systems Gemini"
411 select ARCH_REQUIRE_GPIOLIB
412 select ARCH_USES_GETTIMEOFFSET
414 Support for the Cortina Systems Gemini family SoCs
417 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
420 select ARCH_REQUIRE_GPIOLIB
421 select GENERIC_CLOCKEVENTS
423 select GENERIC_IRQ_CHIP
424 select MIGHT_HAVE_CACHE_L2X0
430 Support for CSR SiRFSoC ARM Cortex A9 Platform
437 select ARCH_USES_GETTIMEOFFSET
438 select NEED_MACH_IO_H
439 select NEED_MACH_MEMORY_H
441 This is an evaluation board for the StrongARM processor available
442 from Digital. It has limited hardware on-board, including an
443 Ethernet interface, two PCMCIA sockets, two serial ports and a
452 select ARCH_REQUIRE_GPIOLIB
453 select ARCH_HAS_HOLES_MEMORYMODEL
454 select ARCH_USES_GETTIMEOFFSET
455 select NEED_MACH_MEMORY_H
457 This enables support for the Cirrus EP93xx series of CPUs.
459 config ARCH_FOOTBRIDGE
463 select GENERIC_CLOCKEVENTS
465 select NEED_MACH_IO_H
466 select NEED_MACH_MEMORY_H
468 Support for systems based on the DC21285 companion chip
469 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
472 bool "Freescale MXC/iMX-based"
473 select GENERIC_CLOCKEVENTS
474 select ARCH_REQUIRE_GPIOLIB
477 select GENERIC_IRQ_CHIP
478 select MULTI_IRQ_HANDLER
482 Support for Freescale MXC/iMX-based family of processors
485 bool "Freescale MXS-based"
486 select GENERIC_CLOCKEVENTS
487 select ARCH_REQUIRE_GPIOLIB
491 select HAVE_CLK_PREPARE
492 select MULTI_IRQ_HANDLER
496 Support for Freescale MXS-based family of processors
499 bool "Hilscher NetX based"
503 select GENERIC_CLOCKEVENTS
505 This enables support for systems based on the Hilscher NetX Soc
508 bool "Hynix HMS720x-based"
511 select ARCH_USES_GETTIMEOFFSET
513 This enables support for systems based on the Hynix HMS720x
521 select ARCH_SUPPORTS_MSI
523 select NEED_MACH_IO_H
524 select NEED_MACH_MEMORY_H
525 select NEED_RET_TO_USER
527 Support for Intel's IOP13XX (XScale) family of processors.
533 select NEED_MACH_IO_H
534 select NEED_RET_TO_USER
537 select ARCH_REQUIRE_GPIOLIB
539 Support for Intel's 80219 and IOP32X (XScale) family of
546 select NEED_MACH_IO_H
547 select NEED_RET_TO_USER
550 select ARCH_REQUIRE_GPIOLIB
552 Support for Intel's IOP33X (XScale) family of processors.
557 select ARCH_HAS_DMA_SET_COHERENT_MASK
560 select ARCH_REQUIRE_GPIOLIB
561 select GENERIC_CLOCKEVENTS
562 select MIGHT_HAVE_PCI
563 select NEED_MACH_IO_H
564 select DMABOUNCE if PCI
566 Support for Intel's IXP4XX (XScale) family of processors.
569 bool "Marvell SOCs with Device Tree support"
570 select GENERIC_CLOCKEVENTS
571 select MULTI_IRQ_HANDLER
574 select GENERIC_IRQ_CHIP
578 Support for the Marvell SoC Family with device tree support
584 select ARCH_REQUIRE_GPIOLIB
585 select GENERIC_CLOCKEVENTS
586 select NEED_MACH_IO_H
589 Support for the Marvell Dove SoC 88AP510
592 bool "Marvell Kirkwood"
595 select ARCH_REQUIRE_GPIOLIB
596 select GENERIC_CLOCKEVENTS
597 select NEED_MACH_IO_H
600 Support for the following Marvell Kirkwood series SoCs:
601 88F6180, 88F6192 and 88F6281.
607 select ARCH_REQUIRE_GPIOLIB
610 select USB_ARCH_HAS_OHCI
612 select GENERIC_CLOCKEVENTS
616 Support for the NXP LPC32XX family of processors
619 bool "Marvell MV78xx0"
622 select ARCH_REQUIRE_GPIOLIB
623 select GENERIC_CLOCKEVENTS
624 select NEED_MACH_IO_H
627 Support for the following Marvell MV78xx0 series SoCs:
635 select ARCH_REQUIRE_GPIOLIB
636 select GENERIC_CLOCKEVENTS
637 select NEED_MACH_IO_H
640 Support for the following Marvell Orion 5x series SoCs:
641 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
642 Orion-2 (5281), Orion-1-90 (6183).
645 bool "Marvell PXA168/910/MMP2"
647 select ARCH_REQUIRE_GPIOLIB
649 select GENERIC_CLOCKEVENTS
654 select GENERIC_ALLOCATOR
656 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
659 bool "Micrel/Kendin KS8695"
661 select ARCH_REQUIRE_GPIOLIB
662 select ARCH_USES_GETTIMEOFFSET
663 select NEED_MACH_MEMORY_H
665 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
666 System-on-Chip devices.
669 bool "Nuvoton W90X900 CPU"
671 select ARCH_REQUIRE_GPIOLIB
674 select GENERIC_CLOCKEVENTS
676 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
677 At present, the w90x900 has been renamed nuc900, regarding
678 the ARM series product line, you can login the following
679 link address to know more.
681 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
682 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
688 select GENERIC_CLOCKEVENTS
692 select MIGHT_HAVE_CACHE_L2X0
693 select NEED_MACH_IO_H if PCI
694 select ARCH_HAS_CPUFREQ
697 This enables support for NVIDIA Tegra based systems (Tegra APX,
698 Tegra 6xx and Tegra 2 series).
700 config ARCH_PICOXCELL
701 bool "Picochip picoXcell"
702 select ARCH_REQUIRE_GPIOLIB
703 select ARM_PATCH_PHYS_VIRT
707 select DW_APB_TIMER_OF
708 select GENERIC_CLOCKEVENTS
715 This enables support for systems based on the Picochip picoXcell
716 family of Femtocell devices. The picoxcell support requires device tree
720 bool "Philips Nexperia PNX4008 Mobile"
723 select ARCH_USES_GETTIMEOFFSET
725 This enables support for Philips PNX4008 mobile platform.
728 bool "PXA2xx/PXA3xx-based"
731 select ARCH_HAS_CPUFREQ
734 select ARCH_REQUIRE_GPIOLIB
735 select GENERIC_CLOCKEVENTS
740 select MULTI_IRQ_HANDLER
741 select ARM_CPU_SUSPEND if PM
744 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
749 select GENERIC_CLOCKEVENTS
750 select ARCH_REQUIRE_GPIOLIB
753 Support for Qualcomm MSM/QSD based systems. This runs on the
754 apps processor of the MSM/QSD and depends on a shared memory
755 interface to the modem processor which runs the baseband
756 stack and controls some vital subsystems
757 (clock and power control, etc).
760 bool "Renesas SH-Mobile / R-Mobile"
763 select HAVE_MACH_CLKDEV
765 select GENERIC_CLOCKEVENTS
766 select MIGHT_HAVE_CACHE_L2X0
769 select MULTI_IRQ_HANDLER
770 select PM_GENERIC_DOMAINS if PM
771 select NEED_MACH_MEMORY_H
773 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
779 select ARCH_MAY_HAVE_PC_FDC
780 select HAVE_PATA_PLATFORM
783 select ARCH_SPARSEMEM_ENABLE
784 select ARCH_USES_GETTIMEOFFSET
786 select NEED_MACH_IO_H
787 select NEED_MACH_MEMORY_H
789 On the Acorn Risc-PC, Linux can support the internal IDE disk and
790 CD-ROM interface, serial and parallel port, and the floppy drive.
797 select ARCH_SPARSEMEM_ENABLE
799 select ARCH_HAS_CPUFREQ
801 select GENERIC_CLOCKEVENTS
803 select ARCH_REQUIRE_GPIOLIB
805 select NEED_MACH_MEMORY_H
808 Support for StrongARM 11x0 based boards.
811 bool "Samsung S3C24XX SoCs"
813 select ARCH_HAS_CPUFREQ
816 select ARCH_USES_GETTIMEOFFSET
817 select HAVE_S3C2410_I2C if I2C
818 select HAVE_S3C_RTC if RTC_CLASS
819 select HAVE_S3C2410_WATCHDOG if WATCHDOG
820 select NEED_MACH_IO_H
822 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
823 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
824 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
825 Samsung SMDK2410 development board (and derivatives).
828 bool "Samsung S3C64XX"
836 select ARCH_USES_GETTIMEOFFSET
837 select ARCH_HAS_CPUFREQ
838 select ARCH_REQUIRE_GPIOLIB
839 select SAMSUNG_CLKSRC
840 select SAMSUNG_IRQ_VIC_TIMER
841 select S3C_GPIO_TRACK
843 select USB_ARCH_HAS_OHCI
844 select SAMSUNG_GPIOLIB_4BIT
845 select HAVE_S3C2410_I2C if I2C
846 select HAVE_S3C2410_WATCHDOG if WATCHDOG
848 Samsung S3C64XX series based systems
851 bool "Samsung S5P6440 S5P6450"
857 select HAVE_S3C2410_WATCHDOG if WATCHDOG
858 select GENERIC_CLOCKEVENTS
859 select HAVE_S3C2410_I2C if I2C
860 select HAVE_S3C_RTC if RTC_CLASS
862 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
866 bool "Samsung S5PC100"
871 select ARCH_USES_GETTIMEOFFSET
872 select HAVE_S3C2410_I2C if I2C
873 select HAVE_S3C_RTC if RTC_CLASS
874 select HAVE_S3C2410_WATCHDOG if WATCHDOG
876 Samsung S5PC100 series based systems
879 bool "Samsung S5PV210/S5PC110"
881 select ARCH_SPARSEMEM_ENABLE
882 select ARCH_HAS_HOLES_MEMORYMODEL
887 select ARCH_HAS_CPUFREQ
888 select GENERIC_CLOCKEVENTS
889 select HAVE_S3C2410_I2C if I2C
890 select HAVE_S3C_RTC if RTC_CLASS
891 select HAVE_S3C2410_WATCHDOG if WATCHDOG
892 select NEED_MACH_MEMORY_H
894 Samsung S5PV210/S5PC110 series based systems
897 bool "SAMSUNG EXYNOS"
899 select ARCH_SPARSEMEM_ENABLE
900 select ARCH_HAS_HOLES_MEMORYMODEL
904 select ARCH_HAS_CPUFREQ
905 select GENERIC_CLOCKEVENTS
906 select HAVE_S3C_RTC if RTC_CLASS
907 select HAVE_S3C2410_I2C if I2C
908 select HAVE_S3C2410_WATCHDOG if WATCHDOG
909 select NEED_MACH_MEMORY_H
911 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
920 select ARCH_USES_GETTIMEOFFSET
921 select NEED_MACH_MEMORY_H
922 select NEED_MACH_IO_H
924 Support for the StrongARM based Digital DNARD machine, also known
925 as "Shark" (<http://www.shark-linux.de/shark.html>).
928 bool "ST-Ericsson U300 Series"
934 select ARM_PATCH_PHYS_VIRT
936 select GENERIC_CLOCKEVENTS
940 select ARCH_REQUIRE_GPIOLIB
942 Support for ST-Ericsson U300 series mobile platforms.
945 bool "ST-Ericsson U8500 Series"
949 select GENERIC_CLOCKEVENTS
951 select ARCH_REQUIRE_GPIOLIB
952 select ARCH_HAS_CPUFREQ
954 select MIGHT_HAVE_CACHE_L2X0
956 Support for ST-Ericsson's Ux500 architecture
959 bool "STMicroelectronics Nomadik"
964 select GENERIC_CLOCKEVENTS
966 select MIGHT_HAVE_CACHE_L2X0
967 select ARCH_REQUIRE_GPIOLIB
969 Support for the Nomadik platform by ST-Ericsson
973 select GENERIC_CLOCKEVENTS
974 select ARCH_REQUIRE_GPIOLIB
978 select GENERIC_ALLOCATOR
979 select GENERIC_IRQ_CHIP
980 select ARCH_HAS_HOLES_MEMORYMODEL
982 Support for TI's DaVinci platform.
988 select ARCH_REQUIRE_GPIOLIB
989 select ARCH_HAS_CPUFREQ
991 select GENERIC_CLOCKEVENTS
992 select ARCH_HAS_HOLES_MEMORYMODEL
994 Support for TI's OMAP platform (OMAP1/2/3/4).
999 select ARCH_REQUIRE_GPIOLIB
1000 select CLKDEV_LOOKUP
1003 select GENERIC_CLOCKEVENTS
1006 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
1009 bool "VIA/WonderMedia 85xx"
1012 select ARCH_HAS_CPUFREQ
1013 select GENERIC_CLOCKEVENTS
1014 select ARCH_REQUIRE_GPIOLIB
1016 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1019 bool "Xilinx Zynq ARM Cortex A9 Platform"
1021 select GENERIC_CLOCKEVENTS
1022 select CLKDEV_LOOKUP
1026 select MIGHT_HAVE_CACHE_L2X0
1029 Support for Xilinx Zynq ARM Cortex A9 Platform
1033 # This is sorted alphabetically by mach-* pathname. However, plat-*
1034 # Kconfigs may be included either alphabetically (according to the
1035 # plat- suffix) or along side the corresponding mach-* source.
1037 source "arch/arm/mach-mvebu/Kconfig"
1039 source "arch/arm/mach-at91/Kconfig"
1041 source "arch/arm/mach-bcmring/Kconfig"
1043 source "arch/arm/mach-clps711x/Kconfig"
1045 source "arch/arm/mach-cns3xxx/Kconfig"
1047 source "arch/arm/mach-davinci/Kconfig"
1049 source "arch/arm/mach-dove/Kconfig"
1051 source "arch/arm/mach-ep93xx/Kconfig"
1053 source "arch/arm/mach-footbridge/Kconfig"
1055 source "arch/arm/mach-gemini/Kconfig"
1057 source "arch/arm/mach-h720x/Kconfig"
1059 source "arch/arm/mach-integrator/Kconfig"
1061 source "arch/arm/mach-iop32x/Kconfig"
1063 source "arch/arm/mach-iop33x/Kconfig"
1065 source "arch/arm/mach-iop13xx/Kconfig"
1067 source "arch/arm/mach-ixp4xx/Kconfig"
1069 source "arch/arm/mach-kirkwood/Kconfig"
1071 source "arch/arm/mach-ks8695/Kconfig"
1073 source "arch/arm/mach-msm/Kconfig"
1075 source "arch/arm/mach-mv78xx0/Kconfig"
1077 source "arch/arm/plat-mxc/Kconfig"
1079 source "arch/arm/mach-mxs/Kconfig"
1081 source "arch/arm/mach-netx/Kconfig"
1083 source "arch/arm/mach-nomadik/Kconfig"
1084 source "arch/arm/plat-nomadik/Kconfig"
1086 source "arch/arm/plat-omap/Kconfig"
1088 source "arch/arm/mach-omap1/Kconfig"
1090 source "arch/arm/mach-omap2/Kconfig"
1092 source "arch/arm/mach-orion5x/Kconfig"
1094 source "arch/arm/mach-pxa/Kconfig"
1095 source "arch/arm/plat-pxa/Kconfig"
1097 source "arch/arm/mach-mmp/Kconfig"
1099 source "arch/arm/mach-realview/Kconfig"
1101 source "arch/arm/mach-sa1100/Kconfig"
1103 source "arch/arm/plat-samsung/Kconfig"
1104 source "arch/arm/plat-s3c24xx/Kconfig"
1106 source "arch/arm/plat-spear/Kconfig"
1108 source "arch/arm/mach-s3c24xx/Kconfig"
1110 source "arch/arm/mach-s3c2412/Kconfig"
1111 source "arch/arm/mach-s3c2440/Kconfig"
1115 source "arch/arm/mach-s3c64xx/Kconfig"
1118 source "arch/arm/mach-s5p64x0/Kconfig"
1120 source "arch/arm/mach-s5pc100/Kconfig"
1122 source "arch/arm/mach-s5pv210/Kconfig"
1124 source "arch/arm/mach-exynos/Kconfig"
1126 source "arch/arm/mach-shmobile/Kconfig"
1128 source "arch/arm/mach-tegra/Kconfig"
1130 source "arch/arm/mach-u300/Kconfig"
1132 source "arch/arm/mach-ux500/Kconfig"
1134 source "arch/arm/mach-versatile/Kconfig"
1136 source "arch/arm/mach-vexpress/Kconfig"
1137 source "arch/arm/plat-versatile/Kconfig"
1139 source "arch/arm/mach-vt8500/Kconfig"
1141 source "arch/arm/mach-w90x900/Kconfig"
1143 # Definitions to make life easier
1149 select GENERIC_CLOCKEVENTS
1154 select GENERIC_IRQ_CHIP
1161 config PLAT_VERSATILE
1164 config ARM_TIMER_SP804
1167 select HAVE_SCHED_CLOCK
1169 source arch/arm/mm/Kconfig
1173 default 16 if ARCH_EP93XX
1177 bool "Enable iWMMXt support"
1178 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1179 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1181 Enable support for iWMMXt context switching at run time if
1182 running on a CPU that supports it.
1186 depends on CPU_XSCALE
1190 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1191 (!ARCH_OMAP3 || OMAP3_EMU)
1195 config MULTI_IRQ_HANDLER
1198 Allow each machine to specify it's own IRQ handler at run time.
1201 source "arch/arm/Kconfig-nommu"
1204 config ARM_ERRATA_326103
1205 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1208 Executing a SWP instruction to read-only memory does not set bit 11
1209 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1210 treat the access as a read, preventing a COW from occurring and
1211 causing the faulting task to livelock.
1213 config ARM_ERRATA_411920
1214 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1215 depends on CPU_V6 || CPU_V6K
1217 Invalidation of the Instruction Cache operation can
1218 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1219 It does not affect the MPCore. This option enables the ARM Ltd.
1220 recommended workaround.
1222 config ARM_ERRATA_430973
1223 bool "ARM errata: Stale prediction on replaced interworking branch"
1226 This option enables the workaround for the 430973 Cortex-A8
1227 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1228 interworking branch is replaced with another code sequence at the
1229 same virtual address, whether due to self-modifying code or virtual
1230 to physical address re-mapping, Cortex-A8 does not recover from the
1231 stale interworking branch prediction. This results in Cortex-A8
1232 executing the new code sequence in the incorrect ARM or Thumb state.
1233 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1234 and also flushes the branch target cache at every context switch.
1235 Note that setting specific bits in the ACTLR register may not be
1236 available in non-secure mode.
1238 config ARM_ERRATA_458693
1239 bool "ARM errata: Processor deadlock when a false hazard is created"
1242 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1243 erratum. For very specific sequences of memory operations, it is
1244 possible for a hazard condition intended for a cache line to instead
1245 be incorrectly associated with a different cache line. This false
1246 hazard might then cause a processor deadlock. The workaround enables
1247 the L1 caching of the NEON accesses and disables the PLD instruction
1248 in the ACTLR register. Note that setting specific bits in the ACTLR
1249 register may not be available in non-secure mode.
1251 config ARM_ERRATA_460075
1252 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1255 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1256 erratum. Any asynchronous access to the L2 cache may encounter a
1257 situation in which recent store transactions to the L2 cache are lost
1258 and overwritten with stale memory contents from external memory. The
1259 workaround disables the write-allocate mode for the L2 cache via the
1260 ACTLR register. Note that setting specific bits in the ACTLR register
1261 may not be available in non-secure mode.
1263 config ARM_ERRATA_742230
1264 bool "ARM errata: DMB operation may be faulty"
1265 depends on CPU_V7 && SMP
1267 This option enables the workaround for the 742230 Cortex-A9
1268 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1269 between two write operations may not ensure the correct visibility
1270 ordering of the two writes. This workaround sets a specific bit in
1271 the diagnostic register of the Cortex-A9 which causes the DMB
1272 instruction to behave as a DSB, ensuring the correct behaviour of
1275 config ARM_ERRATA_742231
1276 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1277 depends on CPU_V7 && SMP
1279 This option enables the workaround for the 742231 Cortex-A9
1280 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1281 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1282 accessing some data located in the same cache line, may get corrupted
1283 data due to bad handling of the address hazard when the line gets
1284 replaced from one of the CPUs at the same time as another CPU is
1285 accessing it. This workaround sets specific bits in the diagnostic
1286 register of the Cortex-A9 which reduces the linefill issuing
1287 capabilities of the processor.
1289 config PL310_ERRATA_588369
1290 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1291 depends on CACHE_L2X0
1293 The PL310 L2 cache controller implements three types of Clean &
1294 Invalidate maintenance operations: by Physical Address
1295 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1296 They are architecturally defined to behave as the execution of a
1297 clean operation followed immediately by an invalidate operation,
1298 both performing to the same memory location. This functionality
1299 is not correctly implemented in PL310 as clean lines are not
1300 invalidated as a result of these operations.
1302 config ARM_ERRATA_720789
1303 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1306 This option enables the workaround for the 720789 Cortex-A9 (prior to
1307 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1308 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1309 As a consequence of this erratum, some TLB entries which should be
1310 invalidated are not, resulting in an incoherency in the system page
1311 tables. The workaround changes the TLB flushing routines to invalidate
1312 entries regardless of the ASID.
1314 config PL310_ERRATA_727915
1315 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1316 depends on CACHE_L2X0
1318 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1319 operation (offset 0x7FC). This operation runs in background so that
1320 PL310 can handle normal accesses while it is in progress. Under very
1321 rare circumstances, due to this erratum, write data can be lost when
1322 PL310 treats a cacheable write transaction during a Clean &
1323 Invalidate by Way operation.
1325 config ARM_ERRATA_743622
1326 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1329 This option enables the workaround for the 743622 Cortex-A9
1330 (r2p*) erratum. Under very rare conditions, a faulty
1331 optimisation in the Cortex-A9 Store Buffer may lead to data
1332 corruption. This workaround sets a specific bit in the diagnostic
1333 register of the Cortex-A9 which disables the Store Buffer
1334 optimisation, preventing the defect from occurring. This has no
1335 visible impact on the overall performance or power consumption of the
1338 config ARM_ERRATA_751472
1339 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1342 This option enables the workaround for the 751472 Cortex-A9 (prior
1343 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1344 completion of a following broadcasted operation if the second
1345 operation is received by a CPU before the ICIALLUIS has completed,
1346 potentially leading to corrupted entries in the cache or TLB.
1348 config PL310_ERRATA_753970
1349 bool "PL310 errata: cache sync operation may be faulty"
1350 depends on CACHE_PL310
1352 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1354 Under some condition the effect of cache sync operation on
1355 the store buffer still remains when the operation completes.
1356 This means that the store buffer is always asked to drain and
1357 this prevents it from merging any further writes. The workaround
1358 is to replace the normal offset of cache sync operation (0x730)
1359 by another offset targeting an unmapped PL310 register 0x740.
1360 This has the same effect as the cache sync operation: store buffer
1361 drain and waiting for all buffers empty.
1363 config ARM_ERRATA_754322
1364 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1367 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1368 r3p*) erratum. A speculative memory access may cause a page table walk
1369 which starts prior to an ASID switch but completes afterwards. This
1370 can populate the micro-TLB with a stale entry which may be hit with
1371 the new ASID. This workaround places two dsb instructions in the mm
1372 switching code so that no page table walks can cross the ASID switch.
1374 config ARM_ERRATA_754327
1375 bool "ARM errata: no automatic Store Buffer drain"
1376 depends on CPU_V7 && SMP
1378 This option enables the workaround for the 754327 Cortex-A9 (prior to
1379 r2p0) erratum. The Store Buffer does not have any automatic draining
1380 mechanism and therefore a livelock may occur if an external agent
1381 continuously polls a memory location waiting to observe an update.
1382 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1383 written polling loops from denying visibility of updates to memory.
1385 config ARM_ERRATA_364296
1386 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1387 depends on CPU_V6 && !SMP
1389 This options enables the workaround for the 364296 ARM1136
1390 r0p2 erratum (possible cache data corruption with
1391 hit-under-miss enabled). It sets the undocumented bit 31 in
1392 the auxiliary control register and the FI bit in the control
1393 register, thus disabling hit-under-miss without putting the
1394 processor into full low interrupt latency mode. ARM11MPCore
1397 config ARM_ERRATA_764369
1398 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1399 depends on CPU_V7 && SMP
1401 This option enables the workaround for erratum 764369
1402 affecting Cortex-A9 MPCore with two or more processors (all
1403 current revisions). Under certain timing circumstances, a data
1404 cache line maintenance operation by MVA targeting an Inner
1405 Shareable memory region may fail to proceed up to either the
1406 Point of Coherency or to the Point of Unification of the
1407 system. This workaround adds a DSB instruction before the
1408 relevant cache maintenance functions and sets a specific bit
1409 in the diagnostic control register of the SCU.
1411 config PL310_ERRATA_769419
1412 bool "PL310 errata: no automatic Store Buffer drain"
1413 depends on CACHE_L2X0
1415 On revisions of the PL310 prior to r3p2, the Store Buffer does
1416 not automatically drain. This can cause normal, non-cacheable
1417 writes to be retained when the memory system is idle, leading
1418 to suboptimal I/O performance for drivers using coherent DMA.
1419 This option adds a write barrier to the cpu_idle loop so that,
1420 on systems with an outer cache, the store buffer is drained
1425 source "arch/arm/common/Kconfig"
1435 Find out whether you have ISA slots on your motherboard. ISA is the
1436 name of a bus system, i.e. the way the CPU talks to the other stuff
1437 inside your box. Other bus systems are PCI, EISA, MicroChannel
1438 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1439 newer boards don't support it. If you have ISA, say Y, otherwise N.
1441 # Select ISA DMA controller support
1446 # Select ISA DMA interface
1451 bool "PCI support" if MIGHT_HAVE_PCI
1453 Find out whether you have a PCI motherboard. PCI is the name of a
1454 bus system, i.e. the way the CPU talks to the other stuff inside
1455 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1456 VESA. If you have PCI, say Y, otherwise N.
1462 config PCI_NANOENGINE
1463 bool "BSE nanoEngine PCI support"
1464 depends on SA1100_NANOENGINE
1466 Enable PCI on the BSE nanoEngine board.
1471 # Select the host bridge type
1472 config PCI_HOST_VIA82C505
1474 depends on PCI && ARCH_SHARK
1477 config PCI_HOST_ITE8152
1479 depends on PCI && MACH_ARMCORE
1483 source "drivers/pci/Kconfig"
1485 source "drivers/pcmcia/Kconfig"
1489 menu "Kernel Features"
1494 This option should be selected by machines which have an SMP-
1497 The only effect of this option is to make the SMP-related
1498 options available to the user for configuration.
1501 bool "Symmetric Multi-Processing"
1502 depends on CPU_V6K || CPU_V7
1503 depends on GENERIC_CLOCKEVENTS
1506 select USE_GENERIC_SMP_HELPERS
1507 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1509 This enables support for systems with more than one CPU. If you have
1510 a system with only one CPU, like most personal computers, say N. If
1511 you have a system with more than one CPU, say Y.
1513 If you say N here, the kernel will run on single and multiprocessor
1514 machines, but will use only one CPU of a multiprocessor machine. If
1515 you say Y here, the kernel will run on many, but not all, single
1516 processor machines. On a single processor machine, the kernel will
1517 run faster if you say N here.
1519 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1520 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1521 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1523 If you don't know what to do here, say N.
1526 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1527 depends on EXPERIMENTAL
1528 depends on SMP && !XIP_KERNEL
1531 SMP kernels contain instructions which fail on non-SMP processors.
1532 Enabling this option allows the kernel to modify itself to make
1533 these instructions safe. Disabling it allows about 1K of space
1536 If you don't know what to do here, say Y.
1538 config ARM_CPU_TOPOLOGY
1539 bool "Support cpu topology definition"
1540 depends on SMP && CPU_V7
1543 Support ARM cpu topology definition. The MPIDR register defines
1544 affinity between processors which is then used to describe the cpu
1545 topology of an ARM System.
1548 bool "Multi-core scheduler support"
1549 depends on ARM_CPU_TOPOLOGY
1551 Multi-core scheduler support improves the CPU scheduler's decision
1552 making when dealing with multi-core CPU chips at a cost of slightly
1553 increased overhead in some places. If unsure say N here.
1556 bool "SMT scheduler support"
1557 depends on ARM_CPU_TOPOLOGY
1559 Improves the CPU scheduler's decision making when dealing with
1560 MultiThreading at a cost of slightly increased overhead in some
1561 places. If unsure say N here.
1566 This option enables support for the ARM system coherency unit
1568 config ARM_ARCH_TIMER
1569 bool "Architected timer support"
1572 This option enables support for the ARM architected timer
1578 This options enables support for the ARM timer and watchdog unit
1581 prompt "Memory split"
1584 Select the desired split between kernel and user memory.
1586 If you are not absolutely sure what you are doing, leave this
1590 bool "3G/1G user/kernel split"
1592 bool "2G/2G user/kernel split"
1594 bool "1G/3G user/kernel split"
1599 default 0x40000000 if VMSPLIT_1G
1600 default 0x80000000 if VMSPLIT_2G
1604 int "Maximum number of CPUs (2-32)"
1610 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1611 depends on SMP && HOTPLUG && EXPERIMENTAL
1613 Say Y here to experiment with turning CPUs off and on. CPUs
1614 can be controlled through /sys/devices/system/cpu.
1617 bool "Use local timer interrupts"
1620 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1622 Enable support for local timers on SMP platforms, rather then the
1623 legacy IPI broadcast method. Local timers allows the system
1624 accounting to be spread across the timer interval, preventing a
1625 "thundering herd" at every timer tick.
1629 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1630 default 355 if ARCH_U8500
1631 default 264 if MACH_H4700
1632 default 512 if SOC_OMAP5
1635 Maximum number of GPIOs in the system.
1637 If unsure, leave the default value.
1639 source kernel/Kconfig.preempt
1643 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1644 ARCH_S5PV210 || ARCH_EXYNOS4
1645 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1646 default AT91_TIMER_HZ if ARCH_AT91
1647 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1650 config THUMB2_KERNEL
1651 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1652 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1654 select ARM_ASM_UNIFIED
1657 By enabling this option, the kernel will be compiled in
1658 Thumb-2 mode. A compiler/assembler that understand the unified
1659 ARM-Thumb syntax is needed.
1663 config THUMB2_AVOID_R_ARM_THM_JUMP11
1664 bool "Work around buggy Thumb-2 short branch relocations in gas"
1665 depends on THUMB2_KERNEL && MODULES
1668 Various binutils versions can resolve Thumb-2 branches to
1669 locally-defined, preemptible global symbols as short-range "b.n"
1670 branch instructions.
1672 This is a problem, because there's no guarantee the final
1673 destination of the symbol, or any candidate locations for a
1674 trampoline, are within range of the branch. For this reason, the
1675 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1676 relocation in modules at all, and it makes little sense to add
1679 The symptom is that the kernel fails with an "unsupported
1680 relocation" error when loading some modules.
1682 Until fixed tools are available, passing
1683 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1684 code which hits this problem, at the cost of a bit of extra runtime
1685 stack usage in some cases.
1687 The problem is described in more detail at:
1688 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1690 Only Thumb-2 kernels are affected.
1692 Unless you are sure your tools don't have this problem, say Y.
1694 config ARM_ASM_UNIFIED
1698 bool "Use the ARM EABI to compile the kernel"
1700 This option allows for the kernel to be compiled using the latest
1701 ARM ABI (aka EABI). This is only useful if you are using a user
1702 space environment that is also compiled with EABI.
1704 Since there are major incompatibilities between the legacy ABI and
1705 EABI, especially with regard to structure member alignment, this
1706 option also changes the kernel syscall calling convention to
1707 disambiguate both ABIs and allow for backward compatibility support
1708 (selected with CONFIG_OABI_COMPAT).
1710 To use this you need GCC version 4.0.0 or later.
1713 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1714 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1717 This option preserves the old syscall interface along with the
1718 new (ARM EABI) one. It also provides a compatibility layer to
1719 intercept syscalls that have structure arguments which layout
1720 in memory differs between the legacy ABI and the new ARM EABI
1721 (only for non "thumb" binaries). This option adds a tiny
1722 overhead to all syscalls and produces a slightly larger kernel.
1723 If you know you'll be using only pure EABI user space then you
1724 can say N here. If this option is not selected and you attempt
1725 to execute a legacy ABI binary then the result will be
1726 UNPREDICTABLE (in fact it can be predicted that it won't work
1727 at all). If in doubt say Y.
1729 config ARCH_HAS_HOLES_MEMORYMODEL
1732 config ARCH_SPARSEMEM_ENABLE
1735 config ARCH_SPARSEMEM_DEFAULT
1736 def_bool ARCH_SPARSEMEM_ENABLE
1738 config ARCH_SELECT_MEMORY_MODEL
1739 def_bool ARCH_SPARSEMEM_ENABLE
1741 config HAVE_ARCH_PFN_VALID
1742 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1745 bool "High Memory Support"
1748 The address space of ARM processors is only 4 Gigabytes large
1749 and it has to accommodate user address space, kernel address
1750 space as well as some memory mapped IO. That means that, if you
1751 have a large amount of physical memory and/or IO, not all of the
1752 memory can be "permanently mapped" by the kernel. The physical
1753 memory that is not permanently mapped is called "high memory".
1755 Depending on the selected kernel/user memory split, minimum
1756 vmalloc space and actual amount of RAM, you may not need this
1757 option which should result in a slightly faster kernel.
1762 bool "Allocate 2nd-level pagetables from highmem"
1765 config HW_PERF_EVENTS
1766 bool "Enable hardware performance counter support for perf events"
1767 depends on PERF_EVENTS && CPU_HAS_PMU
1770 Enable hardware performance counter support for perf events. If
1771 disabled, perf events will use software events only.
1775 config FORCE_MAX_ZONEORDER
1776 int "Maximum zone order" if ARCH_SHMOBILE
1777 range 11 64 if ARCH_SHMOBILE
1778 default "9" if SA1111
1781 The kernel memory allocator divides physically contiguous memory
1782 blocks into "zones", where each zone is a power of two number of
1783 pages. This option selects the largest power of two that the kernel
1784 keeps in the memory allocator. If you need to allocate very large
1785 blocks of physically contiguous memory, then you may need to
1786 increase this value.
1788 This config option is actually maximum order plus one. For example,
1789 a value of 11 means that the largest free memory block is 2^10 pages.
1792 bool "Timer and CPU usage LEDs"
1793 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1794 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1795 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1796 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1797 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1798 ARCH_AT91 || ARCH_DAVINCI || \
1799 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1801 If you say Y here, the LEDs on your machine will be used
1802 to provide useful information about your current system status.
1804 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1805 be able to select which LEDs are active using the options below. If
1806 you are compiling a kernel for the EBSA-110 or the LART however, the
1807 red LED will simply flash regularly to indicate that the system is
1808 still functional. It is safe to say Y here if you have a CATS
1809 system, but the driver will do nothing.
1812 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1813 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1814 || MACH_OMAP_PERSEUS2
1816 depends on !GENERIC_CLOCKEVENTS
1817 default y if ARCH_EBSA110
1819 If you say Y here, one of the system LEDs (the green one on the
1820 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1821 will flash regularly to indicate that the system is still
1822 operational. This is mainly useful to kernel hackers who are
1823 debugging unstable kernels.
1825 The LART uses the same LED for both Timer LED and CPU usage LED
1826 functions. You may choose to use both, but the Timer LED function
1827 will overrule the CPU usage LED.
1830 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1832 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1833 || MACH_OMAP_PERSEUS2
1836 If you say Y here, the red LED will be used to give a good real
1837 time indication of CPU usage, by lighting whenever the idle task
1838 is not currently executing.
1840 The LART uses the same LED for both Timer LED and CPU usage LED
1841 functions. You may choose to use both, but the Timer LED function
1842 will overrule the CPU usage LED.
1844 config ALIGNMENT_TRAP
1846 depends on CPU_CP15_MMU
1847 default y if !ARCH_EBSA110
1848 select HAVE_PROC_CPU if PROC_FS
1850 ARM processors cannot fetch/store information which is not
1851 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1852 address divisible by 4. On 32-bit ARM processors, these non-aligned
1853 fetch/store instructions will be emulated in software if you say
1854 here, which has a severe performance impact. This is necessary for
1855 correct operation of some network protocols. With an IP-only
1856 configuration it is safe to say N, otherwise say Y.
1858 config UACCESS_WITH_MEMCPY
1859 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1860 depends on MMU && EXPERIMENTAL
1861 default y if CPU_FEROCEON
1863 Implement faster copy_to_user and clear_user methods for CPU
1864 cores where a 8-word STM instruction give significantly higher
1865 memory write throughput than a sequence of individual 32bit stores.
1867 A possible side effect is a slight increase in scheduling latency
1868 between threads sharing the same address space if they invoke
1869 such copy operations with large buffers.
1871 However, if the CPU data cache is using a write-allocate mode,
1872 this option is unlikely to provide any performance gain.
1876 prompt "Enable seccomp to safely compute untrusted bytecode"
1878 This kernel feature is useful for number crunching applications
1879 that may need to compute untrusted bytecode during their
1880 execution. By using pipes or other transports made available to
1881 the process as file descriptors supporting the read/write
1882 syscalls, it's possible to isolate those applications in
1883 their own address space using seccomp. Once seccomp is
1884 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1885 and the task is only allowed to execute a few safe syscalls
1886 defined by each seccomp mode.
1888 config CC_STACKPROTECTOR
1889 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1890 depends on EXPERIMENTAL
1892 This option turns on the -fstack-protector GCC feature. This
1893 feature puts, at the beginning of functions, a canary value on
1894 the stack just before the return address, and validates
1895 the value just before actually returning. Stack based buffer
1896 overflows (that need to overwrite this return address) now also
1897 overwrite the canary, which gets detected and the attack is then
1898 neutralized via a kernel panic.
1899 This feature requires gcc version 4.2 or above.
1901 config DEPRECATED_PARAM_STRUCT
1902 bool "Provide old way to pass kernel parameters"
1904 This was deprecated in 2001 and announced to live on for 5 years.
1905 Some old boot loaders still use this way.
1912 bool "Flattened Device Tree support"
1914 select OF_EARLY_FLATTREE
1917 Include support for flattened device tree machine descriptions.
1919 # Compressed boot loader in ROM. Yes, we really want to ask about
1920 # TEXT and BSS so we preserve their values in the config files.
1921 config ZBOOT_ROM_TEXT
1922 hex "Compressed ROM boot loader base address"
1925 The physical address at which the ROM-able zImage is to be
1926 placed in the target. Platforms which normally make use of
1927 ROM-able zImage formats normally set this to a suitable
1928 value in their defconfig file.
1930 If ZBOOT_ROM is not enabled, this has no effect.
1932 config ZBOOT_ROM_BSS
1933 hex "Compressed ROM boot loader BSS address"
1936 The base address of an area of read/write memory in the target
1937 for the ROM-able zImage which must be available while the
1938 decompressor is running. It must be large enough to hold the
1939 entire decompressed kernel plus an additional 128 KiB.
1940 Platforms which normally make use of ROM-able zImage formats
1941 normally set this to a suitable value in their defconfig file.
1943 If ZBOOT_ROM is not enabled, this has no effect.
1946 bool "Compressed boot loader in ROM/flash"
1947 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1949 Say Y here if you intend to execute your compressed kernel image
1950 (zImage) directly from ROM or flash. If unsure, say N.
1953 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1954 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1955 default ZBOOT_ROM_NONE
1957 Include experimental SD/MMC loading code in the ROM-able zImage.
1958 With this enabled it is possible to write the ROM-able zImage
1959 kernel image to an MMC or SD card and boot the kernel straight
1960 from the reset vector. At reset the processor Mask ROM will load
1961 the first part of the ROM-able zImage which in turn loads the
1962 rest the kernel image to RAM.
1964 config ZBOOT_ROM_NONE
1965 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1967 Do not load image from SD or MMC
1969 config ZBOOT_ROM_MMCIF
1970 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1972 Load image from MMCIF hardware block.
1974 config ZBOOT_ROM_SH_MOBILE_SDHI
1975 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1977 Load image from SDHI hardware block
1981 config ARM_APPENDED_DTB
1982 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1983 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1985 With this option, the boot code will look for a device tree binary
1986 (DTB) appended to zImage
1987 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1989 This is meant as a backward compatibility convenience for those
1990 systems with a bootloader that can't be upgraded to accommodate
1991 the documented boot protocol using a device tree.
1993 Beware that there is very little in terms of protection against
1994 this option being confused by leftover garbage in memory that might
1995 look like a DTB header after a reboot if no actual DTB is appended
1996 to zImage. Do not leave this option active in a production kernel
1997 if you don't intend to always append a DTB. Proper passing of the
1998 location into r2 of a bootloader provided DTB is always preferable
2001 config ARM_ATAG_DTB_COMPAT
2002 bool "Supplement the appended DTB with traditional ATAG information"
2003 depends on ARM_APPENDED_DTB
2005 Some old bootloaders can't be updated to a DTB capable one, yet
2006 they provide ATAGs with memory configuration, the ramdisk address,
2007 the kernel cmdline string, etc. Such information is dynamically
2008 provided by the bootloader and can't always be stored in a static
2009 DTB. To allow a device tree enabled kernel to be used with such
2010 bootloaders, this option allows zImage to extract the information
2011 from the ATAG list and store it at run time into the appended DTB.
2014 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2015 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2017 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2018 bool "Use bootloader kernel arguments if available"
2020 Uses the command-line options passed by the boot loader instead of
2021 the device tree bootargs property. If the boot loader doesn't provide
2022 any, the device tree bootargs property will be used.
2024 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2025 bool "Extend with bootloader kernel arguments"
2027 The command-line arguments provided by the boot loader will be
2028 appended to the the device tree bootargs property.
2033 string "Default kernel command string"
2036 On some architectures (EBSA110 and CATS), there is currently no way
2037 for the boot loader to pass arguments to the kernel. For these
2038 architectures, you should supply some command-line options at build
2039 time by entering them here. As a minimum, you should specify the
2040 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2043 prompt "Kernel command line type" if CMDLINE != ""
2044 default CMDLINE_FROM_BOOTLOADER
2046 config CMDLINE_FROM_BOOTLOADER
2047 bool "Use bootloader kernel arguments if available"
2049 Uses the command-line options passed by the boot loader. If
2050 the boot loader doesn't provide any, the default kernel command
2051 string provided in CMDLINE will be used.
2053 config CMDLINE_EXTEND
2054 bool "Extend bootloader kernel arguments"
2056 The command-line arguments provided by the boot loader will be
2057 appended to the default kernel command string.
2059 config CMDLINE_FORCE
2060 bool "Always use the default kernel command string"
2062 Always use the default kernel command string, even if the boot
2063 loader passes other arguments to the kernel.
2064 This is useful if you cannot or don't want to change the
2065 command-line options your boot loader passes to the kernel.
2069 bool "Kernel Execute-In-Place from ROM"
2070 depends on !ZBOOT_ROM && !ARM_LPAE
2072 Execute-In-Place allows the kernel to run from non-volatile storage
2073 directly addressable by the CPU, such as NOR flash. This saves RAM
2074 space since the text section of the kernel is not loaded from flash
2075 to RAM. Read-write sections, such as the data section and stack,
2076 are still copied to RAM. The XIP kernel is not compressed since
2077 it has to run directly from flash, so it will take more space to
2078 store it. The flash address used to link the kernel object files,
2079 and for storing it, is configuration dependent. Therefore, if you
2080 say Y here, you must know the proper physical address where to
2081 store the kernel image depending on your own flash memory usage.
2083 Also note that the make target becomes "make xipImage" rather than
2084 "make zImage" or "make Image". The final kernel binary to put in
2085 ROM memory will be arch/arm/boot/xipImage.
2089 config XIP_PHYS_ADDR
2090 hex "XIP Kernel Physical Location"
2091 depends on XIP_KERNEL
2092 default "0x00080000"
2094 This is the physical address in your flash memory the kernel will
2095 be linked for and stored to. This address is dependent on your
2099 bool "Kexec system call (EXPERIMENTAL)"
2100 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2102 kexec is a system call that implements the ability to shutdown your
2103 current kernel, and to start another kernel. It is like a reboot
2104 but it is independent of the system firmware. And like a reboot
2105 you can start any kernel with it, not just Linux.
2107 It is an ongoing process to be certain the hardware in a machine
2108 is properly shutdown, so do not be surprised if this code does not
2109 initially work for you. It may help to enable device hotplugging
2113 bool "Export atags in procfs"
2117 Should the atags used to boot the kernel be exported in an "atags"
2118 file in procfs. Useful with kexec.
2121 bool "Build kdump crash kernel (EXPERIMENTAL)"
2122 depends on EXPERIMENTAL
2124 Generate crash dump after being started by kexec. This should
2125 be normally only set in special crash dump kernels which are
2126 loaded in the main kernel with kexec-tools into a specially
2127 reserved region and then later executed after a crash by
2128 kdump/kexec. The crash dump kernel must be compiled to a
2129 memory address not used by the main kernel
2131 For more details see Documentation/kdump/kdump.txt
2133 config AUTO_ZRELADDR
2134 bool "Auto calculation of the decompressed kernel image address"
2135 depends on !ZBOOT_ROM && !ARCH_U300
2137 ZRELADDR is the physical address where the decompressed kernel
2138 image will be placed. If AUTO_ZRELADDR is selected, the address
2139 will be determined at run-time by masking the current IP with
2140 0xf8000000. This assumes the zImage being placed in the first 128MB
2141 from start of memory.
2145 menu "CPU Power Management"
2149 source "drivers/cpufreq/Kconfig"
2152 tristate "CPUfreq driver for i.MX CPUs"
2153 depends on ARCH_MXC && CPU_FREQ
2155 This enables the CPUfreq driver for i.MX CPUs.
2157 config CPU_FREQ_SA1100
2160 config CPU_FREQ_SA1110
2163 config CPU_FREQ_INTEGRATOR
2164 tristate "CPUfreq driver for ARM Integrator CPUs"
2165 depends on ARCH_INTEGRATOR && CPU_FREQ
2168 This enables the CPUfreq driver for ARM Integrator CPUs.
2170 For details, take a look at <file:Documentation/cpu-freq>.
2176 depends on CPU_FREQ && ARCH_PXA && PXA25x
2178 select CPU_FREQ_TABLE
2179 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2184 Internal configuration node for common cpufreq on Samsung SoC
2186 config CPU_FREQ_S3C24XX
2187 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2188 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2191 This enables the CPUfreq driver for the Samsung S3C24XX family
2194 For details, take a look at <file:Documentation/cpu-freq>.
2198 config CPU_FREQ_S3C24XX_PLL
2199 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2200 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2202 Compile in support for changing the PLL frequency from the
2203 S3C24XX series CPUfreq driver. The PLL takes time to settle
2204 after a frequency change, so by default it is not enabled.
2206 This also means that the PLL tables for the selected CPU(s) will
2207 be built which may increase the size of the kernel image.
2209 config CPU_FREQ_S3C24XX_DEBUG
2210 bool "Debug CPUfreq Samsung driver core"
2211 depends on CPU_FREQ_S3C24XX
2213 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2215 config CPU_FREQ_S3C24XX_IODEBUG
2216 bool "Debug CPUfreq Samsung driver IO timing"
2217 depends on CPU_FREQ_S3C24XX
2219 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2221 config CPU_FREQ_S3C24XX_DEBUGFS
2222 bool "Export debugfs for CPUFreq"
2223 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2225 Export status information via debugfs.
2229 source "drivers/cpuidle/Kconfig"
2233 menu "Floating point emulation"
2235 comment "At least one emulation must be selected"
2238 bool "NWFPE math emulation"
2239 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2241 Say Y to include the NWFPE floating point emulator in the kernel.
2242 This is necessary to run most binaries. Linux does not currently
2243 support floating point hardware so you need to say Y here even if
2244 your machine has an FPA or floating point co-processor podule.
2246 You may say N here if you are going to load the Acorn FPEmulator
2247 early in the bootup.
2250 bool "Support extended precision"
2251 depends on FPE_NWFPE
2253 Say Y to include 80-bit support in the kernel floating-point
2254 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2255 Note that gcc does not generate 80-bit operations by default,
2256 so in most cases this option only enlarges the size of the
2257 floating point emulator without any good reason.
2259 You almost surely want to say N here.
2262 bool "FastFPE math emulation (EXPERIMENTAL)"
2263 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2265 Say Y here to include the FAST floating point emulator in the kernel.
2266 This is an experimental much faster emulator which now also has full
2267 precision for the mantissa. It does not support any exceptions.
2268 It is very simple, and approximately 3-6 times faster than NWFPE.
2270 It should be sufficient for most programs. It may be not suitable
2271 for scientific calculations, but you have to check this for yourself.
2272 If you do not feel you need a faster FP emulation you should better
2276 bool "VFP-format floating point maths"
2277 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2279 Say Y to include VFP support code in the kernel. This is needed
2280 if your hardware includes a VFP unit.
2282 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2283 release notes and additional status information.
2285 Say N if your target does not have VFP hardware.
2293 bool "Advanced SIMD (NEON) Extension support"
2294 depends on VFPv3 && CPU_V7
2296 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2301 menu "Userspace binary formats"
2303 source "fs/Kconfig.binfmt"
2306 tristate "RISC OS personality"
2309 Say Y here to include the kernel code necessary if you want to run
2310 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2311 experimental; if this sounds frightening, say N and sleep in peace.
2312 You can also say M here to compile this support as a module (which
2313 will be called arthur).
2317 menu "Power management options"
2319 source "kernel/power/Kconfig"
2321 config ARCH_SUSPEND_POSSIBLE
2322 depends on !ARCH_S5PC100 && !ARCH_TEGRA
2323 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2324 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2327 config ARM_CPU_SUSPEND
2332 source "net/Kconfig"
2334 source "drivers/Kconfig"
2338 source "arch/arm/Kconfig.debug"
2340 source "security/Kconfig"
2342 source "crypto/Kconfig"
2344 source "lib/Kconfig"