4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_STRNCPY_FROM_USER
20 select GENERIC_STRNLEN_USER
21 select HARDIRQS_SW_RESEND
23 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
25 select HAVE_ARCH_SECCOMP_FILTER
26 select HAVE_ARCH_TRACEHOOK
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_DEBUG_KMEMLEAK
30 select HAVE_DMA_API_DEBUG
32 select HAVE_DMA_CONTIGUOUS if MMU
33 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
34 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
35 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
36 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
37 select HAVE_GENERIC_DMA_COHERENT
38 select HAVE_GENERIC_HARDIRQS
39 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
40 select HAVE_IDE if PCI || ISA || PCMCIA
41 select HAVE_KERNEL_GZIP
42 select HAVE_KERNEL_LZMA
43 select HAVE_KERNEL_LZO
45 select HAVE_KPROBES if !XIP_KERNEL
46 select HAVE_KRETPROBES if (HAVE_KPROBES)
48 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
49 select HAVE_PERF_EVENTS
50 select HAVE_REGS_AND_STACK_ACCESS_API
51 select HAVE_SYSCALL_TRACEPOINTS
54 select PERF_USE_VMALLOC
56 select SYS_SUPPORTS_APM_EMULATION
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select MODULES_USE_ELF_REL
59 select CLONE_BACKWARDS
60 select OLD_SIGSUSPEND3
63 The ARM series is a line of low-power-consumption RISC chip designs
64 licensed by ARM Ltd and targeted at embedded applications and
65 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
66 manufactured, but legacy ARM-based PC hardware remains popular in
67 Europe. There is an ARM Linux project with a web page at
68 <http://www.arm.linux.org.uk/>.
70 config ARM_HAS_SG_CHAIN
73 config NEED_SG_DMA_LENGTH
76 config ARM_DMA_USE_IOMMU
78 select ARM_HAS_SG_CHAIN
79 select NEED_SG_DMA_LENGTH
83 config ARM_DMA_IOMMU_ALIGNMENT
84 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
88 DMA mapping framework by default aligns all buffers to the smallest
89 PAGE_SIZE order which is greater than or equal to the requested buffer
90 size. This works well for buffers up to a few hundreds kilobytes, but
91 for larger buffers it just a waste of address space. Drivers which has
92 relatively small addressing window (like 64Mib) might run out of
93 virtual space with just a few allocations.
95 With this parameter you can specify the maximum PAGE_SIZE order for
96 DMA IOMMU buffers. Larger buffers will be aligned only to this
97 specified order. The order is expressed as a power of two multiplied
105 config MIGHT_HAVE_PCI
108 config SYS_SUPPORTS_APM_EMULATION
116 select GENERIC_ALLOCATOR
127 The Extended Industry Standard Architecture (EISA) bus was
128 developed as an open alternative to the IBM MicroChannel bus.
130 The EISA bus provided some of the features of the IBM MicroChannel
131 bus while maintaining backward compatibility with cards made for
132 the older ISA bus. The EISA bus saw limited use between 1988 and
133 1995 when it was made obsolete by the PCI bus.
135 Say Y here if you are building a kernel for an EISA-based machine.
142 config STACKTRACE_SUPPORT
146 config HAVE_LATENCYTOP_SUPPORT
151 config LOCKDEP_SUPPORT
155 config TRACE_IRQFLAGS_SUPPORT
159 config RWSEM_GENERIC_SPINLOCK
163 config RWSEM_XCHGADD_ALGORITHM
166 config ARCH_HAS_ILOG2_U32
169 config ARCH_HAS_ILOG2_U64
172 config ARCH_HAS_CPUFREQ
175 Internal node to signify that the ARCH has CPUFREQ support
176 and that the relevant menu configurations are displayed for
179 config GENERIC_HWEIGHT
183 config GENERIC_CALIBRATE_DELAY
187 config ARCH_MAY_HAVE_PC_FDC
193 config NEED_DMA_MAP_STATE
196 config ARCH_HAS_DMA_SET_COHERENT_MASK
199 config GENERIC_ISA_DMA
205 config NEED_RET_TO_USER
213 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
214 default DRAM_BASE if REMAP_VECTORS_TO_RAM
217 The base address of exception vectors.
219 config ARM_PATCH_PHYS_VIRT
220 bool "Patch physical to virtual translations at runtime" if EMBEDDED
222 depends on !XIP_KERNEL && MMU
223 depends on !ARCH_REALVIEW || !SPARSEMEM
225 Patch phys-to-virt and virt-to-phys translation functions at
226 boot and module load time according to the position of the
227 kernel in system memory.
229 This can only be used with non-XIP MMU kernels where the base
230 of physical memory is at a 16MB boundary.
232 Only disable this option if you know that you do not require
233 this feature (eg, building a kernel for a single machine) and
234 you need to shrink the kernel to the minimal size.
236 config NEED_MACH_GPIO_H
239 Select this when mach/gpio.h is required to provide special
240 definitions for this platform. The need for mach/gpio.h should
241 be avoided when possible.
243 config NEED_MACH_IO_H
246 Select this when mach/io.h is required to provide special
247 definitions for this platform. The need for mach/io.h should
248 be avoided when possible.
250 config NEED_MACH_MEMORY_H
253 Select this when mach/memory.h is required to provide special
254 definitions for this platform. The need for mach/memory.h should
255 be avoided when possible.
258 hex "Physical address of main memory" if MMU
259 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
260 default DRAM_BASE if !MMU
262 Please provide the physical address corresponding to the
263 location of main memory in your system.
269 source "init/Kconfig"
271 source "kernel/Kconfig.freezer"
276 bool "MMU-based Paged Memory Management Support"
279 Select if you want MMU-based virtualised addressing space
280 support by paged memory management. If unsure, say 'Y'.
283 # The "ARM system type" choice list is ordered alphabetically by option
284 # text. Please add new entries in the option alphabetic order.
287 prompt "ARM system type"
288 default ARCH_VERSATILE if !MMU
289 default ARCH_MULTIPLATFORM if MMU
291 config ARCH_MULTIPLATFORM
292 bool "Allow multiple platforms to be selected"
294 select ARM_PATCH_PHYS_VIRT
297 select MULTI_IRQ_HANDLER
301 config ARCH_INTEGRATOR
302 bool "ARM Ltd. Integrator family"
303 select ARCH_HAS_CPUFREQ
306 select COMMON_CLK_VERSATILE
307 select GENERIC_CLOCKEVENTS
310 select MULTI_IRQ_HANDLER
311 select NEED_MACH_MEMORY_H
312 select PLAT_VERSATILE
314 select VERSATILE_FPGA_IRQ
316 Support for ARM's Integrator platform.
319 bool "ARM Ltd. RealView family"
320 select ARCH_WANT_OPTIONAL_GPIOLIB
322 select ARM_TIMER_SP804
324 select COMMON_CLK_VERSATILE
325 select GENERIC_CLOCKEVENTS
326 select GPIO_PL061 if GPIOLIB
328 select NEED_MACH_MEMORY_H
329 select PLAT_VERSATILE
330 select PLAT_VERSATILE_CLCD
332 This enables support for ARM Ltd RealView boards.
334 config ARCH_VERSATILE
335 bool "ARM Ltd. Versatile family"
336 select ARCH_WANT_OPTIONAL_GPIOLIB
338 select ARM_TIMER_SP804
341 select GENERIC_CLOCKEVENTS
342 select HAVE_MACH_CLKDEV
344 select PLAT_VERSATILE
345 select PLAT_VERSATILE_CLCD
346 select PLAT_VERSATILE_CLOCK
347 select VERSATILE_FPGA_IRQ
349 This enables support for ARM Ltd Versatile board.
353 select ARCH_REQUIRE_GPIOLIB
357 select NEED_MACH_GPIO_H
358 select NEED_MACH_IO_H if PCCARD
360 select PINCTRL_AT91 if USE_OF
362 This enables support for systems based on Atmel
363 AT91RM9200 and AT91SAM9* processors.
366 bool "Broadcom BCM2835 family"
367 select ARCH_REQUIRE_GPIOLIB
369 select ARM_ERRATA_411920
370 select ARM_TIMER_SP804
375 select GENERIC_CLOCKEVENTS
376 select MULTI_IRQ_HANDLER
378 select PINCTRL_BCM2835
382 This enables support for the Broadcom BCM2835 SoC. This SoC is
383 use in the Raspberry Pi, and Roku 2 devices.
386 bool "Cavium Networks CNS3XXX family"
389 select GENERIC_CLOCKEVENTS
390 select MIGHT_HAVE_CACHE_L2X0
391 select MIGHT_HAVE_PCI
392 select PCI_DOMAINS if PCI
394 Support for Cavium Networks CNS3XXX platform.
397 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
398 select ARCH_REQUIRE_GPIOLIB
403 select GENERIC_CLOCKEVENTS
404 select MULTI_IRQ_HANDLER
405 select NEED_MACH_MEMORY_H
408 Support for Cirrus Logic 711x/721x/731x based boards.
411 bool "Cortina Systems Gemini"
412 select ARCH_REQUIRE_GPIOLIB
413 select ARCH_USES_GETTIMEOFFSET
414 select NEED_MACH_GPIO_H
417 Support for the Cortina Systems Gemini family SoCs
421 select ARCH_REQUIRE_GPIOLIB
424 select GENERIC_CLOCKEVENTS
425 select GENERIC_IRQ_CHIP
426 select MIGHT_HAVE_CACHE_L2X0
432 Support for CSR SiRFprimaII/Marco/Polo platforms
436 select ARCH_USES_GETTIMEOFFSET
439 select NEED_MACH_IO_H
440 select NEED_MACH_MEMORY_H
443 This is an evaluation board for the StrongARM processor available
444 from Digital. It has limited hardware on-board, including an
445 Ethernet interface, two PCMCIA sockets, two serial ports and a
450 select ARCH_HAS_HOLES_MEMORYMODEL
451 select ARCH_REQUIRE_GPIOLIB
452 select ARCH_USES_GETTIMEOFFSET
457 select NEED_MACH_MEMORY_H
459 This enables support for the Cirrus EP93xx series of CPUs.
461 config ARCH_FOOTBRIDGE
465 select GENERIC_CLOCKEVENTS
467 select NEED_MACH_IO_H if !MMU
468 select NEED_MACH_MEMORY_H
470 Support for systems based on the DC21285 companion chip
471 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
474 bool "Freescale MXS-based"
475 select ARCH_REQUIRE_GPIOLIB
480 select GENERIC_CLOCKEVENTS
481 select HAVE_CLK_PREPARE
482 select MULTI_IRQ_HANDLER
488 Support for Freescale MXS-based family of processors
491 bool "Hilscher NetX based"
495 select GENERIC_CLOCKEVENTS
497 This enables support for systems based on the Hilscher NetX Soc
502 select ARCH_SUPPORTS_MSI
504 select NEED_MACH_MEMORY_H
505 select NEED_RET_TO_USER
510 Support for Intel's IOP13XX (XScale) family of processors.
515 select ARCH_REQUIRE_GPIOLIB
517 select NEED_MACH_GPIO_H
518 select NEED_RET_TO_USER
522 Support for Intel's 80219 and IOP32X (XScale) family of
528 select ARCH_REQUIRE_GPIOLIB
530 select NEED_MACH_GPIO_H
531 select NEED_RET_TO_USER
535 Support for Intel's IOP33X (XScale) family of processors.
540 select ARCH_HAS_DMA_SET_COHERENT_MASK
541 select ARCH_REQUIRE_GPIOLIB
544 select DMABOUNCE if PCI
545 select GENERIC_CLOCKEVENTS
546 select MIGHT_HAVE_PCI
547 select NEED_MACH_IO_H
548 select USB_EHCI_BIG_ENDIAN_MMIO
549 select USB_EHCI_BIG_ENDIAN_DESC
551 Support for Intel's IXP4XX (XScale) family of processors.
555 select ARCH_REQUIRE_GPIOLIB
557 select GENERIC_CLOCKEVENTS
558 select MIGHT_HAVE_PCI
561 select PLAT_ORION_LEGACY
562 select USB_ARCH_HAS_EHCI
564 Support for the Marvell Dove SoC 88AP510
567 bool "Marvell Kirkwood"
568 select ARCH_REQUIRE_GPIOLIB
570 select GENERIC_CLOCKEVENTS
574 select PINCTRL_KIRKWOOD
575 select PLAT_ORION_LEGACY
577 Support for the following Marvell Kirkwood series SoCs:
578 88F6180, 88F6192 and 88F6281.
581 bool "Marvell MV78xx0"
582 select ARCH_REQUIRE_GPIOLIB
584 select GENERIC_CLOCKEVENTS
586 select PLAT_ORION_LEGACY
588 Support for the following Marvell MV78xx0 series SoCs:
594 select ARCH_REQUIRE_GPIOLIB
596 select GENERIC_CLOCKEVENTS
598 select PLAT_ORION_LEGACY
600 Support for the following Marvell Orion 5x series SoCs:
601 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
602 Orion-2 (5281), Orion-1-90 (6183).
605 bool "Marvell PXA168/910/MMP2"
607 select ARCH_REQUIRE_GPIOLIB
609 select GENERIC_ALLOCATOR
610 select GENERIC_CLOCKEVENTS
613 select NEED_MACH_GPIO_H
618 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
621 bool "Micrel/Kendin KS8695"
622 select ARCH_REQUIRE_GPIOLIB
625 select GENERIC_CLOCKEVENTS
626 select NEED_MACH_MEMORY_H
628 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
629 System-on-Chip devices.
632 bool "Nuvoton W90X900 CPU"
633 select ARCH_REQUIRE_GPIOLIB
637 select GENERIC_CLOCKEVENTS
639 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
640 At present, the w90x900 has been renamed nuc900, regarding
641 the ARM series product line, you can login the following
642 link address to know more.
644 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
645 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
649 select ARCH_REQUIRE_GPIOLIB
654 select GENERIC_CLOCKEVENTS
657 select USB_ARCH_HAS_OHCI
660 Support for the NXP LPC32XX family of processors
664 select ARCH_HAS_CPUFREQ
665 select ARCH_REQUIRE_GPIOLIB
670 select GENERIC_CLOCKEVENTS
673 select MIGHT_HAVE_CACHE_L2X0
677 This enables support for NVIDIA Tegra based systems (Tegra APX,
678 Tegra 6xx and Tegra 2 series).
681 bool "PXA2xx/PXA3xx-based"
683 select ARCH_HAS_CPUFREQ
685 select ARCH_REQUIRE_GPIOLIB
686 select ARM_CPU_SUSPEND if PM
690 select GENERIC_CLOCKEVENTS
693 select MULTI_IRQ_HANDLER
694 select NEED_MACH_GPIO_H
698 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
702 select ARCH_REQUIRE_GPIOLIB
704 select GENERIC_CLOCKEVENTS
707 Support for Qualcomm MSM/QSD based systems. This runs on the
708 apps processor of the MSM/QSD and depends on a shared memory
709 interface to the modem processor which runs the baseband
710 stack and controls some vital subsystems
711 (clock and power control, etc).
714 bool "Renesas SH-Mobile / R-Mobile"
716 select GENERIC_CLOCKEVENTS
718 select HAVE_MACH_CLKDEV
720 select MIGHT_HAVE_CACHE_L2X0
721 select MULTI_IRQ_HANDLER
722 select NEED_MACH_MEMORY_H
725 select PM_GENERIC_DOMAINS if PM
728 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
733 select ARCH_MAY_HAVE_PC_FDC
734 select ARCH_SPARSEMEM_ENABLE
735 select ARCH_USES_GETTIMEOFFSET
738 select HAVE_PATA_PLATFORM
740 select NEED_MACH_IO_H
741 select NEED_MACH_MEMORY_H
745 On the Acorn Risc-PC, Linux can support the internal IDE disk and
746 CD-ROM interface, serial and parallel port, and the floppy drive.
750 select ARCH_HAS_CPUFREQ
752 select ARCH_REQUIRE_GPIOLIB
753 select ARCH_SPARSEMEM_ENABLE
758 select GENERIC_CLOCKEVENTS
761 select NEED_MACH_GPIO_H
762 select NEED_MACH_MEMORY_H
765 Support for StrongARM 11x0 based boards.
768 bool "Samsung S3C24XX SoCs"
769 select ARCH_HAS_CPUFREQ
770 select ARCH_USES_GETTIMEOFFSET
773 select HAVE_S3C2410_I2C if I2C
774 select HAVE_S3C2410_WATCHDOG if WATCHDOG
775 select HAVE_S3C_RTC if RTC_CLASS
776 select NEED_MACH_GPIO_H
777 select NEED_MACH_IO_H
779 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
780 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
781 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
782 Samsung SMDK2410 development board (and derivatives).
785 bool "Samsung S3C64XX"
786 select ARCH_HAS_CPUFREQ
787 select ARCH_REQUIRE_GPIOLIB
788 select ARCH_USES_GETTIMEOFFSET
793 select HAVE_S3C2410_I2C if I2C
794 select HAVE_S3C2410_WATCHDOG if WATCHDOG
796 select NEED_MACH_GPIO_H
800 select S3C_GPIO_TRACK
801 select SAMSUNG_CLKSRC
802 select SAMSUNG_GPIOLIB_4BIT
803 select SAMSUNG_IRQ_VIC_TIMER
804 select USB_ARCH_HAS_OHCI
806 Samsung S3C64XX series based systems
809 bool "Samsung S5P6440 S5P6450"
813 select GENERIC_CLOCKEVENTS
815 select HAVE_S3C2410_I2C if I2C
816 select HAVE_S3C2410_WATCHDOG if WATCHDOG
817 select HAVE_S3C_RTC if RTC_CLASS
818 select NEED_MACH_GPIO_H
820 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
824 bool "Samsung S5PC100"
825 select ARCH_USES_GETTIMEOFFSET
829 select HAVE_S3C2410_I2C if I2C
830 select HAVE_S3C2410_WATCHDOG if WATCHDOG
831 select HAVE_S3C_RTC if RTC_CLASS
832 select NEED_MACH_GPIO_H
834 Samsung S5PC100 series based systems
837 bool "Samsung S5PV210/S5PC110"
838 select ARCH_HAS_CPUFREQ
839 select ARCH_HAS_HOLES_MEMORYMODEL
840 select ARCH_SPARSEMEM_ENABLE
844 select GENERIC_CLOCKEVENTS
846 select HAVE_S3C2410_I2C if I2C
847 select HAVE_S3C2410_WATCHDOG if WATCHDOG
848 select HAVE_S3C_RTC if RTC_CLASS
849 select NEED_MACH_GPIO_H
850 select NEED_MACH_MEMORY_H
852 Samsung S5PV210/S5PC110 series based systems
855 bool "Samsung EXYNOS"
856 select ARCH_HAS_CPUFREQ
857 select ARCH_HAS_HOLES_MEMORYMODEL
858 select ARCH_SPARSEMEM_ENABLE
861 select GENERIC_CLOCKEVENTS
863 select HAVE_S3C2410_I2C if I2C
864 select HAVE_S3C2410_WATCHDOG if WATCHDOG
865 select HAVE_S3C_RTC if RTC_CLASS
866 select NEED_MACH_GPIO_H
867 select NEED_MACH_MEMORY_H
869 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
873 select ARCH_USES_GETTIMEOFFSET
877 select NEED_MACH_MEMORY_H
882 Support for the StrongARM based Digital DNARD machine, also known
883 as "Shark" (<http://www.shark-linux.de/shark.html>).
886 bool "ST-Ericsson U300 Series"
888 select ARCH_REQUIRE_GPIOLIB
890 select ARM_PATCH_PHYS_VIRT
896 select GENERIC_CLOCKEVENTS
900 Support for ST-Ericsson U300 series mobile platforms.
903 bool "ST-Ericsson U8500 Series"
905 select ARCH_HAS_CPUFREQ
906 select ARCH_REQUIRE_GPIOLIB
910 select GENERIC_CLOCKEVENTS
912 select MIGHT_HAVE_CACHE_L2X0
915 Support for ST-Ericsson's Ux500 architecture
918 bool "STMicroelectronics Nomadik"
919 select ARCH_REQUIRE_GPIOLIB
922 select CLKSRC_NOMADIK_MTU
925 select GENERIC_CLOCKEVENTS
926 select MIGHT_HAVE_CACHE_L2X0
929 select PINCTRL_STN8815
932 Support for the Nomadik platform by ST-Ericsson
936 select ARCH_HAS_CPUFREQ
937 select ARCH_REQUIRE_GPIOLIB
942 select GENERIC_CLOCKEVENTS
945 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
949 select ARCH_HAS_HOLES_MEMORYMODEL
950 select ARCH_REQUIRE_GPIOLIB
952 select GENERIC_ALLOCATOR
953 select GENERIC_CLOCKEVENTS
954 select GENERIC_IRQ_CHIP
956 select NEED_MACH_GPIO_H
960 Support for TI's DaVinci platform.
965 select ARCH_HAS_CPUFREQ
966 select ARCH_HAS_HOLES_MEMORYMODEL
968 select ARCH_REQUIRE_GPIOLIB
971 select GENERIC_CLOCKEVENTS
972 select GENERIC_IRQ_CHIP
976 select NEED_MACH_IO_H if PCCARD
977 select NEED_MACH_MEMORY_H
979 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
983 menu "Multiple platform selection"
984 depends on ARCH_MULTIPLATFORM
986 comment "CPU Core family selection"
989 bool "ARMv4 based platforms (FA526, StrongARM)"
990 depends on !ARCH_MULTI_V6_V7
991 select ARCH_MULTI_V4_V5
993 config ARCH_MULTI_V4T
994 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
995 depends on !ARCH_MULTI_V6_V7
996 select ARCH_MULTI_V4_V5
999 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
1000 depends on !ARCH_MULTI_V6_V7
1001 select ARCH_MULTI_V4_V5
1003 config ARCH_MULTI_V4_V5
1006 config ARCH_MULTI_V6
1007 bool "ARMv6 based platforms (ARM11)"
1008 select ARCH_MULTI_V6_V7
1011 config ARCH_MULTI_V7
1012 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
1014 select ARCH_MULTI_V6_V7
1015 select ARCH_VEXPRESS
1018 config ARCH_MULTI_V6_V7
1021 config ARCH_MULTI_CPU_AUTO
1022 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1023 select ARCH_MULTI_V5
1028 # This is sorted alphabetically by mach-* pathname. However, plat-*
1029 # Kconfigs may be included either alphabetically (according to the
1030 # plat- suffix) or along side the corresponding mach-* source.
1032 source "arch/arm/mach-mvebu/Kconfig"
1034 source "arch/arm/mach-at91/Kconfig"
1036 source "arch/arm/mach-bcm/Kconfig"
1038 source "arch/arm/mach-clps711x/Kconfig"
1040 source "arch/arm/mach-cns3xxx/Kconfig"
1042 source "arch/arm/mach-davinci/Kconfig"
1044 source "arch/arm/mach-dove/Kconfig"
1046 source "arch/arm/mach-ep93xx/Kconfig"
1048 source "arch/arm/mach-footbridge/Kconfig"
1050 source "arch/arm/mach-gemini/Kconfig"
1052 source "arch/arm/mach-highbank/Kconfig"
1054 source "arch/arm/mach-integrator/Kconfig"
1056 source "arch/arm/mach-iop32x/Kconfig"
1058 source "arch/arm/mach-iop33x/Kconfig"
1060 source "arch/arm/mach-iop13xx/Kconfig"
1062 source "arch/arm/mach-ixp4xx/Kconfig"
1064 source "arch/arm/mach-kirkwood/Kconfig"
1066 source "arch/arm/mach-ks8695/Kconfig"
1068 source "arch/arm/mach-msm/Kconfig"
1070 source "arch/arm/mach-mv78xx0/Kconfig"
1072 source "arch/arm/mach-imx/Kconfig"
1074 source "arch/arm/mach-mxs/Kconfig"
1076 source "arch/arm/mach-netx/Kconfig"
1078 source "arch/arm/mach-nomadik/Kconfig"
1080 source "arch/arm/plat-omap/Kconfig"
1082 source "arch/arm/mach-omap1/Kconfig"
1084 source "arch/arm/mach-omap2/Kconfig"
1086 source "arch/arm/mach-orion5x/Kconfig"
1088 source "arch/arm/mach-picoxcell/Kconfig"
1090 source "arch/arm/mach-pxa/Kconfig"
1091 source "arch/arm/plat-pxa/Kconfig"
1093 source "arch/arm/mach-mmp/Kconfig"
1095 source "arch/arm/mach-realview/Kconfig"
1097 source "arch/arm/mach-sa1100/Kconfig"
1099 source "arch/arm/plat-samsung/Kconfig"
1101 source "arch/arm/mach-socfpga/Kconfig"
1103 source "arch/arm/plat-spear/Kconfig"
1105 source "arch/arm/mach-s3c24xx/Kconfig"
1108 source "arch/arm/mach-s3c64xx/Kconfig"
1111 source "arch/arm/mach-s5p64x0/Kconfig"
1113 source "arch/arm/mach-s5pc100/Kconfig"
1115 source "arch/arm/mach-s5pv210/Kconfig"
1117 source "arch/arm/mach-exynos/Kconfig"
1119 source "arch/arm/mach-shmobile/Kconfig"
1121 source "arch/arm/mach-sunxi/Kconfig"
1123 source "arch/arm/mach-prima2/Kconfig"
1125 source "arch/arm/mach-tegra/Kconfig"
1127 source "arch/arm/mach-u300/Kconfig"
1129 source "arch/arm/mach-ux500/Kconfig"
1131 source "arch/arm/mach-versatile/Kconfig"
1133 source "arch/arm/mach-vexpress/Kconfig"
1134 source "arch/arm/plat-versatile/Kconfig"
1136 source "arch/arm/mach-virt/Kconfig"
1138 source "arch/arm/mach-vt8500/Kconfig"
1140 source "arch/arm/mach-w90x900/Kconfig"
1142 source "arch/arm/mach-zynq/Kconfig"
1144 # Definitions to make life easier
1150 select GENERIC_CLOCKEVENTS
1156 select GENERIC_IRQ_CHIP
1159 config PLAT_ORION_LEGACY
1166 config PLAT_VERSATILE
1169 config ARM_TIMER_SP804
1173 source arch/arm/mm/Kconfig
1177 default 16 if ARCH_EP93XX
1181 bool "Enable iWMMXt support" if !CPU_PJ4
1182 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1183 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1185 Enable support for iWMMXt context switching at run time if
1186 running on a CPU that supports it.
1190 depends on CPU_XSCALE
1193 config MULTI_IRQ_HANDLER
1196 Allow each machine to specify it's own IRQ handler at run time.
1199 source "arch/arm/Kconfig-nommu"
1202 config ARM_ERRATA_326103
1203 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1206 Executing a SWP instruction to read-only memory does not set bit 11
1207 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1208 treat the access as a read, preventing a COW from occurring and
1209 causing the faulting task to livelock.
1211 config ARM_ERRATA_411920
1212 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1213 depends on CPU_V6 || CPU_V6K
1215 Invalidation of the Instruction Cache operation can
1216 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1217 It does not affect the MPCore. This option enables the ARM Ltd.
1218 recommended workaround.
1220 config ARM_ERRATA_430973
1221 bool "ARM errata: Stale prediction on replaced interworking branch"
1224 This option enables the workaround for the 430973 Cortex-A8
1225 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1226 interworking branch is replaced with another code sequence at the
1227 same virtual address, whether due to self-modifying code or virtual
1228 to physical address re-mapping, Cortex-A8 does not recover from the
1229 stale interworking branch prediction. This results in Cortex-A8
1230 executing the new code sequence in the incorrect ARM or Thumb state.
1231 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1232 and also flushes the branch target cache at every context switch.
1233 Note that setting specific bits in the ACTLR register may not be
1234 available in non-secure mode.
1236 config ARM_ERRATA_458693
1237 bool "ARM errata: Processor deadlock when a false hazard is created"
1239 depends on !ARCH_MULTIPLATFORM
1241 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1242 erratum. For very specific sequences of memory operations, it is
1243 possible for a hazard condition intended for a cache line to instead
1244 be incorrectly associated with a different cache line. This false
1245 hazard might then cause a processor deadlock. The workaround enables
1246 the L1 caching of the NEON accesses and disables the PLD instruction
1247 in the ACTLR register. Note that setting specific bits in the ACTLR
1248 register may not be available in non-secure mode.
1250 config ARM_ERRATA_460075
1251 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1253 depends on !ARCH_MULTIPLATFORM
1255 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1256 erratum. Any asynchronous access to the L2 cache may encounter a
1257 situation in which recent store transactions to the L2 cache are lost
1258 and overwritten with stale memory contents from external memory. The
1259 workaround disables the write-allocate mode for the L2 cache via the
1260 ACTLR register. Note that setting specific bits in the ACTLR register
1261 may not be available in non-secure mode.
1263 config ARM_ERRATA_742230
1264 bool "ARM errata: DMB operation may be faulty"
1265 depends on CPU_V7 && SMP
1266 depends on !ARCH_MULTIPLATFORM
1268 This option enables the workaround for the 742230 Cortex-A9
1269 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1270 between two write operations may not ensure the correct visibility
1271 ordering of the two writes. This workaround sets a specific bit in
1272 the diagnostic register of the Cortex-A9 which causes the DMB
1273 instruction to behave as a DSB, ensuring the correct behaviour of
1276 config ARM_ERRATA_742231
1277 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1278 depends on CPU_V7 && SMP
1279 depends on !ARCH_MULTIPLATFORM
1281 This option enables the workaround for the 742231 Cortex-A9
1282 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1283 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1284 accessing some data located in the same cache line, may get corrupted
1285 data due to bad handling of the address hazard when the line gets
1286 replaced from one of the CPUs at the same time as another CPU is
1287 accessing it. This workaround sets specific bits in the diagnostic
1288 register of the Cortex-A9 which reduces the linefill issuing
1289 capabilities of the processor.
1291 config PL310_ERRATA_588369
1292 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1293 depends on CACHE_L2X0
1295 The PL310 L2 cache controller implements three types of Clean &
1296 Invalidate maintenance operations: by Physical Address
1297 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1298 They are architecturally defined to behave as the execution of a
1299 clean operation followed immediately by an invalidate operation,
1300 both performing to the same memory location. This functionality
1301 is not correctly implemented in PL310 as clean lines are not
1302 invalidated as a result of these operations.
1304 config ARM_ERRATA_720789
1305 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1308 This option enables the workaround for the 720789 Cortex-A9 (prior to
1309 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1310 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1311 As a consequence of this erratum, some TLB entries which should be
1312 invalidated are not, resulting in an incoherency in the system page
1313 tables. The workaround changes the TLB flushing routines to invalidate
1314 entries regardless of the ASID.
1316 config PL310_ERRATA_727915
1317 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1318 depends on CACHE_L2X0
1320 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1321 operation (offset 0x7FC). This operation runs in background so that
1322 PL310 can handle normal accesses while it is in progress. Under very
1323 rare circumstances, due to this erratum, write data can be lost when
1324 PL310 treats a cacheable write transaction during a Clean &
1325 Invalidate by Way operation.
1327 config ARM_ERRATA_743622
1328 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1330 depends on !ARCH_MULTIPLATFORM
1332 This option enables the workaround for the 743622 Cortex-A9
1333 (r2p*) erratum. Under very rare conditions, a faulty
1334 optimisation in the Cortex-A9 Store Buffer may lead to data
1335 corruption. This workaround sets a specific bit in the diagnostic
1336 register of the Cortex-A9 which disables the Store Buffer
1337 optimisation, preventing the defect from occurring. This has no
1338 visible impact on the overall performance or power consumption of the
1341 config ARM_ERRATA_751472
1342 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1344 depends on !ARCH_MULTIPLATFORM
1346 This option enables the workaround for the 751472 Cortex-A9 (prior
1347 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1348 completion of a following broadcasted operation if the second
1349 operation is received by a CPU before the ICIALLUIS has completed,
1350 potentially leading to corrupted entries in the cache or TLB.
1352 config PL310_ERRATA_753970
1353 bool "PL310 errata: cache sync operation may be faulty"
1354 depends on CACHE_PL310
1356 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1358 Under some condition the effect of cache sync operation on
1359 the store buffer still remains when the operation completes.
1360 This means that the store buffer is always asked to drain and
1361 this prevents it from merging any further writes. The workaround
1362 is to replace the normal offset of cache sync operation (0x730)
1363 by another offset targeting an unmapped PL310 register 0x740.
1364 This has the same effect as the cache sync operation: store buffer
1365 drain and waiting for all buffers empty.
1367 config ARM_ERRATA_754322
1368 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1371 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1372 r3p*) erratum. A speculative memory access may cause a page table walk
1373 which starts prior to an ASID switch but completes afterwards. This
1374 can populate the micro-TLB with a stale entry which may be hit with
1375 the new ASID. This workaround places two dsb instructions in the mm
1376 switching code so that no page table walks can cross the ASID switch.
1378 config ARM_ERRATA_754327
1379 bool "ARM errata: no automatic Store Buffer drain"
1380 depends on CPU_V7 && SMP
1382 This option enables the workaround for the 754327 Cortex-A9 (prior to
1383 r2p0) erratum. The Store Buffer does not have any automatic draining
1384 mechanism and therefore a livelock may occur if an external agent
1385 continuously polls a memory location waiting to observe an update.
1386 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1387 written polling loops from denying visibility of updates to memory.
1389 config ARM_ERRATA_364296
1390 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1391 depends on CPU_V6 && !SMP
1393 This options enables the workaround for the 364296 ARM1136
1394 r0p2 erratum (possible cache data corruption with
1395 hit-under-miss enabled). It sets the undocumented bit 31 in
1396 the auxiliary control register and the FI bit in the control
1397 register, thus disabling hit-under-miss without putting the
1398 processor into full low interrupt latency mode. ARM11MPCore
1401 config ARM_ERRATA_764369
1402 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1403 depends on CPU_V7 && SMP
1405 This option enables the workaround for erratum 764369
1406 affecting Cortex-A9 MPCore with two or more processors (all
1407 current revisions). Under certain timing circumstances, a data
1408 cache line maintenance operation by MVA targeting an Inner
1409 Shareable memory region may fail to proceed up to either the
1410 Point of Coherency or to the Point of Unification of the
1411 system. This workaround adds a DSB instruction before the
1412 relevant cache maintenance functions and sets a specific bit
1413 in the diagnostic control register of the SCU.
1415 config PL310_ERRATA_769419
1416 bool "PL310 errata: no automatic Store Buffer drain"
1417 depends on CACHE_L2X0
1419 On revisions of the PL310 prior to r3p2, the Store Buffer does
1420 not automatically drain. This can cause normal, non-cacheable
1421 writes to be retained when the memory system is idle, leading
1422 to suboptimal I/O performance for drivers using coherent DMA.
1423 This option adds a write barrier to the cpu_idle loop so that,
1424 on systems with an outer cache, the store buffer is drained
1427 config ARM_ERRATA_775420
1428 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1431 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1432 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1433 operation aborts with MMU exception, it might cause the processor
1434 to deadlock. This workaround puts DSB before executing ISB if
1435 an abort may occur on cache maintenance.
1437 config ARM_ERRATA_798181
1438 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1439 depends on CPU_V7 && SMP
1441 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1442 adequately shooting down all use of the old entries. This
1443 option enables the Linux kernel workaround for this erratum
1444 which sends an IPI to the CPUs that are running the same ASID
1445 as the one being invalidated.
1449 source "arch/arm/common/Kconfig"
1459 Find out whether you have ISA slots on your motherboard. ISA is the
1460 name of a bus system, i.e. the way the CPU talks to the other stuff
1461 inside your box. Other bus systems are PCI, EISA, MicroChannel
1462 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1463 newer boards don't support it. If you have ISA, say Y, otherwise N.
1465 # Select ISA DMA controller support
1470 # Select ISA DMA interface
1475 bool "PCI support" if MIGHT_HAVE_PCI
1477 Find out whether you have a PCI motherboard. PCI is the name of a
1478 bus system, i.e. the way the CPU talks to the other stuff inside
1479 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1480 VESA. If you have PCI, say Y, otherwise N.
1486 config PCI_NANOENGINE
1487 bool "BSE nanoEngine PCI support"
1488 depends on SA1100_NANOENGINE
1490 Enable PCI on the BSE nanoEngine board.
1495 # Select the host bridge type
1496 config PCI_HOST_VIA82C505
1498 depends on PCI && ARCH_SHARK
1501 config PCI_HOST_ITE8152
1503 depends on PCI && MACH_ARMCORE
1507 source "drivers/pci/Kconfig"
1509 source "drivers/pcmcia/Kconfig"
1513 menu "Kernel Features"
1518 This option should be selected by machines which have an SMP-
1521 The only effect of this option is to make the SMP-related
1522 options available to the user for configuration.
1525 bool "Symmetric Multi-Processing"
1526 depends on CPU_V6K || CPU_V7
1527 depends on GENERIC_CLOCKEVENTS
1530 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1531 select USE_GENERIC_SMP_HELPERS
1533 This enables support for systems with more than one CPU. If you have
1534 a system with only one CPU, like most personal computers, say N. If
1535 you have a system with more than one CPU, say Y.
1537 If you say N here, the kernel will run on single and multiprocessor
1538 machines, but will use only one CPU of a multiprocessor machine. If
1539 you say Y here, the kernel will run on many, but not all, single
1540 processor machines. On a single processor machine, the kernel will
1541 run faster if you say N here.
1543 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1544 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1545 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1547 If you don't know what to do here, say N.
1550 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1551 depends on SMP && !XIP_KERNEL
1554 SMP kernels contain instructions which fail on non-SMP processors.
1555 Enabling this option allows the kernel to modify itself to make
1556 these instructions safe. Disabling it allows about 1K of space
1559 If you don't know what to do here, say Y.
1561 config ARM_CPU_TOPOLOGY
1562 bool "Support cpu topology definition"
1563 depends on SMP && CPU_V7
1566 Support ARM cpu topology definition. The MPIDR register defines
1567 affinity between processors which is then used to describe the cpu
1568 topology of an ARM System.
1571 bool "Multi-core scheduler support"
1572 depends on ARM_CPU_TOPOLOGY
1574 Multi-core scheduler support improves the CPU scheduler's decision
1575 making when dealing with multi-core CPU chips at a cost of slightly
1576 increased overhead in some places. If unsure say N here.
1579 bool "SMT scheduler support"
1580 depends on ARM_CPU_TOPOLOGY
1582 Improves the CPU scheduler's decision making when dealing with
1583 MultiThreading at a cost of slightly increased overhead in some
1584 places. If unsure say N here.
1589 This option enables support for the ARM system coherency unit
1591 config HAVE_ARM_ARCH_TIMER
1592 bool "Architected timer support"
1594 select ARM_ARCH_TIMER
1596 This option enables support for the ARM architected timer
1601 select CLKSRC_OF if OF
1603 This options enables support for the ARM timer and watchdog unit
1606 prompt "Memory split"
1609 Select the desired split between kernel and user memory.
1611 If you are not absolutely sure what you are doing, leave this
1615 bool "3G/1G user/kernel split"
1617 bool "2G/2G user/kernel split"
1619 bool "1G/3G user/kernel split"
1624 default 0x40000000 if VMSPLIT_1G
1625 default 0x80000000 if VMSPLIT_2G
1629 int "Maximum number of CPUs (2-32)"
1635 bool "Support for hot-pluggable CPUs"
1636 depends on SMP && HOTPLUG
1638 Say Y here to experiment with turning CPUs off and on. CPUs
1639 can be controlled through /sys/devices/system/cpu.
1642 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1645 Say Y here if you want Linux to communicate with system firmware
1646 implementing the PSCI specification for CPU-centric power
1647 management operations described in ARM document number ARM DEN
1648 0022A ("Power State Coordination Interface System Software on
1652 bool "Use local timer interrupts"
1655 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1657 Enable support for local timers on SMP platforms, rather then the
1658 legacy IPI broadcast method. Local timers allows the system
1659 accounting to be spread across the timer interval, preventing a
1660 "thundering herd" at every timer tick.
1662 # The GPIO number here must be sorted by descending number. In case of
1663 # a multiplatform kernel, we just want the highest value required by the
1664 # selected platforms.
1667 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1668 default 512 if SOC_OMAP5
1669 default 355 if ARCH_U8500
1670 default 288 if ARCH_VT8500 || ARCH_SUNXI
1671 default 264 if MACH_H4700
1674 Maximum number of GPIOs in the system.
1676 If unsure, leave the default value.
1678 source kernel/Kconfig.preempt
1682 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1683 ARCH_S5PV210 || ARCH_EXYNOS4
1684 default AT91_TIMER_HZ if ARCH_AT91
1685 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1689 def_bool HIGH_RES_TIMERS
1691 config THUMB2_KERNEL
1692 bool "Compile the kernel in Thumb-2 mode"
1693 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1695 select ARM_ASM_UNIFIED
1698 By enabling this option, the kernel will be compiled in
1699 Thumb-2 mode. A compiler/assembler that understand the unified
1700 ARM-Thumb syntax is needed.
1704 config THUMB2_AVOID_R_ARM_THM_JUMP11
1705 bool "Work around buggy Thumb-2 short branch relocations in gas"
1706 depends on THUMB2_KERNEL && MODULES
1709 Various binutils versions can resolve Thumb-2 branches to
1710 locally-defined, preemptible global symbols as short-range "b.n"
1711 branch instructions.
1713 This is a problem, because there's no guarantee the final
1714 destination of the symbol, or any candidate locations for a
1715 trampoline, are within range of the branch. For this reason, the
1716 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1717 relocation in modules at all, and it makes little sense to add
1720 The symptom is that the kernel fails with an "unsupported
1721 relocation" error when loading some modules.
1723 Until fixed tools are available, passing
1724 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1725 code which hits this problem, at the cost of a bit of extra runtime
1726 stack usage in some cases.
1728 The problem is described in more detail at:
1729 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1731 Only Thumb-2 kernels are affected.
1733 Unless you are sure your tools don't have this problem, say Y.
1735 config ARM_ASM_UNIFIED
1739 bool "Use the ARM EABI to compile the kernel"
1741 This option allows for the kernel to be compiled using the latest
1742 ARM ABI (aka EABI). This is only useful if you are using a user
1743 space environment that is also compiled with EABI.
1745 Since there are major incompatibilities between the legacy ABI and
1746 EABI, especially with regard to structure member alignment, this
1747 option also changes the kernel syscall calling convention to
1748 disambiguate both ABIs and allow for backward compatibility support
1749 (selected with CONFIG_OABI_COMPAT).
1751 To use this you need GCC version 4.0.0 or later.
1754 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1755 depends on AEABI && !THUMB2_KERNEL
1758 This option preserves the old syscall interface along with the
1759 new (ARM EABI) one. It also provides a compatibility layer to
1760 intercept syscalls that have structure arguments which layout
1761 in memory differs between the legacy ABI and the new ARM EABI
1762 (only for non "thumb" binaries). This option adds a tiny
1763 overhead to all syscalls and produces a slightly larger kernel.
1764 If you know you'll be using only pure EABI user space then you
1765 can say N here. If this option is not selected and you attempt
1766 to execute a legacy ABI binary then the result will be
1767 UNPREDICTABLE (in fact it can be predicted that it won't work
1768 at all). If in doubt say Y.
1770 config ARCH_HAS_HOLES_MEMORYMODEL
1773 config ARCH_SPARSEMEM_ENABLE
1776 config ARCH_SPARSEMEM_DEFAULT
1777 def_bool ARCH_SPARSEMEM_ENABLE
1779 config ARCH_SELECT_MEMORY_MODEL
1780 def_bool ARCH_SPARSEMEM_ENABLE
1782 config HAVE_ARCH_PFN_VALID
1783 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1786 bool "High Memory Support"
1789 The address space of ARM processors is only 4 Gigabytes large
1790 and it has to accommodate user address space, kernel address
1791 space as well as some memory mapped IO. That means that, if you
1792 have a large amount of physical memory and/or IO, not all of the
1793 memory can be "permanently mapped" by the kernel. The physical
1794 memory that is not permanently mapped is called "high memory".
1796 Depending on the selected kernel/user memory split, minimum
1797 vmalloc space and actual amount of RAM, you may not need this
1798 option which should result in a slightly faster kernel.
1803 bool "Allocate 2nd-level pagetables from highmem"
1806 config HW_PERF_EVENTS
1807 bool "Enable hardware performance counter support for perf events"
1808 depends on PERF_EVENTS
1811 Enable hardware performance counter support for perf events. If
1812 disabled, perf events will use software events only.
1816 config FORCE_MAX_ZONEORDER
1817 int "Maximum zone order" if ARCH_SHMOBILE
1818 range 11 64 if ARCH_SHMOBILE
1819 default "12" if SOC_AM33XX
1820 default "9" if SA1111
1823 The kernel memory allocator divides physically contiguous memory
1824 blocks into "zones", where each zone is a power of two number of
1825 pages. This option selects the largest power of two that the kernel
1826 keeps in the memory allocator. If you need to allocate very large
1827 blocks of physically contiguous memory, then you may need to
1828 increase this value.
1830 This config option is actually maximum order plus one. For example,
1831 a value of 11 means that the largest free memory block is 2^10 pages.
1833 config ALIGNMENT_TRAP
1835 depends on CPU_CP15_MMU
1836 default y if !ARCH_EBSA110
1837 select HAVE_PROC_CPU if PROC_FS
1839 ARM processors cannot fetch/store information which is not
1840 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1841 address divisible by 4. On 32-bit ARM processors, these non-aligned
1842 fetch/store instructions will be emulated in software if you say
1843 here, which has a severe performance impact. This is necessary for
1844 correct operation of some network protocols. With an IP-only
1845 configuration it is safe to say N, otherwise say Y.
1847 config UACCESS_WITH_MEMCPY
1848 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1850 default y if CPU_FEROCEON
1852 Implement faster copy_to_user and clear_user methods for CPU
1853 cores where a 8-word STM instruction give significantly higher
1854 memory write throughput than a sequence of individual 32bit stores.
1856 A possible side effect is a slight increase in scheduling latency
1857 between threads sharing the same address space if they invoke
1858 such copy operations with large buffers.
1860 However, if the CPU data cache is using a write-allocate mode,
1861 this option is unlikely to provide any performance gain.
1865 prompt "Enable seccomp to safely compute untrusted bytecode"
1867 This kernel feature is useful for number crunching applications
1868 that may need to compute untrusted bytecode during their
1869 execution. By using pipes or other transports made available to
1870 the process as file descriptors supporting the read/write
1871 syscalls, it's possible to isolate those applications in
1872 their own address space using seccomp. Once seccomp is
1873 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1874 and the task is only allowed to execute a few safe syscalls
1875 defined by each seccomp mode.
1877 config CC_STACKPROTECTOR
1878 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1880 This option turns on the -fstack-protector GCC feature. This
1881 feature puts, at the beginning of functions, a canary value on
1882 the stack just before the return address, and validates
1883 the value just before actually returning. Stack based buffer
1884 overflows (that need to overwrite this return address) now also
1885 overwrite the canary, which gets detected and the attack is then
1886 neutralized via a kernel panic.
1887 This feature requires gcc version 4.2 or above.
1894 bool "Xen guest support on ARM (EXPERIMENTAL)"
1895 depends on ARM && AEABI && OF
1896 depends on CPU_V7 && !CPU_V6
1897 depends on !GENERIC_ATOMIC64
1899 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1906 bool "Flattened Device Tree support"
1909 select OF_EARLY_FLATTREE
1911 Include support for flattened device tree machine descriptions.
1914 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1917 This is the traditional way of passing data to the kernel at boot
1918 time. If you are solely relying on the flattened device tree (or
1919 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1920 to remove ATAGS support from your kernel binary. If unsure,
1923 config DEPRECATED_PARAM_STRUCT
1924 bool "Provide old way to pass kernel parameters"
1927 This was deprecated in 2001 and announced to live on for 5 years.
1928 Some old boot loaders still use this way.
1930 # Compressed boot loader in ROM. Yes, we really want to ask about
1931 # TEXT and BSS so we preserve their values in the config files.
1932 config ZBOOT_ROM_TEXT
1933 hex "Compressed ROM boot loader base address"
1936 The physical address at which the ROM-able zImage is to be
1937 placed in the target. Platforms which normally make use of
1938 ROM-able zImage formats normally set this to a suitable
1939 value in their defconfig file.
1941 If ZBOOT_ROM is not enabled, this has no effect.
1943 config ZBOOT_ROM_BSS
1944 hex "Compressed ROM boot loader BSS address"
1947 The base address of an area of read/write memory in the target
1948 for the ROM-able zImage which must be available while the
1949 decompressor is running. It must be large enough to hold the
1950 entire decompressed kernel plus an additional 128 KiB.
1951 Platforms which normally make use of ROM-able zImage formats
1952 normally set this to a suitable value in their defconfig file.
1954 If ZBOOT_ROM is not enabled, this has no effect.
1957 bool "Compressed boot loader in ROM/flash"
1958 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1960 Say Y here if you intend to execute your compressed kernel image
1961 (zImage) directly from ROM or flash. If unsure, say N.
1964 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1965 depends on ZBOOT_ROM && ARCH_SH7372
1966 default ZBOOT_ROM_NONE
1968 Include experimental SD/MMC loading code in the ROM-able zImage.
1969 With this enabled it is possible to write the ROM-able zImage
1970 kernel image to an MMC or SD card and boot the kernel straight
1971 from the reset vector. At reset the processor Mask ROM will load
1972 the first part of the ROM-able zImage which in turn loads the
1973 rest the kernel image to RAM.
1975 config ZBOOT_ROM_NONE
1976 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1978 Do not load image from SD or MMC
1980 config ZBOOT_ROM_MMCIF
1981 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1983 Load image from MMCIF hardware block.
1985 config ZBOOT_ROM_SH_MOBILE_SDHI
1986 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1988 Load image from SDHI hardware block
1992 config ARM_APPENDED_DTB
1993 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1994 depends on OF && !ZBOOT_ROM
1996 With this option, the boot code will look for a device tree binary
1997 (DTB) appended to zImage
1998 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2000 This is meant as a backward compatibility convenience for those
2001 systems with a bootloader that can't be upgraded to accommodate
2002 the documented boot protocol using a device tree.
2004 Beware that there is very little in terms of protection against
2005 this option being confused by leftover garbage in memory that might
2006 look like a DTB header after a reboot if no actual DTB is appended
2007 to zImage. Do not leave this option active in a production kernel
2008 if you don't intend to always append a DTB. Proper passing of the
2009 location into r2 of a bootloader provided DTB is always preferable
2012 config ARM_ATAG_DTB_COMPAT
2013 bool "Supplement the appended DTB with traditional ATAG information"
2014 depends on ARM_APPENDED_DTB
2016 Some old bootloaders can't be updated to a DTB capable one, yet
2017 they provide ATAGs with memory configuration, the ramdisk address,
2018 the kernel cmdline string, etc. Such information is dynamically
2019 provided by the bootloader and can't always be stored in a static
2020 DTB. To allow a device tree enabled kernel to be used with such
2021 bootloaders, this option allows zImage to extract the information
2022 from the ATAG list and store it at run time into the appended DTB.
2025 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2026 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2028 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2029 bool "Use bootloader kernel arguments if available"
2031 Uses the command-line options passed by the boot loader instead of
2032 the device tree bootargs property. If the boot loader doesn't provide
2033 any, the device tree bootargs property will be used.
2035 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2036 bool "Extend with bootloader kernel arguments"
2038 The command-line arguments provided by the boot loader will be
2039 appended to the the device tree bootargs property.
2044 string "Default kernel command string"
2047 On some architectures (EBSA110 and CATS), there is currently no way
2048 for the boot loader to pass arguments to the kernel. For these
2049 architectures, you should supply some command-line options at build
2050 time by entering them here. As a minimum, you should specify the
2051 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2054 prompt "Kernel command line type" if CMDLINE != ""
2055 default CMDLINE_FROM_BOOTLOADER
2058 config CMDLINE_FROM_BOOTLOADER
2059 bool "Use bootloader kernel arguments if available"
2061 Uses the command-line options passed by the boot loader. If
2062 the boot loader doesn't provide any, the default kernel command
2063 string provided in CMDLINE will be used.
2065 config CMDLINE_EXTEND
2066 bool "Extend bootloader kernel arguments"
2068 The command-line arguments provided by the boot loader will be
2069 appended to the default kernel command string.
2071 config CMDLINE_FORCE
2072 bool "Always use the default kernel command string"
2074 Always use the default kernel command string, even if the boot
2075 loader passes other arguments to the kernel.
2076 This is useful if you cannot or don't want to change the
2077 command-line options your boot loader passes to the kernel.
2081 bool "Kernel Execute-In-Place from ROM"
2082 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2084 Execute-In-Place allows the kernel to run from non-volatile storage
2085 directly addressable by the CPU, such as NOR flash. This saves RAM
2086 space since the text section of the kernel is not loaded from flash
2087 to RAM. Read-write sections, such as the data section and stack,
2088 are still copied to RAM. The XIP kernel is not compressed since
2089 it has to run directly from flash, so it will take more space to
2090 store it. The flash address used to link the kernel object files,
2091 and for storing it, is configuration dependent. Therefore, if you
2092 say Y here, you must know the proper physical address where to
2093 store the kernel image depending on your own flash memory usage.
2095 Also note that the make target becomes "make xipImage" rather than
2096 "make zImage" or "make Image". The final kernel binary to put in
2097 ROM memory will be arch/arm/boot/xipImage.
2101 config XIP_PHYS_ADDR
2102 hex "XIP Kernel Physical Location"
2103 depends on XIP_KERNEL
2104 default "0x00080000"
2106 This is the physical address in your flash memory the kernel will
2107 be linked for and stored to. This address is dependent on your
2111 bool "Kexec system call (EXPERIMENTAL)"
2112 depends on (!SMP || HOTPLUG_CPU)
2114 kexec is a system call that implements the ability to shutdown your
2115 current kernel, and to start another kernel. It is like a reboot
2116 but it is independent of the system firmware. And like a reboot
2117 you can start any kernel with it, not just Linux.
2119 It is an ongoing process to be certain the hardware in a machine
2120 is properly shutdown, so do not be surprised if this code does not
2121 initially work for you. It may help to enable device hotplugging
2125 bool "Export atags in procfs"
2126 depends on ATAGS && KEXEC
2129 Should the atags used to boot the kernel be exported in an "atags"
2130 file in procfs. Useful with kexec.
2133 bool "Build kdump crash kernel (EXPERIMENTAL)"
2135 Generate crash dump after being started by kexec. This should
2136 be normally only set in special crash dump kernels which are
2137 loaded in the main kernel with kexec-tools into a specially
2138 reserved region and then later executed after a crash by
2139 kdump/kexec. The crash dump kernel must be compiled to a
2140 memory address not used by the main kernel
2142 For more details see Documentation/kdump/kdump.txt
2144 config AUTO_ZRELADDR
2145 bool "Auto calculation of the decompressed kernel image address"
2146 depends on !ZBOOT_ROM && !ARCH_U300
2148 ZRELADDR is the physical address where the decompressed kernel
2149 image will be placed. If AUTO_ZRELADDR is selected, the address
2150 will be determined at run-time by masking the current IP with
2151 0xf8000000. This assumes the zImage being placed in the first 128MB
2152 from start of memory.
2156 menu "CPU Power Management"
2159 source "drivers/cpufreq/Kconfig"
2164 Internal configuration node for common cpufreq on Samsung SoC
2166 config CPU_FREQ_S3C24XX
2167 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2168 depends on ARCH_S3C24XX && CPU_FREQ
2171 This enables the CPUfreq driver for the Samsung S3C24XX family
2174 For details, take a look at <file:Documentation/cpu-freq>.
2178 config CPU_FREQ_S3C24XX_PLL
2179 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2180 depends on CPU_FREQ_S3C24XX
2182 Compile in support for changing the PLL frequency from the
2183 S3C24XX series CPUfreq driver. The PLL takes time to settle
2184 after a frequency change, so by default it is not enabled.
2186 This also means that the PLL tables for the selected CPU(s) will
2187 be built which may increase the size of the kernel image.
2189 config CPU_FREQ_S3C24XX_DEBUG
2190 bool "Debug CPUfreq Samsung driver core"
2191 depends on CPU_FREQ_S3C24XX
2193 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2195 config CPU_FREQ_S3C24XX_IODEBUG
2196 bool "Debug CPUfreq Samsung driver IO timing"
2197 depends on CPU_FREQ_S3C24XX
2199 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2201 config CPU_FREQ_S3C24XX_DEBUGFS
2202 bool "Export debugfs for CPUFreq"
2203 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2205 Export status information via debugfs.
2209 source "drivers/cpuidle/Kconfig"
2213 menu "Floating point emulation"
2215 comment "At least one emulation must be selected"
2218 bool "NWFPE math emulation"
2219 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2221 Say Y to include the NWFPE floating point emulator in the kernel.
2222 This is necessary to run most binaries. Linux does not currently
2223 support floating point hardware so you need to say Y here even if
2224 your machine has an FPA or floating point co-processor podule.
2226 You may say N here if you are going to load the Acorn FPEmulator
2227 early in the bootup.
2230 bool "Support extended precision"
2231 depends on FPE_NWFPE
2233 Say Y to include 80-bit support in the kernel floating-point
2234 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2235 Note that gcc does not generate 80-bit operations by default,
2236 so in most cases this option only enlarges the size of the
2237 floating point emulator without any good reason.
2239 You almost surely want to say N here.
2242 bool "FastFPE math emulation (EXPERIMENTAL)"
2243 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2245 Say Y here to include the FAST floating point emulator in the kernel.
2246 This is an experimental much faster emulator which now also has full
2247 precision for the mantissa. It does not support any exceptions.
2248 It is very simple, and approximately 3-6 times faster than NWFPE.
2250 It should be sufficient for most programs. It may be not suitable
2251 for scientific calculations, but you have to check this for yourself.
2252 If you do not feel you need a faster FP emulation you should better
2256 bool "VFP-format floating point maths"
2257 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2259 Say Y to include VFP support code in the kernel. This is needed
2260 if your hardware includes a VFP unit.
2262 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2263 release notes and additional status information.
2265 Say N if your target does not have VFP hardware.
2273 bool "Advanced SIMD (NEON) Extension support"
2274 depends on VFPv3 && CPU_V7
2276 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2281 menu "Userspace binary formats"
2283 source "fs/Kconfig.binfmt"
2286 tristate "RISC OS personality"
2289 Say Y here to include the kernel code necessary if you want to run
2290 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2291 experimental; if this sounds frightening, say N and sleep in peace.
2292 You can also say M here to compile this support as a module (which
2293 will be called arthur).
2297 menu "Power management options"
2299 source "kernel/power/Kconfig"
2301 config ARCH_SUSPEND_POSSIBLE
2302 depends on !ARCH_S5PC100
2303 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2304 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2307 config ARM_CPU_SUSPEND
2312 source "net/Kconfig"
2314 source "drivers/Kconfig"
2318 source "arch/arm/Kconfig.debug"
2320 source "security/Kconfig"
2322 source "crypto/Kconfig"
2324 source "lib/Kconfig"
2326 source "arch/arm/kvm/Kconfig"