4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_USE_BUILTIN_BSWAP
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_WANT_IPC_PARSE_VERSION
13 select BUILDTIME_EXTABLE_SORT if MMU
14 select CLONE_BACKWARDS
15 select CPU_PM if (SUSPEND || CPU_IDLE)
16 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
17 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
18 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
19 select GENERIC_IDLE_POLL_SETUP
20 select GENERIC_IRQ_PROBE
21 select GENERIC_IRQ_SHOW
22 select GENERIC_PCI_IOMAP
23 select GENERIC_SCHED_CLOCK
24 select GENERIC_SMP_IDLE_THREAD
25 select GENERIC_STRNCPY_FROM_USER
26 select GENERIC_STRNLEN_USER
27 select HARDIRQS_SW_RESEND
28 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
29 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
31 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
32 select HAVE_ARCH_TRACEHOOK
34 select HAVE_CC_STACKPROTECTOR
35 select HAVE_CONTEXT_TRACKING
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_DEBUG_KMEMLEAK
38 select HAVE_DMA_API_DEBUG
40 select HAVE_DMA_CONTIGUOUS if MMU
41 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
42 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
43 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
44 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
45 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
46 select HAVE_GENERIC_DMA_COHERENT
47 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
48 select HAVE_IDE if PCI || ISA || PCMCIA
49 select HAVE_IRQ_TIME_ACCOUNTING
50 select HAVE_KERNEL_GZIP
51 select HAVE_KERNEL_LZ4
52 select HAVE_KERNEL_LZMA
53 select HAVE_KERNEL_LZO
55 select HAVE_KPROBES if !XIP_KERNEL
56 select HAVE_KRETPROBES if (HAVE_KPROBES)
58 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
59 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
60 select HAVE_PERF_EVENTS
62 select HAVE_PERF_USER_STACK_DUMP
63 select HAVE_REGS_AND_STACK_ACCESS_API
64 select HAVE_SYSCALL_TRACEPOINTS
66 select HAVE_VIRT_CPU_ACCOUNTING_GEN
67 select IRQ_FORCED_THREADING
68 select MODULES_USE_ELF_REL
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
86 select ARCH_HAS_SG_CHAIN
89 config NEED_SG_DMA_LENGTH
92 config ARM_DMA_USE_IOMMU
94 select ARM_HAS_SG_CHAIN
95 select NEED_SG_DMA_LENGTH
99 config ARM_DMA_IOMMU_ALIGNMENT
100 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
104 DMA mapping framework by default aligns all buffers to the smallest
105 PAGE_SIZE order which is greater than or equal to the requested buffer
106 size. This works well for buffers up to a few hundreds kilobytes, but
107 for larger buffers it just a waste of address space. Drivers which has
108 relatively small addressing window (like 64Mib) might run out of
109 virtual space with just a few allocations.
111 With this parameter you can specify the maximum PAGE_SIZE order for
112 DMA IOMMU buffers. Larger buffers will be aligned only to this
113 specified order. The order is expressed as a power of two multiplied
118 config MIGHT_HAVE_PCI
121 config SYS_SUPPORTS_APM_EMULATION
126 select GENERIC_ALLOCATOR
137 The Extended Industry Standard Architecture (EISA) bus was
138 developed as an open alternative to the IBM MicroChannel bus.
140 The EISA bus provided some of the features of the IBM MicroChannel
141 bus while maintaining backward compatibility with cards made for
142 the older ISA bus. The EISA bus saw limited use between 1988 and
143 1995 when it was made obsolete by the PCI bus.
145 Say Y here if you are building a kernel for an EISA-based machine.
152 config STACKTRACE_SUPPORT
156 config HAVE_LATENCYTOP_SUPPORT
161 config LOCKDEP_SUPPORT
165 config TRACE_IRQFLAGS_SUPPORT
169 config RWSEM_XCHGADD_ALGORITHM
173 config ARCH_HAS_ILOG2_U32
176 config ARCH_HAS_ILOG2_U64
179 config ARCH_HAS_BANDGAP
182 config GENERIC_HWEIGHT
186 config GENERIC_CALIBRATE_DELAY
190 config ARCH_MAY_HAVE_PC_FDC
196 config NEED_DMA_MAP_STATE
199 config ARCH_SUPPORTS_UPROBES
202 config ARCH_HAS_DMA_SET_COHERENT_MASK
205 config GENERIC_ISA_DMA
211 config NEED_RET_TO_USER
219 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
220 default DRAM_BASE if REMAP_VECTORS_TO_RAM
223 The base address of exception vectors. This must be two pages
226 config ARM_PATCH_PHYS_VIRT
227 bool "Patch physical to virtual translations at runtime" if EMBEDDED
229 depends on !XIP_KERNEL && MMU
230 depends on !ARCH_REALVIEW || !SPARSEMEM
232 Patch phys-to-virt and virt-to-phys translation functions at
233 boot and module load time according to the position of the
234 kernel in system memory.
236 This can only be used with non-XIP MMU kernels where the base
237 of physical memory is at a 16MB boundary.
239 Only disable this option if you know that you do not require
240 this feature (eg, building a kernel for a single machine) and
241 you need to shrink the kernel to the minimal size.
243 config NEED_MACH_IO_H
246 Select this when mach/io.h is required to provide special
247 definitions for this platform. The need for mach/io.h should
248 be avoided when possible.
250 config NEED_MACH_MEMORY_H
253 Select this when mach/memory.h is required to provide special
254 definitions for this platform. The need for mach/memory.h should
255 be avoided when possible.
258 hex "Physical address of main memory" if MMU
259 depends on !ARM_PATCH_PHYS_VIRT
260 default DRAM_BASE if !MMU
261 default 0x00000000 if ARCH_EBSA110 || \
262 EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
267 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
268 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
269 default 0x20000000 if ARCH_S5PV210
270 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
271 default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
272 default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
273 default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
274 default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
276 Please provide the physical address corresponding to the
277 location of main memory in your system.
283 source "init/Kconfig"
285 source "kernel/Kconfig.freezer"
290 bool "MMU-based Paged Memory Management Support"
293 Select if you want MMU-based virtualised addressing space
294 support by paged memory management. If unsure, say 'Y'.
297 # The "ARM system type" choice list is ordered alphabetically by option
298 # text. Please add new entries in the option alphabetic order.
301 prompt "ARM system type"
302 default ARCH_VERSATILE if !MMU
303 default ARCH_MULTIPLATFORM if MMU
305 config ARCH_MULTIPLATFORM
306 bool "Allow multiple platforms to be selected"
308 select ARCH_WANT_OPTIONAL_GPIOLIB
309 select ARM_HAS_SG_CHAIN
310 select ARM_PATCH_PHYS_VIRT
314 select GENERIC_CLOCKEVENTS
315 select MIGHT_HAVE_PCI
316 select MULTI_IRQ_HANDLER
320 config ARCH_INTEGRATOR
321 bool "ARM Ltd. Integrator family"
323 select ARM_PATCH_PHYS_VIRT if MMU
326 select COMMON_CLK_VERSATILE
327 select GENERIC_CLOCKEVENTS
330 select MULTI_IRQ_HANDLER
331 select PLAT_VERSATILE
334 select VERSATILE_FPGA_IRQ
336 Support for ARM's Integrator platform.
339 bool "ARM Ltd. RealView family"
340 select ARCH_WANT_OPTIONAL_GPIOLIB
342 select ARM_TIMER_SP804
344 select COMMON_CLK_VERSATILE
345 select GENERIC_CLOCKEVENTS
346 select GPIO_PL061 if GPIOLIB
348 select NEED_MACH_MEMORY_H
349 select PLAT_VERSATILE
351 This enables support for ARM Ltd RealView boards.
353 config ARCH_VERSATILE
354 bool "ARM Ltd. Versatile family"
355 select ARCH_WANT_OPTIONAL_GPIOLIB
357 select ARM_TIMER_SP804
360 select GENERIC_CLOCKEVENTS
361 select HAVE_MACH_CLKDEV
363 select PLAT_VERSATILE
364 select PLAT_VERSATILE_CLOCK
365 select VERSATILE_FPGA_IRQ
367 This enables support for ARM Ltd Versatile board.
371 select ARCH_REQUIRE_GPIOLIB
374 select NEED_MACH_IO_H if PCCARD
376 select PINCTRL_AT91 if USE_OF
378 This enables support for systems based on Atmel
379 AT91RM9200 and AT91SAM9* processors.
382 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
383 select ARCH_REQUIRE_GPIOLIB
388 select GENERIC_CLOCKEVENTS
392 Support for Cirrus Logic 711x/721x/731x based boards.
395 bool "Cortina Systems Gemini"
396 select ARCH_REQUIRE_GPIOLIB
399 select GENERIC_CLOCKEVENTS
401 Support for the Cortina Systems Gemini family SoCs
405 select ARCH_USES_GETTIMEOFFSET
408 select NEED_MACH_IO_H
409 select NEED_MACH_MEMORY_H
412 This is an evaluation board for the StrongARM processor available
413 from Digital. It has limited hardware on-board, including an
414 Ethernet interface, two PCMCIA sockets, two serial ports and a
418 bool "Energy Micro efm32"
420 select ARCH_REQUIRE_GPIOLIB
426 select GENERIC_CLOCKEVENTS
432 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
437 select ARCH_HAS_HOLES_MEMORYMODEL
438 select ARCH_REQUIRE_GPIOLIB
439 select ARCH_USES_GETTIMEOFFSET
445 This enables support for the Cirrus EP93xx series of CPUs.
447 config ARCH_FOOTBRIDGE
451 select GENERIC_CLOCKEVENTS
453 select NEED_MACH_IO_H if !MMU
454 select NEED_MACH_MEMORY_H
456 Support for systems based on the DC21285 companion chip
457 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
460 bool "Hilscher NetX based"
464 select GENERIC_CLOCKEVENTS
466 This enables support for systems based on the Hilscher NetX Soc
472 select NEED_MACH_MEMORY_H
473 select NEED_RET_TO_USER
479 Support for Intel's IOP13XX (XScale) family of processors.
484 select ARCH_REQUIRE_GPIOLIB
487 select NEED_RET_TO_USER
491 Support for Intel's 80219 and IOP32X (XScale) family of
497 select ARCH_REQUIRE_GPIOLIB
500 select NEED_RET_TO_USER
504 Support for Intel's IOP33X (XScale) family of processors.
509 select ARCH_HAS_DMA_SET_COHERENT_MASK
510 select ARCH_REQUIRE_GPIOLIB
511 select ARCH_SUPPORTS_BIG_ENDIAN
514 select DMABOUNCE if PCI
515 select GENERIC_CLOCKEVENTS
516 select MIGHT_HAVE_PCI
517 select NEED_MACH_IO_H
518 select USB_EHCI_BIG_ENDIAN_DESC
519 select USB_EHCI_BIG_ENDIAN_MMIO
521 Support for Intel's IXP4XX (XScale) family of processors.
525 select ARCH_REQUIRE_GPIOLIB
527 select GENERIC_CLOCKEVENTS
528 select MIGHT_HAVE_PCI
532 select PLAT_ORION_LEGACY
534 Support for the Marvell Dove SoC 88AP510
537 bool "Marvell MV78xx0"
538 select ARCH_REQUIRE_GPIOLIB
540 select GENERIC_CLOCKEVENTS
543 select PLAT_ORION_LEGACY
545 Support for the following Marvell MV78xx0 series SoCs:
551 select ARCH_REQUIRE_GPIOLIB
553 select GENERIC_CLOCKEVENTS
556 select PLAT_ORION_LEGACY
558 Support for the following Marvell Orion 5x series SoCs:
559 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
560 Orion-2 (5281), Orion-1-90 (6183).
563 bool "Marvell PXA168/910/MMP2"
565 select ARCH_REQUIRE_GPIOLIB
567 select GENERIC_ALLOCATOR
568 select GENERIC_CLOCKEVENTS
571 select MULTI_IRQ_HANDLER
576 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
579 bool "Micrel/Kendin KS8695"
580 select ARCH_REQUIRE_GPIOLIB
583 select GENERIC_CLOCKEVENTS
584 select NEED_MACH_MEMORY_H
586 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
587 System-on-Chip devices.
590 bool "Nuvoton W90X900 CPU"
591 select ARCH_REQUIRE_GPIOLIB
595 select GENERIC_CLOCKEVENTS
597 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
598 At present, the w90x900 has been renamed nuc900, regarding
599 the ARM series product line, you can login the following
600 link address to know more.
602 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
603 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
607 select ARCH_REQUIRE_GPIOLIB
612 select GENERIC_CLOCKEVENTS
616 Support for the NXP LPC32XX family of processors
619 bool "PXA2xx/PXA3xx-based"
622 select ARCH_REQUIRE_GPIOLIB
623 select ARM_CPU_SUSPEND if PM
628 select GENERIC_CLOCKEVENTS
631 select MULTI_IRQ_HANDLER
635 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
638 bool "Qualcomm MSM (non-multiplatform)"
639 select ARCH_REQUIRE_GPIOLIB
641 select GENERIC_CLOCKEVENTS
643 Support for Qualcomm MSM/QSD based systems. This runs on the
644 apps processor of the MSM/QSD and depends on a shared memory
645 interface to the modem processor which runs the baseband
646 stack and controls some vital subsystems
647 (clock and power control, etc).
649 config ARCH_SHMOBILE_LEGACY
650 bool "Renesas ARM SoCs (non-multiplatform)"
652 select ARM_PATCH_PHYS_VIRT if MMU
655 select GENERIC_CLOCKEVENTS
656 select HAVE_ARM_SCU if SMP
657 select HAVE_ARM_TWD if SMP
658 select HAVE_MACH_CLKDEV
660 select MIGHT_HAVE_CACHE_L2X0
661 select MULTI_IRQ_HANDLER
664 select PM_GENERIC_DOMAINS if PM
668 Support for Renesas ARM SoC platforms using a non-multiplatform
669 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
675 select ARCH_MAY_HAVE_PC_FDC
676 select ARCH_SPARSEMEM_ENABLE
677 select ARCH_USES_GETTIMEOFFSET
681 select HAVE_PATA_PLATFORM
683 select NEED_MACH_IO_H
684 select NEED_MACH_MEMORY_H
688 On the Acorn Risc-PC, Linux can support the internal IDE disk and
689 CD-ROM interface, serial and parallel port, and the floppy drive.
694 select ARCH_REQUIRE_GPIOLIB
695 select ARCH_SPARSEMEM_ENABLE
700 select GENERIC_CLOCKEVENTS
703 select NEED_MACH_MEMORY_H
706 Support for StrongARM 11x0 based boards.
709 bool "Samsung S3C24XX SoCs"
710 select ARCH_REQUIRE_GPIOLIB
713 select CLKSRC_SAMSUNG_PWM
714 select GENERIC_CLOCKEVENTS
716 select HAVE_S3C2410_I2C if I2C
717 select HAVE_S3C2410_WATCHDOG if WATCHDOG
718 select HAVE_S3C_RTC if RTC_CLASS
719 select MULTI_IRQ_HANDLER
720 select NEED_MACH_IO_H
723 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
724 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
725 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
726 Samsung SMDK2410 development board (and derivatives).
729 bool "Samsung S3C64XX"
730 select ARCH_REQUIRE_GPIOLIB
735 select CLKSRC_SAMSUNG_PWM
736 select COMMON_CLK_SAMSUNG
738 select GENERIC_CLOCKEVENTS
740 select HAVE_S3C2410_I2C if I2C
741 select HAVE_S3C2410_WATCHDOG if WATCHDOG
745 select PM_GENERIC_DOMAINS if PM
747 select S3C_GPIO_TRACK
749 select SAMSUNG_WAKEMASK
750 select SAMSUNG_WDT_RESET
752 Samsung S3C64XX series based systems
756 select ARCH_HAS_HOLES_MEMORYMODEL
757 select ARCH_REQUIRE_GPIOLIB
759 select GENERIC_ALLOCATOR
760 select GENERIC_CLOCKEVENTS
761 select GENERIC_IRQ_CHIP
767 Support for TI's DaVinci platform.
772 select ARCH_HAS_HOLES_MEMORYMODEL
774 select ARCH_REQUIRE_GPIOLIB
777 select GENERIC_CLOCKEVENTS
778 select GENERIC_IRQ_CHIP
781 select NEED_MACH_IO_H if PCCARD
782 select NEED_MACH_MEMORY_H
784 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
788 menu "Multiple platform selection"
789 depends on ARCH_MULTIPLATFORM
791 comment "CPU Core family selection"
794 bool "ARMv4 based platforms (FA526)"
795 depends on !ARCH_MULTI_V6_V7
796 select ARCH_MULTI_V4_V5
799 config ARCH_MULTI_V4T
800 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
801 depends on !ARCH_MULTI_V6_V7
802 select ARCH_MULTI_V4_V5
803 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
804 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
805 CPU_ARM925T || CPU_ARM940T)
808 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
809 depends on !ARCH_MULTI_V6_V7
810 select ARCH_MULTI_V4_V5
811 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
812 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
813 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
815 config ARCH_MULTI_V4_V5
819 bool "ARMv6 based platforms (ARM11)"
820 select ARCH_MULTI_V6_V7
824 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
826 select ARCH_MULTI_V6_V7
830 config ARCH_MULTI_V6_V7
832 select MIGHT_HAVE_CACHE_L2X0
834 config ARCH_MULTI_CPU_AUTO
835 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
841 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
845 select HAVE_ARM_ARCH_TIMER
848 # This is sorted alphabetically by mach-* pathname. However, plat-*
849 # Kconfigs may be included either alphabetically (according to the
850 # plat- suffix) or along side the corresponding mach-* source.
852 source "arch/arm/mach-mvebu/Kconfig"
854 source "arch/arm/mach-at91/Kconfig"
856 source "arch/arm/mach-axxia/Kconfig"
858 source "arch/arm/mach-bcm/Kconfig"
860 source "arch/arm/mach-berlin/Kconfig"
862 source "arch/arm/mach-clps711x/Kconfig"
864 source "arch/arm/mach-cns3xxx/Kconfig"
866 source "arch/arm/mach-davinci/Kconfig"
868 source "arch/arm/mach-dove/Kconfig"
870 source "arch/arm/mach-ep93xx/Kconfig"
872 source "arch/arm/mach-footbridge/Kconfig"
874 source "arch/arm/mach-gemini/Kconfig"
876 source "arch/arm/mach-highbank/Kconfig"
878 source "arch/arm/mach-hisi/Kconfig"
880 source "arch/arm/mach-integrator/Kconfig"
882 source "arch/arm/mach-iop32x/Kconfig"
884 source "arch/arm/mach-iop33x/Kconfig"
886 source "arch/arm/mach-iop13xx/Kconfig"
888 source "arch/arm/mach-ixp4xx/Kconfig"
890 source "arch/arm/mach-keystone/Kconfig"
892 source "arch/arm/mach-ks8695/Kconfig"
894 source "arch/arm/mach-meson/Kconfig"
896 source "arch/arm/mach-msm/Kconfig"
898 source "arch/arm/mach-moxart/Kconfig"
900 source "arch/arm/mach-mv78xx0/Kconfig"
902 source "arch/arm/mach-imx/Kconfig"
904 source "arch/arm/mach-mediatek/Kconfig"
906 source "arch/arm/mach-mxs/Kconfig"
908 source "arch/arm/mach-netx/Kconfig"
910 source "arch/arm/mach-nomadik/Kconfig"
912 source "arch/arm/mach-nspire/Kconfig"
914 source "arch/arm/plat-omap/Kconfig"
916 source "arch/arm/mach-omap1/Kconfig"
918 source "arch/arm/mach-omap2/Kconfig"
920 source "arch/arm/mach-orion5x/Kconfig"
922 source "arch/arm/mach-picoxcell/Kconfig"
924 source "arch/arm/mach-pxa/Kconfig"
925 source "arch/arm/plat-pxa/Kconfig"
927 source "arch/arm/mach-mmp/Kconfig"
929 source "arch/arm/mach-qcom/Kconfig"
931 source "arch/arm/mach-realview/Kconfig"
933 source "arch/arm/mach-rockchip/Kconfig"
935 source "arch/arm/mach-sa1100/Kconfig"
937 source "arch/arm/mach-socfpga/Kconfig"
939 source "arch/arm/mach-spear/Kconfig"
941 source "arch/arm/mach-sti/Kconfig"
943 source "arch/arm/mach-s3c24xx/Kconfig"
945 source "arch/arm/mach-s3c64xx/Kconfig"
947 source "arch/arm/mach-s5pv210/Kconfig"
949 source "arch/arm/mach-exynos/Kconfig"
950 source "arch/arm/plat-samsung/Kconfig"
952 source "arch/arm/mach-shmobile/Kconfig"
954 source "arch/arm/mach-sunxi/Kconfig"
956 source "arch/arm/mach-prima2/Kconfig"
958 source "arch/arm/mach-tegra/Kconfig"
960 source "arch/arm/mach-u300/Kconfig"
962 source "arch/arm/mach-ux500/Kconfig"
964 source "arch/arm/mach-versatile/Kconfig"
966 source "arch/arm/mach-vexpress/Kconfig"
967 source "arch/arm/plat-versatile/Kconfig"
969 source "arch/arm/mach-vt8500/Kconfig"
971 source "arch/arm/mach-w90x900/Kconfig"
973 source "arch/arm/mach-zynq/Kconfig"
975 # Definitions to make life easier
981 select GENERIC_CLOCKEVENTS
987 select GENERIC_IRQ_CHIP
990 config PLAT_ORION_LEGACY
997 config PLAT_VERSATILE
1000 config ARM_TIMER_SP804
1003 select CLKSRC_OF if OF
1005 source "arch/arm/firmware/Kconfig"
1007 source arch/arm/mm/Kconfig
1010 bool "Enable iWMMXt support"
1011 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1012 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1014 Enable support for iWMMXt context switching at run time if
1015 running on a CPU that supports it.
1017 config MULTI_IRQ_HANDLER
1020 Allow each machine to specify it's own IRQ handler at run time.
1023 source "arch/arm/Kconfig-nommu"
1026 config PJ4B_ERRATA_4742
1027 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1028 depends on CPU_PJ4B && MACH_ARMADA_370
1031 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1032 Event (WFE) IDLE states, a specific timing sensitivity exists between
1033 the retiring WFI/WFE instructions and the newly issued subsequent
1034 instructions. This sensitivity can result in a CPU hang scenario.
1036 The software must insert either a Data Synchronization Barrier (DSB)
1037 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1040 config ARM_ERRATA_326103
1041 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1044 Executing a SWP instruction to read-only memory does not set bit 11
1045 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1046 treat the access as a read, preventing a COW from occurring and
1047 causing the faulting task to livelock.
1049 config ARM_ERRATA_411920
1050 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1051 depends on CPU_V6 || CPU_V6K
1053 Invalidation of the Instruction Cache operation can
1054 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1055 It does not affect the MPCore. This option enables the ARM Ltd.
1056 recommended workaround.
1058 config ARM_ERRATA_430973
1059 bool "ARM errata: Stale prediction on replaced interworking branch"
1062 This option enables the workaround for the 430973 Cortex-A8
1063 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1064 interworking branch is replaced with another code sequence at the
1065 same virtual address, whether due to self-modifying code or virtual
1066 to physical address re-mapping, Cortex-A8 does not recover from the
1067 stale interworking branch prediction. This results in Cortex-A8
1068 executing the new code sequence in the incorrect ARM or Thumb state.
1069 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1070 and also flushes the branch target cache at every context switch.
1071 Note that setting specific bits in the ACTLR register may not be
1072 available in non-secure mode.
1074 config ARM_ERRATA_458693
1075 bool "ARM errata: Processor deadlock when a false hazard is created"
1077 depends on !ARCH_MULTIPLATFORM
1079 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1080 erratum. For very specific sequences of memory operations, it is
1081 possible for a hazard condition intended for a cache line to instead
1082 be incorrectly associated with a different cache line. This false
1083 hazard might then cause a processor deadlock. The workaround enables
1084 the L1 caching of the NEON accesses and disables the PLD instruction
1085 in the ACTLR register. Note that setting specific bits in the ACTLR
1086 register may not be available in non-secure mode.
1088 config ARM_ERRATA_460075
1089 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1091 depends on !ARCH_MULTIPLATFORM
1093 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1094 erratum. Any asynchronous access to the L2 cache may encounter a
1095 situation in which recent store transactions to the L2 cache are lost
1096 and overwritten with stale memory contents from external memory. The
1097 workaround disables the write-allocate mode for the L2 cache via the
1098 ACTLR register. Note that setting specific bits in the ACTLR register
1099 may not be available in non-secure mode.
1101 config ARM_ERRATA_742230
1102 bool "ARM errata: DMB operation may be faulty"
1103 depends on CPU_V7 && SMP
1104 depends on !ARCH_MULTIPLATFORM
1106 This option enables the workaround for the 742230 Cortex-A9
1107 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1108 between two write operations may not ensure the correct visibility
1109 ordering of the two writes. This workaround sets a specific bit in
1110 the diagnostic register of the Cortex-A9 which causes the DMB
1111 instruction to behave as a DSB, ensuring the correct behaviour of
1114 config ARM_ERRATA_742231
1115 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1116 depends on CPU_V7 && SMP
1117 depends on !ARCH_MULTIPLATFORM
1119 This option enables the workaround for the 742231 Cortex-A9
1120 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1121 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1122 accessing some data located in the same cache line, may get corrupted
1123 data due to bad handling of the address hazard when the line gets
1124 replaced from one of the CPUs at the same time as another CPU is
1125 accessing it. This workaround sets specific bits in the diagnostic
1126 register of the Cortex-A9 which reduces the linefill issuing
1127 capabilities of the processor.
1129 config ARM_ERRATA_643719
1130 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1131 depends on CPU_V7 && SMP
1133 This option enables the workaround for the 643719 Cortex-A9 (prior to
1134 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1135 register returns zero when it should return one. The workaround
1136 corrects this value, ensuring cache maintenance operations which use
1137 it behave as intended and avoiding data corruption.
1139 config ARM_ERRATA_720789
1140 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1143 This option enables the workaround for the 720789 Cortex-A9 (prior to
1144 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1145 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1146 As a consequence of this erratum, some TLB entries which should be
1147 invalidated are not, resulting in an incoherency in the system page
1148 tables. The workaround changes the TLB flushing routines to invalidate
1149 entries regardless of the ASID.
1151 config ARM_ERRATA_743622
1152 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1154 depends on !ARCH_MULTIPLATFORM
1156 This option enables the workaround for the 743622 Cortex-A9
1157 (r2p*) erratum. Under very rare conditions, a faulty
1158 optimisation in the Cortex-A9 Store Buffer may lead to data
1159 corruption. This workaround sets a specific bit in the diagnostic
1160 register of the Cortex-A9 which disables the Store Buffer
1161 optimisation, preventing the defect from occurring. This has no
1162 visible impact on the overall performance or power consumption of the
1165 config ARM_ERRATA_751472
1166 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1168 depends on !ARCH_MULTIPLATFORM
1170 This option enables the workaround for the 751472 Cortex-A9 (prior
1171 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1172 completion of a following broadcasted operation if the second
1173 operation is received by a CPU before the ICIALLUIS has completed,
1174 potentially leading to corrupted entries in the cache or TLB.
1176 config ARM_ERRATA_754322
1177 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1180 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1181 r3p*) erratum. A speculative memory access may cause a page table walk
1182 which starts prior to an ASID switch but completes afterwards. This
1183 can populate the micro-TLB with a stale entry which may be hit with
1184 the new ASID. This workaround places two dsb instructions in the mm
1185 switching code so that no page table walks can cross the ASID switch.
1187 config ARM_ERRATA_754327
1188 bool "ARM errata: no automatic Store Buffer drain"
1189 depends on CPU_V7 && SMP
1191 This option enables the workaround for the 754327 Cortex-A9 (prior to
1192 r2p0) erratum. The Store Buffer does not have any automatic draining
1193 mechanism and therefore a livelock may occur if an external agent
1194 continuously polls a memory location waiting to observe an update.
1195 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1196 written polling loops from denying visibility of updates to memory.
1198 config ARM_ERRATA_364296
1199 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1202 This options enables the workaround for the 364296 ARM1136
1203 r0p2 erratum (possible cache data corruption with
1204 hit-under-miss enabled). It sets the undocumented bit 31 in
1205 the auxiliary control register and the FI bit in the control
1206 register, thus disabling hit-under-miss without putting the
1207 processor into full low interrupt latency mode. ARM11MPCore
1210 config ARM_ERRATA_764369
1211 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1212 depends on CPU_V7 && SMP
1214 This option enables the workaround for erratum 764369
1215 affecting Cortex-A9 MPCore with two or more processors (all
1216 current revisions). Under certain timing circumstances, a data
1217 cache line maintenance operation by MVA targeting an Inner
1218 Shareable memory region may fail to proceed up to either the
1219 Point of Coherency or to the Point of Unification of the
1220 system. This workaround adds a DSB instruction before the
1221 relevant cache maintenance functions and sets a specific bit
1222 in the diagnostic control register of the SCU.
1224 config ARM_ERRATA_775420
1225 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1228 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1229 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1230 operation aborts with MMU exception, it might cause the processor
1231 to deadlock. This workaround puts DSB before executing ISB if
1232 an abort may occur on cache maintenance.
1234 config ARM_ERRATA_798181
1235 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1236 depends on CPU_V7 && SMP
1238 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1239 adequately shooting down all use of the old entries. This
1240 option enables the Linux kernel workaround for this erratum
1241 which sends an IPI to the CPUs that are running the same ASID
1242 as the one being invalidated.
1244 config ARM_ERRATA_773022
1245 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1248 This option enables the workaround for the 773022 Cortex-A15
1249 (up to r0p4) erratum. In certain rare sequences of code, the
1250 loop buffer may deliver incorrect instructions. This
1251 workaround disables the loop buffer to avoid the erratum.
1255 source "arch/arm/common/Kconfig"
1265 Find out whether you have ISA slots on your motherboard. ISA is the
1266 name of a bus system, i.e. the way the CPU talks to the other stuff
1267 inside your box. Other bus systems are PCI, EISA, MicroChannel
1268 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1269 newer boards don't support it. If you have ISA, say Y, otherwise N.
1271 # Select ISA DMA controller support
1276 # Select ISA DMA interface
1281 bool "PCI support" if MIGHT_HAVE_PCI
1283 Find out whether you have a PCI motherboard. PCI is the name of a
1284 bus system, i.e. the way the CPU talks to the other stuff inside
1285 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1286 VESA. If you have PCI, say Y, otherwise N.
1292 config PCI_NANOENGINE
1293 bool "BSE nanoEngine PCI support"
1294 depends on SA1100_NANOENGINE
1296 Enable PCI on the BSE nanoEngine board.
1301 config PCI_HOST_ITE8152
1303 depends on PCI && MACH_ARMCORE
1307 source "drivers/pci/Kconfig"
1308 source "drivers/pci/pcie/Kconfig"
1310 source "drivers/pcmcia/Kconfig"
1314 menu "Kernel Features"
1319 This option should be selected by machines which have an SMP-
1322 The only effect of this option is to make the SMP-related
1323 options available to the user for configuration.
1326 bool "Symmetric Multi-Processing"
1327 depends on CPU_V6K || CPU_V7
1328 depends on GENERIC_CLOCKEVENTS
1330 depends on MMU || ARM_MPU
1332 This enables support for systems with more than one CPU. If you have
1333 a system with only one CPU, say N. If you have a system with more
1334 than one CPU, say Y.
1336 If you say N here, the kernel will run on uni- and multiprocessor
1337 machines, but will use only one CPU of a multiprocessor machine. If
1338 you say Y here, the kernel will run on many, but not all,
1339 uniprocessor machines. On a uniprocessor machine, the kernel
1340 will run faster if you say N here.
1342 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1343 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1344 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1346 If you don't know what to do here, say N.
1349 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1350 depends on SMP && !XIP_KERNEL && MMU
1353 SMP kernels contain instructions which fail on non-SMP processors.
1354 Enabling this option allows the kernel to modify itself to make
1355 these instructions safe. Disabling it allows about 1K of space
1358 If you don't know what to do here, say Y.
1360 config ARM_CPU_TOPOLOGY
1361 bool "Support cpu topology definition"
1362 depends on SMP && CPU_V7
1365 Support ARM cpu topology definition. The MPIDR register defines
1366 affinity between processors which is then used to describe the cpu
1367 topology of an ARM System.
1370 bool "Multi-core scheduler support"
1371 depends on ARM_CPU_TOPOLOGY
1373 Multi-core scheduler support improves the CPU scheduler's decision
1374 making when dealing with multi-core CPU chips at a cost of slightly
1375 increased overhead in some places. If unsure say N here.
1378 bool "SMT scheduler support"
1379 depends on ARM_CPU_TOPOLOGY
1381 Improves the CPU scheduler's decision making when dealing with
1382 MultiThreading at a cost of slightly increased overhead in some
1383 places. If unsure say N here.
1388 This option enables support for the ARM system coherency unit
1390 config HAVE_ARM_ARCH_TIMER
1391 bool "Architected timer support"
1393 select ARM_ARCH_TIMER
1394 select GENERIC_CLOCKEVENTS
1396 This option enables support for the ARM architected timer
1401 select CLKSRC_OF if OF
1403 This options enables support for the ARM timer and watchdog unit
1406 bool "Multi-Cluster Power Management"
1407 depends on CPU_V7 && SMP
1409 This option provides the common power management infrastructure
1410 for (multi-)cluster based systems, such as big.LITTLE based
1413 config MCPM_QUAD_CLUSTER
1417 To avoid wasting resources unnecessarily, MCPM only supports up
1418 to 2 clusters by default.
1419 Platforms with 3 or 4 clusters that use MCPM must select this
1420 option to allow the additional clusters to be managed.
1423 bool "big.LITTLE support (Experimental)"
1424 depends on CPU_V7 && SMP
1427 This option enables support selections for the big.LITTLE
1428 system architecture.
1431 bool "big.LITTLE switcher support"
1432 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1433 select ARM_CPU_SUSPEND
1436 The big.LITTLE "switcher" provides the core functionality to
1437 transparently handle transition between a cluster of A15's
1438 and a cluster of A7's in a big.LITTLE system.
1440 config BL_SWITCHER_DUMMY_IF
1441 tristate "Simple big.LITTLE switcher user interface"
1442 depends on BL_SWITCHER && DEBUG_KERNEL
1444 This is a simple and dummy char dev interface to control
1445 the big.LITTLE switcher core code. It is meant for
1446 debugging purposes only.
1449 prompt "Memory split"
1453 Select the desired split between kernel and user memory.
1455 If you are not absolutely sure what you are doing, leave this
1459 bool "3G/1G user/kernel split"
1461 bool "2G/2G user/kernel split"
1463 bool "1G/3G user/kernel split"
1468 default PHYS_OFFSET if !MMU
1469 default 0x40000000 if VMSPLIT_1G
1470 default 0x80000000 if VMSPLIT_2G
1474 int "Maximum number of CPUs (2-32)"
1480 bool "Support for hot-pluggable CPUs"
1483 Say Y here to experiment with turning CPUs off and on. CPUs
1484 can be controlled through /sys/devices/system/cpu.
1487 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1490 Say Y here if you want Linux to communicate with system firmware
1491 implementing the PSCI specification for CPU-centric power
1492 management operations described in ARM document number ARM DEN
1493 0022A ("Power State Coordination Interface System Software on
1496 # The GPIO number here must be sorted by descending number. In case of
1497 # a multiplatform kernel, we just want the highest value required by the
1498 # selected platforms.
1501 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1502 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1503 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1504 default 416 if ARCH_SUNXI
1505 default 392 if ARCH_U8500
1506 default 352 if ARCH_VT8500
1507 default 288 if ARCH_ROCKCHIP
1508 default 264 if MACH_H4700
1511 Maximum number of GPIOs in the system.
1513 If unsure, leave the default value.
1515 source kernel/Kconfig.preempt
1519 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1520 ARCH_S5PV210 || ARCH_EXYNOS4
1521 default AT91_TIMER_HZ if ARCH_AT91
1522 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1526 depends on HZ_FIXED = 0
1527 prompt "Timer frequency"
1551 default HZ_FIXED if HZ_FIXED != 0
1552 default 100 if HZ_100
1553 default 200 if HZ_200
1554 default 250 if HZ_250
1555 default 300 if HZ_300
1556 default 500 if HZ_500
1560 def_bool HIGH_RES_TIMERS
1562 config THUMB2_KERNEL
1563 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1564 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1565 default y if CPU_THUMBONLY
1567 select ARM_ASM_UNIFIED
1570 By enabling this option, the kernel will be compiled in
1571 Thumb-2 mode. A compiler/assembler that understand the unified
1572 ARM-Thumb syntax is needed.
1576 config THUMB2_AVOID_R_ARM_THM_JUMP11
1577 bool "Work around buggy Thumb-2 short branch relocations in gas"
1578 depends on THUMB2_KERNEL && MODULES
1581 Various binutils versions can resolve Thumb-2 branches to
1582 locally-defined, preemptible global symbols as short-range "b.n"
1583 branch instructions.
1585 This is a problem, because there's no guarantee the final
1586 destination of the symbol, or any candidate locations for a
1587 trampoline, are within range of the branch. For this reason, the
1588 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1589 relocation in modules at all, and it makes little sense to add
1592 The symptom is that the kernel fails with an "unsupported
1593 relocation" error when loading some modules.
1595 Until fixed tools are available, passing
1596 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1597 code which hits this problem, at the cost of a bit of extra runtime
1598 stack usage in some cases.
1600 The problem is described in more detail at:
1601 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1603 Only Thumb-2 kernels are affected.
1605 Unless you are sure your tools don't have this problem, say Y.
1607 config ARM_ASM_UNIFIED
1611 bool "Use the ARM EABI to compile the kernel"
1613 This option allows for the kernel to be compiled using the latest
1614 ARM ABI (aka EABI). This is only useful if you are using a user
1615 space environment that is also compiled with EABI.
1617 Since there are major incompatibilities between the legacy ABI and
1618 EABI, especially with regard to structure member alignment, this
1619 option also changes the kernel syscall calling convention to
1620 disambiguate both ABIs and allow for backward compatibility support
1621 (selected with CONFIG_OABI_COMPAT).
1623 To use this you need GCC version 4.0.0 or later.
1626 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1627 depends on AEABI && !THUMB2_KERNEL
1629 This option preserves the old syscall interface along with the
1630 new (ARM EABI) one. It also provides a compatibility layer to
1631 intercept syscalls that have structure arguments which layout
1632 in memory differs between the legacy ABI and the new ARM EABI
1633 (only for non "thumb" binaries). This option adds a tiny
1634 overhead to all syscalls and produces a slightly larger kernel.
1636 The seccomp filter system will not be available when this is
1637 selected, since there is no way yet to sensibly distinguish
1638 between calling conventions during filtering.
1640 If you know you'll be using only pure EABI user space then you
1641 can say N here. If this option is not selected and you attempt
1642 to execute a legacy ABI binary then the result will be
1643 UNPREDICTABLE (in fact it can be predicted that it won't work
1644 at all). If in doubt say N.
1646 config ARCH_HAS_HOLES_MEMORYMODEL
1649 config ARCH_SPARSEMEM_ENABLE
1652 config ARCH_SPARSEMEM_DEFAULT
1653 def_bool ARCH_SPARSEMEM_ENABLE
1655 config ARCH_SELECT_MEMORY_MODEL
1656 def_bool ARCH_SPARSEMEM_ENABLE
1658 config HAVE_ARCH_PFN_VALID
1659 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1662 bool "High Memory Support"
1665 The address space of ARM processors is only 4 Gigabytes large
1666 and it has to accommodate user address space, kernel address
1667 space as well as some memory mapped IO. That means that, if you
1668 have a large amount of physical memory and/or IO, not all of the
1669 memory can be "permanently mapped" by the kernel. The physical
1670 memory that is not permanently mapped is called "high memory".
1672 Depending on the selected kernel/user memory split, minimum
1673 vmalloc space and actual amount of RAM, you may not need this
1674 option which should result in a slightly faster kernel.
1679 bool "Allocate 2nd-level pagetables from highmem"
1682 config HW_PERF_EVENTS
1683 bool "Enable hardware performance counter support for perf events"
1684 depends on PERF_EVENTS
1687 Enable hardware performance counter support for perf events. If
1688 disabled, perf events will use software events only.
1690 config SYS_SUPPORTS_HUGETLBFS
1694 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1698 config ARCH_WANT_GENERAL_HUGETLB
1703 config FORCE_MAX_ZONEORDER
1704 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1705 range 11 64 if ARCH_SHMOBILE_LEGACY
1706 default "12" if SOC_AM33XX
1707 default "9" if SA1111 || ARCH_EFM32
1710 The kernel memory allocator divides physically contiguous memory
1711 blocks into "zones", where each zone is a power of two number of
1712 pages. This option selects the largest power of two that the kernel
1713 keeps in the memory allocator. If you need to allocate very large
1714 blocks of physically contiguous memory, then you may need to
1715 increase this value.
1717 This config option is actually maximum order plus one. For example,
1718 a value of 11 means that the largest free memory block is 2^10 pages.
1720 config ALIGNMENT_TRAP
1722 depends on CPU_CP15_MMU
1723 default y if !ARCH_EBSA110
1724 select HAVE_PROC_CPU if PROC_FS
1726 ARM processors cannot fetch/store information which is not
1727 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1728 address divisible by 4. On 32-bit ARM processors, these non-aligned
1729 fetch/store instructions will be emulated in software if you say
1730 here, which has a severe performance impact. This is necessary for
1731 correct operation of some network protocols. With an IP-only
1732 configuration it is safe to say N, otherwise say Y.
1734 config UACCESS_WITH_MEMCPY
1735 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1737 default y if CPU_FEROCEON
1739 Implement faster copy_to_user and clear_user methods for CPU
1740 cores where a 8-word STM instruction give significantly higher
1741 memory write throughput than a sequence of individual 32bit stores.
1743 A possible side effect is a slight increase in scheduling latency
1744 between threads sharing the same address space if they invoke
1745 such copy operations with large buffers.
1747 However, if the CPU data cache is using a write-allocate mode,
1748 this option is unlikely to provide any performance gain.
1752 prompt "Enable seccomp to safely compute untrusted bytecode"
1754 This kernel feature is useful for number crunching applications
1755 that may need to compute untrusted bytecode during their
1756 execution. By using pipes or other transports made available to
1757 the process as file descriptors supporting the read/write
1758 syscalls, it's possible to isolate those applications in
1759 their own address space using seccomp. Once seccomp is
1760 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1761 and the task is only allowed to execute a few safe syscalls
1762 defined by each seccomp mode.
1775 bool "Xen guest support on ARM (EXPERIMENTAL)"
1776 depends on ARM && AEABI && OF
1777 depends on CPU_V7 && !CPU_V6
1778 depends on !GENERIC_ATOMIC64
1780 select ARCH_DMA_ADDR_T_64BIT
1784 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1791 bool "Flattened Device Tree support"
1794 select OF_EARLY_FLATTREE
1795 select OF_RESERVED_MEM
1797 Include support for flattened device tree machine descriptions.
1800 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1803 This is the traditional way of passing data to the kernel at boot
1804 time. If you are solely relying on the flattened device tree (or
1805 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1806 to remove ATAGS support from your kernel binary. If unsure,
1809 config DEPRECATED_PARAM_STRUCT
1810 bool "Provide old way to pass kernel parameters"
1813 This was deprecated in 2001 and announced to live on for 5 years.
1814 Some old boot loaders still use this way.
1816 # Compressed boot loader in ROM. Yes, we really want to ask about
1817 # TEXT and BSS so we preserve their values in the config files.
1818 config ZBOOT_ROM_TEXT
1819 hex "Compressed ROM boot loader base address"
1822 The physical address at which the ROM-able zImage is to be
1823 placed in the target. Platforms which normally make use of
1824 ROM-able zImage formats normally set this to a suitable
1825 value in their defconfig file.
1827 If ZBOOT_ROM is not enabled, this has no effect.
1829 config ZBOOT_ROM_BSS
1830 hex "Compressed ROM boot loader BSS address"
1833 The base address of an area of read/write memory in the target
1834 for the ROM-able zImage which must be available while the
1835 decompressor is running. It must be large enough to hold the
1836 entire decompressed kernel plus an additional 128 KiB.
1837 Platforms which normally make use of ROM-able zImage formats
1838 normally set this to a suitable value in their defconfig file.
1840 If ZBOOT_ROM is not enabled, this has no effect.
1843 bool "Compressed boot loader in ROM/flash"
1844 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1845 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1847 Say Y here if you intend to execute your compressed kernel image
1848 (zImage) directly from ROM or flash. If unsure, say N.
1851 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1852 depends on ZBOOT_ROM && ARCH_SH7372
1853 default ZBOOT_ROM_NONE
1855 Include experimental SD/MMC loading code in the ROM-able zImage.
1856 With this enabled it is possible to write the ROM-able zImage
1857 kernel image to an MMC or SD card and boot the kernel straight
1858 from the reset vector. At reset the processor Mask ROM will load
1859 the first part of the ROM-able zImage which in turn loads the
1860 rest the kernel image to RAM.
1862 config ZBOOT_ROM_NONE
1863 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1865 Do not load image from SD or MMC
1867 config ZBOOT_ROM_MMCIF
1868 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1870 Load image from MMCIF hardware block.
1872 config ZBOOT_ROM_SH_MOBILE_SDHI
1873 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1875 Load image from SDHI hardware block
1879 config ARM_APPENDED_DTB
1880 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1883 With this option, the boot code will look for a device tree binary
1884 (DTB) appended to zImage
1885 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1887 This is meant as a backward compatibility convenience for those
1888 systems with a bootloader that can't be upgraded to accommodate
1889 the documented boot protocol using a device tree.
1891 Beware that there is very little in terms of protection against
1892 this option being confused by leftover garbage in memory that might
1893 look like a DTB header after a reboot if no actual DTB is appended
1894 to zImage. Do not leave this option active in a production kernel
1895 if you don't intend to always append a DTB. Proper passing of the
1896 location into r2 of a bootloader provided DTB is always preferable
1899 config ARM_ATAG_DTB_COMPAT
1900 bool "Supplement the appended DTB with traditional ATAG information"
1901 depends on ARM_APPENDED_DTB
1903 Some old bootloaders can't be updated to a DTB capable one, yet
1904 they provide ATAGs with memory configuration, the ramdisk address,
1905 the kernel cmdline string, etc. Such information is dynamically
1906 provided by the bootloader and can't always be stored in a static
1907 DTB. To allow a device tree enabled kernel to be used with such
1908 bootloaders, this option allows zImage to extract the information
1909 from the ATAG list and store it at run time into the appended DTB.
1912 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1913 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1915 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1916 bool "Use bootloader kernel arguments if available"
1918 Uses the command-line options passed by the boot loader instead of
1919 the device tree bootargs property. If the boot loader doesn't provide
1920 any, the device tree bootargs property will be used.
1922 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1923 bool "Extend with bootloader kernel arguments"
1925 The command-line arguments provided by the boot loader will be
1926 appended to the the device tree bootargs property.
1931 string "Default kernel command string"
1934 On some architectures (EBSA110 and CATS), there is currently no way
1935 for the boot loader to pass arguments to the kernel. For these
1936 architectures, you should supply some command-line options at build
1937 time by entering them here. As a minimum, you should specify the
1938 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1941 prompt "Kernel command line type" if CMDLINE != ""
1942 default CMDLINE_FROM_BOOTLOADER
1945 config CMDLINE_FROM_BOOTLOADER
1946 bool "Use bootloader kernel arguments if available"
1948 Uses the command-line options passed by the boot loader. If
1949 the boot loader doesn't provide any, the default kernel command
1950 string provided in CMDLINE will be used.
1952 config CMDLINE_EXTEND
1953 bool "Extend bootloader kernel arguments"
1955 The command-line arguments provided by the boot loader will be
1956 appended to the default kernel command string.
1958 config CMDLINE_FORCE
1959 bool "Always use the default kernel command string"
1961 Always use the default kernel command string, even if the boot
1962 loader passes other arguments to the kernel.
1963 This is useful if you cannot or don't want to change the
1964 command-line options your boot loader passes to the kernel.
1968 bool "Kernel Execute-In-Place from ROM"
1969 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1971 Execute-In-Place allows the kernel to run from non-volatile storage
1972 directly addressable by the CPU, such as NOR flash. This saves RAM
1973 space since the text section of the kernel is not loaded from flash
1974 to RAM. Read-write sections, such as the data section and stack,
1975 are still copied to RAM. The XIP kernel is not compressed since
1976 it has to run directly from flash, so it will take more space to
1977 store it. The flash address used to link the kernel object files,
1978 and for storing it, is configuration dependent. Therefore, if you
1979 say Y here, you must know the proper physical address where to
1980 store the kernel image depending on your own flash memory usage.
1982 Also note that the make target becomes "make xipImage" rather than
1983 "make zImage" or "make Image". The final kernel binary to put in
1984 ROM memory will be arch/arm/boot/xipImage.
1988 config XIP_PHYS_ADDR
1989 hex "XIP Kernel Physical Location"
1990 depends on XIP_KERNEL
1991 default "0x00080000"
1993 This is the physical address in your flash memory the kernel will
1994 be linked for and stored to. This address is dependent on your
1998 bool "Kexec system call (EXPERIMENTAL)"
1999 depends on (!SMP || PM_SLEEP_SMP)
2001 kexec is a system call that implements the ability to shutdown your
2002 current kernel, and to start another kernel. It is like a reboot
2003 but it is independent of the system firmware. And like a reboot
2004 you can start any kernel with it, not just Linux.
2006 It is an ongoing process to be certain the hardware in a machine
2007 is properly shutdown, so do not be surprised if this code does not
2008 initially work for you.
2011 bool "Export atags in procfs"
2012 depends on ATAGS && KEXEC
2015 Should the atags used to boot the kernel be exported in an "atags"
2016 file in procfs. Useful with kexec.
2019 bool "Build kdump crash kernel (EXPERIMENTAL)"
2021 Generate crash dump after being started by kexec. This should
2022 be normally only set in special crash dump kernels which are
2023 loaded in the main kernel with kexec-tools into a specially
2024 reserved region and then later executed after a crash by
2025 kdump/kexec. The crash dump kernel must be compiled to a
2026 memory address not used by the main kernel
2028 For more details see Documentation/kdump/kdump.txt
2030 config AUTO_ZRELADDR
2031 bool "Auto calculation of the decompressed kernel image address"
2033 ZRELADDR is the physical address where the decompressed kernel
2034 image will be placed. If AUTO_ZRELADDR is selected, the address
2035 will be determined at run-time by masking the current IP with
2036 0xf8000000. This assumes the zImage being placed in the first 128MB
2037 from start of memory.
2041 menu "CPU Power Management"
2043 source "drivers/cpufreq/Kconfig"
2045 source "drivers/cpuidle/Kconfig"
2049 menu "Floating point emulation"
2051 comment "At least one emulation must be selected"
2054 bool "NWFPE math emulation"
2055 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2057 Say Y to include the NWFPE floating point emulator in the kernel.
2058 This is necessary to run most binaries. Linux does not currently
2059 support floating point hardware so you need to say Y here even if
2060 your machine has an FPA or floating point co-processor podule.
2062 You may say N here if you are going to load the Acorn FPEmulator
2063 early in the bootup.
2066 bool "Support extended precision"
2067 depends on FPE_NWFPE
2069 Say Y to include 80-bit support in the kernel floating-point
2070 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2071 Note that gcc does not generate 80-bit operations by default,
2072 so in most cases this option only enlarges the size of the
2073 floating point emulator without any good reason.
2075 You almost surely want to say N here.
2078 bool "FastFPE math emulation (EXPERIMENTAL)"
2079 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2081 Say Y here to include the FAST floating point emulator in the kernel.
2082 This is an experimental much faster emulator which now also has full
2083 precision for the mantissa. It does not support any exceptions.
2084 It is very simple, and approximately 3-6 times faster than NWFPE.
2086 It should be sufficient for most programs. It may be not suitable
2087 for scientific calculations, but you have to check this for yourself.
2088 If you do not feel you need a faster FP emulation you should better
2092 bool "VFP-format floating point maths"
2093 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2095 Say Y to include VFP support code in the kernel. This is needed
2096 if your hardware includes a VFP unit.
2098 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2099 release notes and additional status information.
2101 Say N if your target does not have VFP hardware.
2109 bool "Advanced SIMD (NEON) Extension support"
2110 depends on VFPv3 && CPU_V7
2112 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2115 config KERNEL_MODE_NEON
2116 bool "Support for NEON in kernel mode"
2117 depends on NEON && AEABI
2119 Say Y to include support for NEON in kernel mode.
2123 menu "Userspace binary formats"
2125 source "fs/Kconfig.binfmt"
2128 tristate "RISC OS personality"
2131 Say Y here to include the kernel code necessary if you want to run
2132 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2133 experimental; if this sounds frightening, say N and sleep in peace.
2134 You can also say M here to compile this support as a module (which
2135 will be called arthur).
2139 menu "Power management options"
2141 source "kernel/power/Kconfig"
2143 config ARCH_SUSPEND_POSSIBLE
2144 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2145 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2148 config ARM_CPU_SUSPEND
2151 config ARCH_HIBERNATION_POSSIBLE
2154 default y if ARCH_SUSPEND_POSSIBLE
2158 source "net/Kconfig"
2160 source "drivers/Kconfig"
2164 source "arch/arm/Kconfig.debug"
2166 source "security/Kconfig"
2168 source "crypto/Kconfig"
2170 source "lib/Kconfig"
2172 source "arch/arm/kvm/Kconfig"