5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
41 config ARM_HAS_SG_CHAIN
50 config SYS_SUPPORTS_APM_EMULATION
53 config HAVE_SCHED_CLOCK
59 config ARCH_USES_GETTIMEOFFSET
63 config GENERIC_CLOCKEVENTS
66 config GENERIC_CLOCKEVENTS_BROADCAST
68 depends on GENERIC_CLOCKEVENTS
77 select GENERIC_ALLOCATOR
88 The Extended Industry Standard Architecture (EISA) bus was
89 developed as an open alternative to the IBM MicroChannel bus.
91 The EISA bus provided some of the features of the IBM MicroChannel
92 bus while maintaining backward compatibility with cards made for
93 the older ISA bus. The EISA bus saw limited use between 1988 and
94 1995 when it was made obsolete by the PCI bus.
96 Say Y here if you are building a kernel for an EISA-based machine.
106 MicroChannel Architecture is found in some IBM PS/2 machines and
107 laptops. It is a bus system similar to PCI or ISA. See
108 <file:Documentation/mca.txt> (and especially the web page given
109 there) before attempting to build an MCA bus kernel.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config HARDIRQS_SW_RESEND
132 config GENERIC_IRQ_PROBE
136 config GENERIC_LOCKBREAK
139 depends on SMP && PREEMPT
141 config RWSEM_GENERIC_SPINLOCK
145 config RWSEM_XCHGADD_ALGORITHM
148 config ARCH_HAS_ILOG2_U32
151 config ARCH_HAS_ILOG2_U64
154 config ARCH_HAS_CPUFREQ
157 Internal node to signify that the ARCH has CPUFREQ support
158 and that the relevant menu configurations are displayed for
161 config ARCH_HAS_CPU_IDLE_WAIT
164 config GENERIC_HWEIGHT
168 config GENERIC_CALIBRATE_DELAY
172 config ARCH_MAY_HAVE_PC_FDC
178 config NEED_DMA_MAP_STATE
181 config GENERIC_ISA_DMA
192 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
193 default DRAM_BASE if REMAP_VECTORS_TO_RAM
196 The base address of exception vectors.
198 config ARM_PATCH_PHYS_VIRT
199 bool "Patch physical to virtual translations at runtime" if EMBEDDED
201 depends on !XIP_KERNEL && MMU
202 depends on !ARCH_REALVIEW || !SPARSEMEM
204 Patch phys-to-virt and virt-to-phys translation functions at
205 boot and module load time according to the position of the
206 kernel in system memory.
208 This can only be used with non-XIP MMU kernels where the base
209 of physical memory is at a 16MB boundary.
211 Only disable this option if you know that you do not require
212 this feature (eg, building a kernel for a single machine) and
213 you need to shrink the kernel to the minimal size.
215 config NEED_MACH_MEMORY_H
218 Select this when mach/memory.h is required to provide special
219 definitions for this platform. The need for mach/memory.h should
220 be avoided when possible.
223 hex "Physical address of main memory"
224 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
226 Please provide the physical address corresponding to the
227 location of main memory in your system.
233 source "init/Kconfig"
235 source "kernel/Kconfig.freezer"
240 bool "MMU-based Paged Memory Management Support"
243 Select if you want MMU-based virtualised addressing space
244 support by paged memory management. If unsure, say 'Y'.
247 # The "ARM system type" choice list is ordered alphabetically by option
248 # text. Please add new entries in the option alphabetic order.
251 prompt "ARM system type"
252 default ARCH_VERSATILE
254 config ARCH_INTEGRATOR
255 bool "ARM Ltd. Integrator family"
257 select ARCH_HAS_CPUFREQ
259 select HAVE_MACH_CLKDEV
261 select GENERIC_CLOCKEVENTS
262 select PLAT_VERSATILE
263 select PLAT_VERSATILE_FPGA_IRQ
264 select NEED_MACH_MEMORY_H
266 Support for ARM's Integrator platform.
269 bool "ARM Ltd. RealView family"
272 select HAVE_MACH_CLKDEV
274 select GENERIC_CLOCKEVENTS
275 select ARCH_WANT_OPTIONAL_GPIOLIB
276 select PLAT_VERSATILE
277 select PLAT_VERSATILE_CLCD
278 select ARM_TIMER_SP804
279 select GPIO_PL061 if GPIOLIB
280 select NEED_MACH_MEMORY_H
282 This enables support for ARM Ltd RealView boards.
284 config ARCH_VERSATILE
285 bool "ARM Ltd. Versatile family"
289 select HAVE_MACH_CLKDEV
291 select GENERIC_CLOCKEVENTS
292 select ARCH_WANT_OPTIONAL_GPIOLIB
293 select PLAT_VERSATILE
294 select PLAT_VERSATILE_CLCD
295 select PLAT_VERSATILE_FPGA_IRQ
296 select ARM_TIMER_SP804
298 This enables support for ARM Ltd Versatile board.
301 bool "ARM Ltd. Versatile Express family"
302 select ARCH_WANT_OPTIONAL_GPIOLIB
304 select ARM_TIMER_SP804
306 select HAVE_MACH_CLKDEV
307 select GENERIC_CLOCKEVENTS
309 select HAVE_PATA_PLATFORM
311 select PLAT_VERSATILE
312 select PLAT_VERSATILE_CLCD
314 This enables support for the ARM Ltd Versatile Express boards.
318 select ARCH_REQUIRE_GPIOLIB
322 This enables support for systems based on the Atmel AT91RM9200,
323 AT91SAM9 and AT91CAP9 processors.
326 bool "Broadcom BCMRING"
330 select ARM_TIMER_SP804
332 select GENERIC_CLOCKEVENTS
333 select ARCH_WANT_OPTIONAL_GPIOLIB
335 Support for Broadcom's BCMRing platform.
338 bool "Cirrus Logic CLPS711x/EP721x-based"
340 select ARCH_USES_GETTIMEOFFSET
341 select NEED_MACH_MEMORY_H
343 Support for Cirrus Logic 711x/721x based boards.
346 bool "Cavium Networks CNS3XXX family"
348 select GENERIC_CLOCKEVENTS
350 select MIGHT_HAVE_PCI
351 select PCI_DOMAINS if PCI
353 Support for Cavium Networks CNS3XXX platform.
356 bool "Cortina Systems Gemini"
358 select ARCH_REQUIRE_GPIOLIB
359 select ARCH_USES_GETTIMEOFFSET
361 Support for the Cortina Systems Gemini family SoCs
364 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
367 select GENERIC_CLOCKEVENTS
369 select GENERIC_IRQ_CHIP
373 Support for CSR SiRFSoC ARM Cortex A9 Platform
380 select ARCH_USES_GETTIMEOFFSET
381 select NEED_MACH_MEMORY_H
383 This is an evaluation board for the StrongARM processor available
384 from Digital. It has limited hardware on-board, including an
385 Ethernet interface, two PCMCIA sockets, two serial ports and a
394 select ARCH_REQUIRE_GPIOLIB
395 select ARCH_HAS_HOLES_MEMORYMODEL
396 select ARCH_USES_GETTIMEOFFSET
397 select NEED_MACH_MEMORY_H
399 This enables support for the Cirrus EP93xx series of CPUs.
401 config ARCH_FOOTBRIDGE
405 select GENERIC_CLOCKEVENTS
407 select NEED_MACH_MEMORY_H
409 Support for systems based on the DC21285 companion chip
410 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
413 bool "Freescale MXC/iMX-based"
414 select GENERIC_CLOCKEVENTS
415 select ARCH_REQUIRE_GPIOLIB
418 select GENERIC_IRQ_CHIP
419 select HAVE_SCHED_CLOCK
420 select MULTI_IRQ_HANDLER
422 Support for Freescale MXC/iMX-based family of processors
425 bool "Freescale MXS-based"
426 select GENERIC_CLOCKEVENTS
427 select ARCH_REQUIRE_GPIOLIB
431 Support for Freescale MXS-based family of processors
434 bool "Hilscher NetX based"
438 select GENERIC_CLOCKEVENTS
440 This enables support for systems based on the Hilscher NetX Soc
443 bool "Hynix HMS720x-based"
446 select ARCH_USES_GETTIMEOFFSET
448 This enables support for systems based on the Hynix HMS720x
456 select ARCH_SUPPORTS_MSI
458 select NEED_MACH_MEMORY_H
460 Support for Intel's IOP13XX (XScale) family of processors.
468 select ARCH_REQUIRE_GPIOLIB
470 Support for Intel's 80219 and IOP32X (XScale) family of
479 select ARCH_REQUIRE_GPIOLIB
481 Support for Intel's IOP33X (XScale) family of processors.
488 select ARCH_USES_GETTIMEOFFSET
489 select NEED_MACH_MEMORY_H
491 Support for Intel's IXP23xx (XScale) family of processors.
494 bool "IXP2400/2800-based"
498 select ARCH_USES_GETTIMEOFFSET
499 select NEED_MACH_MEMORY_H
501 Support for Intel's IXP2400/2800 (XScale) family of processors.
509 select GENERIC_CLOCKEVENTS
510 select HAVE_SCHED_CLOCK
511 select MIGHT_HAVE_PCI
512 select DMABOUNCE if PCI
514 Support for Intel's IXP4XX (XScale) family of processors.
520 select ARCH_REQUIRE_GPIOLIB
521 select GENERIC_CLOCKEVENTS
524 Support for the Marvell Dove SoC 88AP510
527 bool "Marvell Kirkwood"
530 select ARCH_REQUIRE_GPIOLIB
531 select GENERIC_CLOCKEVENTS
534 Support for the following Marvell Kirkwood series SoCs:
535 88F6180, 88F6192 and 88F6281.
541 select ARCH_REQUIRE_GPIOLIB
544 select USB_ARCH_HAS_OHCI
546 select GENERIC_CLOCKEVENTS
548 Support for the NXP LPC32XX family of processors
551 bool "Marvell MV78xx0"
554 select ARCH_REQUIRE_GPIOLIB
555 select GENERIC_CLOCKEVENTS
558 Support for the following Marvell MV78xx0 series SoCs:
566 select ARCH_REQUIRE_GPIOLIB
567 select GENERIC_CLOCKEVENTS
570 Support for the following Marvell Orion 5x series SoCs:
571 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
572 Orion-2 (5281), Orion-1-90 (6183).
575 bool "Marvell PXA168/910/MMP2"
577 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS
580 select HAVE_SCHED_CLOCK
585 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
588 bool "Micrel/Kendin KS8695"
590 select ARCH_REQUIRE_GPIOLIB
591 select ARCH_USES_GETTIMEOFFSET
592 select NEED_MACH_MEMORY_H
594 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
595 System-on-Chip devices.
598 bool "Nuvoton W90X900 CPU"
600 select ARCH_REQUIRE_GPIOLIB
603 select GENERIC_CLOCKEVENTS
605 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
606 At present, the w90x900 has been renamed nuc900, regarding
607 the ARM series product line, you can login the following
608 link address to know more.
610 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
611 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
617 select GENERIC_CLOCKEVENTS
620 select HAVE_SCHED_CLOCK
621 select ARCH_HAS_CPUFREQ
623 This enables support for NVIDIA Tegra based systems (Tegra APX,
624 Tegra 6xx and Tegra 2 series).
627 bool "Philips Nexperia PNX4008 Mobile"
630 select ARCH_USES_GETTIMEOFFSET
632 This enables support for Philips PNX4008 mobile platform.
635 bool "PXA2xx/PXA3xx-based"
638 select ARCH_HAS_CPUFREQ
641 select ARCH_REQUIRE_GPIOLIB
642 select GENERIC_CLOCKEVENTS
643 select HAVE_SCHED_CLOCK
648 select MULTI_IRQ_HANDLER
649 select ARM_CPU_SUSPEND if PM
652 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
657 select GENERIC_CLOCKEVENTS
658 select ARCH_REQUIRE_GPIOLIB
661 Support for Qualcomm MSM/QSD based systems. This runs on the
662 apps processor of the MSM/QSD and depends on a shared memory
663 interface to the modem processor which runs the baseband
664 stack and controls some vital subsystems
665 (clock and power control, etc).
668 bool "Renesas SH-Mobile / R-Mobile"
671 select HAVE_MACH_CLKDEV
672 select GENERIC_CLOCKEVENTS
675 select MULTI_IRQ_HANDLER
676 select PM_GENERIC_DOMAINS if PM
677 select NEED_MACH_MEMORY_H
679 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
686 select ARCH_MAY_HAVE_PC_FDC
687 select HAVE_PATA_PLATFORM
690 select ARCH_SPARSEMEM_ENABLE
691 select ARCH_USES_GETTIMEOFFSET
693 select NEED_MACH_MEMORY_H
695 On the Acorn Risc-PC, Linux can support the internal IDE disk and
696 CD-ROM interface, serial and parallel port, and the floppy drive.
703 select ARCH_SPARSEMEM_ENABLE
705 select ARCH_HAS_CPUFREQ
707 select GENERIC_CLOCKEVENTS
709 select HAVE_SCHED_CLOCK
711 select ARCH_REQUIRE_GPIOLIB
713 select NEED_MACH_MEMORY_H
715 Support for StrongARM 11x0 based boards.
718 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
720 select ARCH_HAS_CPUFREQ
723 select ARCH_USES_GETTIMEOFFSET
724 select HAVE_S3C2410_I2C if I2C
726 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
727 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
728 the Samsung SMDK2410 development board (and derivatives).
730 Note, the S3C2416 and the S3C2450 are so close that they even share
731 the same SoC ID code. This means that there is no separate machine
732 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
735 bool "Samsung S3C64XX"
742 select ARCH_USES_GETTIMEOFFSET
743 select ARCH_HAS_CPUFREQ
744 select ARCH_REQUIRE_GPIOLIB
745 select SAMSUNG_CLKSRC
746 select SAMSUNG_IRQ_VIC_TIMER
747 select S3C_GPIO_TRACK
748 select S3C_GPIO_PULL_UPDOWN
749 select S3C_GPIO_CFG_S3C24XX
750 select S3C_GPIO_CFG_S3C64XX
752 select USB_ARCH_HAS_OHCI
753 select SAMSUNG_GPIOLIB_4BIT
754 select HAVE_S3C2410_I2C if I2C
755 select HAVE_S3C2410_WATCHDOG if WATCHDOG
757 Samsung S3C64XX series based systems
760 bool "Samsung S5P6440 S5P6450"
766 select HAVE_S3C2410_WATCHDOG if WATCHDOG
767 select GENERIC_CLOCKEVENTS
768 select HAVE_SCHED_CLOCK
769 select HAVE_S3C2410_I2C if I2C
770 select HAVE_S3C_RTC if RTC_CLASS
772 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
776 bool "Samsung S5PC100"
781 select ARM_L1_CACHE_SHIFT_6
782 select ARCH_USES_GETTIMEOFFSET
783 select HAVE_S3C2410_I2C if I2C
784 select HAVE_S3C_RTC if RTC_CLASS
785 select HAVE_S3C2410_WATCHDOG if WATCHDOG
787 Samsung S5PC100 series based systems
790 bool "Samsung S5PV210/S5PC110"
792 select ARCH_SPARSEMEM_ENABLE
793 select ARCH_HAS_HOLES_MEMORYMODEL
798 select ARM_L1_CACHE_SHIFT_6
799 select ARCH_HAS_CPUFREQ
800 select GENERIC_CLOCKEVENTS
801 select HAVE_SCHED_CLOCK
802 select HAVE_S3C2410_I2C if I2C
803 select HAVE_S3C_RTC if RTC_CLASS
804 select HAVE_S3C2410_WATCHDOG if WATCHDOG
805 select NEED_MACH_MEMORY_H
807 Samsung S5PV210/S5PC110 series based systems
810 bool "Samsung EXYNOS4"
812 select ARCH_SPARSEMEM_ENABLE
813 select ARCH_HAS_HOLES_MEMORYMODEL
817 select ARCH_HAS_CPUFREQ
818 select GENERIC_CLOCKEVENTS
819 select HAVE_S3C_RTC if RTC_CLASS
820 select HAVE_S3C2410_I2C if I2C
821 select HAVE_S3C2410_WATCHDOG if WATCHDOG
822 select NEED_MACH_MEMORY_H
824 Samsung EXYNOS4 series based systems
833 select ARCH_USES_GETTIMEOFFSET
834 select NEED_MACH_MEMORY_H
836 Support for the StrongARM based Digital DNARD machine, also known
837 as "Shark" (<http://www.shark-linux.de/shark.html>).
840 bool "Telechips TCC ARM926-based systems"
845 select GENERIC_CLOCKEVENTS
847 Support for Telechips TCC ARM926-based systems.
850 bool "ST-Ericsson U300 Series"
854 select HAVE_SCHED_CLOCK
857 select ARM_PATCH_PHYS_VIRT
859 select GENERIC_CLOCKEVENTS
861 select HAVE_MACH_CLKDEV
863 select ARCH_REQUIRE_GPIOLIB
864 select NEED_MACH_MEMORY_H
866 Support for ST-Ericsson U300 series mobile platforms.
869 bool "ST-Ericsson U8500 Series"
872 select GENERIC_CLOCKEVENTS
874 select ARCH_REQUIRE_GPIOLIB
875 select ARCH_HAS_CPUFREQ
877 Support for ST-Ericsson's Ux500 architecture
880 bool "STMicroelectronics Nomadik"
885 select GENERIC_CLOCKEVENTS
886 select ARCH_REQUIRE_GPIOLIB
888 Support for the Nomadik platform by ST-Ericsson
892 select GENERIC_CLOCKEVENTS
893 select ARCH_REQUIRE_GPIOLIB
897 select GENERIC_ALLOCATOR
898 select GENERIC_IRQ_CHIP
899 select ARCH_HAS_HOLES_MEMORYMODEL
901 Support for TI's DaVinci platform.
906 select ARCH_REQUIRE_GPIOLIB
907 select ARCH_HAS_CPUFREQ
909 select GENERIC_CLOCKEVENTS
910 select HAVE_SCHED_CLOCK
911 select ARCH_HAS_HOLES_MEMORYMODEL
913 Support for TI's OMAP platform (OMAP1/2/3/4).
918 select ARCH_REQUIRE_GPIOLIB
921 select GENERIC_CLOCKEVENTS
924 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
927 bool "VIA/WonderMedia 85xx"
930 select ARCH_HAS_CPUFREQ
931 select GENERIC_CLOCKEVENTS
932 select ARCH_REQUIRE_GPIOLIB
935 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
938 bool "Xilinx Zynq ARM Cortex A9 Platform"
940 select GENERIC_CLOCKEVENTS
947 Support for Xilinx Zynq ARM Cortex A9 Platform
951 # This is sorted alphabetically by mach-* pathname. However, plat-*
952 # Kconfigs may be included either alphabetically (according to the
953 # plat- suffix) or along side the corresponding mach-* source.
955 source "arch/arm/mach-at91/Kconfig"
957 source "arch/arm/mach-bcmring/Kconfig"
959 source "arch/arm/mach-clps711x/Kconfig"
961 source "arch/arm/mach-cns3xxx/Kconfig"
963 source "arch/arm/mach-davinci/Kconfig"
965 source "arch/arm/mach-dove/Kconfig"
967 source "arch/arm/mach-ep93xx/Kconfig"
969 source "arch/arm/mach-footbridge/Kconfig"
971 source "arch/arm/mach-gemini/Kconfig"
973 source "arch/arm/mach-h720x/Kconfig"
975 source "arch/arm/mach-integrator/Kconfig"
977 source "arch/arm/mach-iop32x/Kconfig"
979 source "arch/arm/mach-iop33x/Kconfig"
981 source "arch/arm/mach-iop13xx/Kconfig"
983 source "arch/arm/mach-ixp4xx/Kconfig"
985 source "arch/arm/mach-ixp2000/Kconfig"
987 source "arch/arm/mach-ixp23xx/Kconfig"
989 source "arch/arm/mach-kirkwood/Kconfig"
991 source "arch/arm/mach-ks8695/Kconfig"
993 source "arch/arm/mach-lpc32xx/Kconfig"
995 source "arch/arm/mach-msm/Kconfig"
997 source "arch/arm/mach-mv78xx0/Kconfig"
999 source "arch/arm/plat-mxc/Kconfig"
1001 source "arch/arm/mach-mxs/Kconfig"
1003 source "arch/arm/mach-netx/Kconfig"
1005 source "arch/arm/mach-nomadik/Kconfig"
1006 source "arch/arm/plat-nomadik/Kconfig"
1008 source "arch/arm/plat-omap/Kconfig"
1010 source "arch/arm/mach-omap1/Kconfig"
1012 source "arch/arm/mach-omap2/Kconfig"
1014 source "arch/arm/mach-orion5x/Kconfig"
1016 source "arch/arm/mach-pxa/Kconfig"
1017 source "arch/arm/plat-pxa/Kconfig"
1019 source "arch/arm/mach-mmp/Kconfig"
1021 source "arch/arm/mach-realview/Kconfig"
1023 source "arch/arm/mach-sa1100/Kconfig"
1025 source "arch/arm/plat-samsung/Kconfig"
1026 source "arch/arm/plat-s3c24xx/Kconfig"
1027 source "arch/arm/plat-s5p/Kconfig"
1029 source "arch/arm/plat-spear/Kconfig"
1031 source "arch/arm/plat-tcc/Kconfig"
1034 source "arch/arm/mach-s3c2410/Kconfig"
1035 source "arch/arm/mach-s3c2412/Kconfig"
1036 source "arch/arm/mach-s3c2416/Kconfig"
1037 source "arch/arm/mach-s3c2440/Kconfig"
1038 source "arch/arm/mach-s3c2443/Kconfig"
1042 source "arch/arm/mach-s3c64xx/Kconfig"
1045 source "arch/arm/mach-s5p64x0/Kconfig"
1047 source "arch/arm/mach-s5pc100/Kconfig"
1049 source "arch/arm/mach-s5pv210/Kconfig"
1051 source "arch/arm/mach-exynos4/Kconfig"
1053 source "arch/arm/mach-shmobile/Kconfig"
1055 source "arch/arm/mach-tegra/Kconfig"
1057 source "arch/arm/mach-u300/Kconfig"
1059 source "arch/arm/mach-ux500/Kconfig"
1061 source "arch/arm/mach-versatile/Kconfig"
1063 source "arch/arm/mach-vexpress/Kconfig"
1064 source "arch/arm/plat-versatile/Kconfig"
1066 source "arch/arm/mach-vt8500/Kconfig"
1068 source "arch/arm/mach-w90x900/Kconfig"
1070 # Definitions to make life easier
1076 select GENERIC_CLOCKEVENTS
1077 select HAVE_SCHED_CLOCK
1082 select GENERIC_IRQ_CHIP
1083 select HAVE_SCHED_CLOCK
1088 config PLAT_VERSATILE
1091 config ARM_TIMER_SP804
1095 source arch/arm/mm/Kconfig
1098 bool "Enable iWMMXt support"
1099 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1100 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1102 Enable support for iWMMXt context switching at run time if
1103 running on a CPU that supports it.
1105 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1108 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1112 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1113 (!ARCH_OMAP3 || OMAP3_EMU)
1117 config MULTI_IRQ_HANDLER
1120 Allow each machine to specify it's own IRQ handler at run time.
1123 source "arch/arm/Kconfig-nommu"
1126 config ARM_ERRATA_411920
1127 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1128 depends on CPU_V6 || CPU_V6K
1130 Invalidation of the Instruction Cache operation can
1131 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1132 It does not affect the MPCore. This option enables the ARM Ltd.
1133 recommended workaround.
1135 config ARM_ERRATA_430973
1136 bool "ARM errata: Stale prediction on replaced interworking branch"
1139 This option enables the workaround for the 430973 Cortex-A8
1140 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1141 interworking branch is replaced with another code sequence at the
1142 same virtual address, whether due to self-modifying code or virtual
1143 to physical address re-mapping, Cortex-A8 does not recover from the
1144 stale interworking branch prediction. This results in Cortex-A8
1145 executing the new code sequence in the incorrect ARM or Thumb state.
1146 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1147 and also flushes the branch target cache at every context switch.
1148 Note that setting specific bits in the ACTLR register may not be
1149 available in non-secure mode.
1151 config ARM_ERRATA_458693
1152 bool "ARM errata: Processor deadlock when a false hazard is created"
1155 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1156 erratum. For very specific sequences of memory operations, it is
1157 possible for a hazard condition intended for a cache line to instead
1158 be incorrectly associated with a different cache line. This false
1159 hazard might then cause a processor deadlock. The workaround enables
1160 the L1 caching of the NEON accesses and disables the PLD instruction
1161 in the ACTLR register. Note that setting specific bits in the ACTLR
1162 register may not be available in non-secure mode.
1164 config ARM_ERRATA_460075
1165 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1168 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1169 erratum. Any asynchronous access to the L2 cache may encounter a
1170 situation in which recent store transactions to the L2 cache are lost
1171 and overwritten with stale memory contents from external memory. The
1172 workaround disables the write-allocate mode for the L2 cache via the
1173 ACTLR register. Note that setting specific bits in the ACTLR register
1174 may not be available in non-secure mode.
1176 config ARM_ERRATA_742230
1177 bool "ARM errata: DMB operation may be faulty"
1178 depends on CPU_V7 && SMP
1180 This option enables the workaround for the 742230 Cortex-A9
1181 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1182 between two write operations may not ensure the correct visibility
1183 ordering of the two writes. This workaround sets a specific bit in
1184 the diagnostic register of the Cortex-A9 which causes the DMB
1185 instruction to behave as a DSB, ensuring the correct behaviour of
1188 config ARM_ERRATA_742231
1189 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1190 depends on CPU_V7 && SMP
1192 This option enables the workaround for the 742231 Cortex-A9
1193 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1194 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1195 accessing some data located in the same cache line, may get corrupted
1196 data due to bad handling of the address hazard when the line gets
1197 replaced from one of the CPUs at the same time as another CPU is
1198 accessing it. This workaround sets specific bits in the diagnostic
1199 register of the Cortex-A9 which reduces the linefill issuing
1200 capabilities of the processor.
1202 config PL310_ERRATA_588369
1203 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1204 depends on CACHE_L2X0
1206 The PL310 L2 cache controller implements three types of Clean &
1207 Invalidate maintenance operations: by Physical Address
1208 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1209 They are architecturally defined to behave as the execution of a
1210 clean operation followed immediately by an invalidate operation,
1211 both performing to the same memory location. This functionality
1212 is not correctly implemented in PL310 as clean lines are not
1213 invalidated as a result of these operations.
1215 config ARM_ERRATA_720789
1216 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1217 depends on CPU_V7 && SMP
1219 This option enables the workaround for the 720789 Cortex-A9 (prior to
1220 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1221 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1222 As a consequence of this erratum, some TLB entries which should be
1223 invalidated are not, resulting in an incoherency in the system page
1224 tables. The workaround changes the TLB flushing routines to invalidate
1225 entries regardless of the ASID.
1227 config PL310_ERRATA_727915
1228 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1229 depends on CACHE_L2X0
1231 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1232 operation (offset 0x7FC). This operation runs in background so that
1233 PL310 can handle normal accesses while it is in progress. Under very
1234 rare circumstances, due to this erratum, write data can be lost when
1235 PL310 treats a cacheable write transaction during a Clean &
1236 Invalidate by Way operation.
1238 config ARM_ERRATA_743622
1239 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1242 This option enables the workaround for the 743622 Cortex-A9
1243 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1244 optimisation in the Cortex-A9 Store Buffer may lead to data
1245 corruption. This workaround sets a specific bit in the diagnostic
1246 register of the Cortex-A9 which disables the Store Buffer
1247 optimisation, preventing the defect from occurring. This has no
1248 visible impact on the overall performance or power consumption of the
1251 config ARM_ERRATA_751472
1252 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1253 depends on CPU_V7 && SMP
1255 This option enables the workaround for the 751472 Cortex-A9 (prior
1256 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1257 completion of a following broadcasted operation if the second
1258 operation is received by a CPU before the ICIALLUIS has completed,
1259 potentially leading to corrupted entries in the cache or TLB.
1261 config ARM_ERRATA_753970
1262 bool "ARM errata: cache sync operation may be faulty"
1263 depends on CACHE_PL310
1265 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1267 Under some condition the effect of cache sync operation on
1268 the store buffer still remains when the operation completes.
1269 This means that the store buffer is always asked to drain and
1270 this prevents it from merging any further writes. The workaround
1271 is to replace the normal offset of cache sync operation (0x730)
1272 by another offset targeting an unmapped PL310 register 0x740.
1273 This has the same effect as the cache sync operation: store buffer
1274 drain and waiting for all buffers empty.
1276 config ARM_ERRATA_754322
1277 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1280 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1281 r3p*) erratum. A speculative memory access may cause a page table walk
1282 which starts prior to an ASID switch but completes afterwards. This
1283 can populate the micro-TLB with a stale entry which may be hit with
1284 the new ASID. This workaround places two dsb instructions in the mm
1285 switching code so that no page table walks can cross the ASID switch.
1287 config ARM_ERRATA_754327
1288 bool "ARM errata: no automatic Store Buffer drain"
1289 depends on CPU_V7 && SMP
1291 This option enables the workaround for the 754327 Cortex-A9 (prior to
1292 r2p0) erratum. The Store Buffer does not have any automatic draining
1293 mechanism and therefore a livelock may occur if an external agent
1294 continuously polls a memory location waiting to observe an update.
1295 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1296 written polling loops from denying visibility of updates to memory.
1298 config ARM_ERRATA_364296
1299 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1300 depends on CPU_V6 && !SMP
1302 This options enables the workaround for the 364296 ARM1136
1303 r0p2 erratum (possible cache data corruption with
1304 hit-under-miss enabled). It sets the undocumented bit 31 in
1305 the auxiliary control register and the FI bit in the control
1306 register, thus disabling hit-under-miss without putting the
1307 processor into full low interrupt latency mode. ARM11MPCore
1310 config ARM_ERRATA_764369
1311 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1312 depends on CPU_V7 && SMP
1314 This option enables the workaround for erratum 764369
1315 affecting Cortex-A9 MPCore with two or more processors (all
1316 current revisions). Under certain timing circumstances, a data
1317 cache line maintenance operation by MVA targeting an Inner
1318 Shareable memory region may fail to proceed up to either the
1319 Point of Coherency or to the Point of Unification of the
1320 system. This workaround adds a DSB instruction before the
1321 relevant cache maintenance functions and sets a specific bit
1322 in the diagnostic control register of the SCU.
1326 source "arch/arm/common/Kconfig"
1336 Find out whether you have ISA slots on your motherboard. ISA is the
1337 name of a bus system, i.e. the way the CPU talks to the other stuff
1338 inside your box. Other bus systems are PCI, EISA, MicroChannel
1339 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1340 newer boards don't support it. If you have ISA, say Y, otherwise N.
1342 # Select ISA DMA controller support
1347 # Select ISA DMA interface
1352 bool "PCI support" if MIGHT_HAVE_PCI
1354 Find out whether you have a PCI motherboard. PCI is the name of a
1355 bus system, i.e. the way the CPU talks to the other stuff inside
1356 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1357 VESA. If you have PCI, say Y, otherwise N.
1363 config PCI_NANOENGINE
1364 bool "BSE nanoEngine PCI support"
1365 depends on SA1100_NANOENGINE
1367 Enable PCI on the BSE nanoEngine board.
1372 # Select the host bridge type
1373 config PCI_HOST_VIA82C505
1375 depends on PCI && ARCH_SHARK
1378 config PCI_HOST_ITE8152
1380 depends on PCI && MACH_ARMCORE
1384 source "drivers/pci/Kconfig"
1386 source "drivers/pcmcia/Kconfig"
1390 menu "Kernel Features"
1392 source "kernel/time/Kconfig"
1395 bool "Symmetric Multi-Processing"
1396 depends on CPU_V6K || CPU_V7
1397 depends on GENERIC_CLOCKEVENTS
1398 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1399 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1400 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1401 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1403 select USE_GENERIC_SMP_HELPERS
1404 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1406 This enables support for systems with more than one CPU. If you have
1407 a system with only one CPU, like most personal computers, say N. If
1408 you have a system with more than one CPU, say Y.
1410 If you say N here, the kernel will run on single and multiprocessor
1411 machines, but will use only one CPU of a multiprocessor machine. If
1412 you say Y here, the kernel will run on many, but not all, single
1413 processor machines. On a single processor machine, the kernel will
1414 run faster if you say N here.
1416 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1417 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1418 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1420 If you don't know what to do here, say N.
1423 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1424 depends on EXPERIMENTAL
1425 depends on SMP && !XIP_KERNEL
1428 SMP kernels contain instructions which fail on non-SMP processors.
1429 Enabling this option allows the kernel to modify itself to make
1430 these instructions safe. Disabling it allows about 1K of space
1433 If you don't know what to do here, say Y.
1435 config ARM_CPU_TOPOLOGY
1436 bool "Support cpu topology definition"
1437 depends on SMP && CPU_V7
1440 Support ARM cpu topology definition. The MPIDR register defines
1441 affinity between processors which is then used to describe the cpu
1442 topology of an ARM System.
1445 bool "Multi-core scheduler support"
1446 depends on ARM_CPU_TOPOLOGY
1448 Multi-core scheduler support improves the CPU scheduler's decision
1449 making when dealing with multi-core CPU chips at a cost of slightly
1450 increased overhead in some places. If unsure say N here.
1453 bool "SMT scheduler support"
1454 depends on ARM_CPU_TOPOLOGY
1456 Improves the CPU scheduler's decision making when dealing with
1457 MultiThreading at a cost of slightly increased overhead in some
1458 places. If unsure say N here.
1463 This option enables support for the ARM system coherency unit
1470 This options enables support for the ARM timer and watchdog unit
1473 prompt "Memory split"
1476 Select the desired split between kernel and user memory.
1478 If you are not absolutely sure what you are doing, leave this
1482 bool "3G/1G user/kernel split"
1484 bool "2G/2G user/kernel split"
1486 bool "1G/3G user/kernel split"
1491 default 0x40000000 if VMSPLIT_1G
1492 default 0x80000000 if VMSPLIT_2G
1496 int "Maximum number of CPUs (2-32)"
1502 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1503 depends on SMP && HOTPLUG && EXPERIMENTAL
1505 Say Y here to experiment with turning CPUs off and on. CPUs
1506 can be controlled through /sys/devices/system/cpu.
1509 bool "Use local timer interrupts"
1512 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1514 Enable support for local timers on SMP platforms, rather then the
1515 legacy IPI broadcast method. Local timers allows the system
1516 accounting to be spread across the timer interval, preventing a
1517 "thundering herd" at every timer tick.
1519 source kernel/Kconfig.preempt
1523 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1524 ARCH_S5PV210 || ARCH_EXYNOS4
1525 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1526 default AT91_TIMER_HZ if ARCH_AT91
1527 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1530 config THUMB2_KERNEL
1531 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1532 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1534 select ARM_ASM_UNIFIED
1537 By enabling this option, the kernel will be compiled in
1538 Thumb-2 mode. A compiler/assembler that understand the unified
1539 ARM-Thumb syntax is needed.
1543 config THUMB2_AVOID_R_ARM_THM_JUMP11
1544 bool "Work around buggy Thumb-2 short branch relocations in gas"
1545 depends on THUMB2_KERNEL && MODULES
1548 Various binutils versions can resolve Thumb-2 branches to
1549 locally-defined, preemptible global symbols as short-range "b.n"
1550 branch instructions.
1552 This is a problem, because there's no guarantee the final
1553 destination of the symbol, or any candidate locations for a
1554 trampoline, are within range of the branch. For this reason, the
1555 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1556 relocation in modules at all, and it makes little sense to add
1559 The symptom is that the kernel fails with an "unsupported
1560 relocation" error when loading some modules.
1562 Until fixed tools are available, passing
1563 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1564 code which hits this problem, at the cost of a bit of extra runtime
1565 stack usage in some cases.
1567 The problem is described in more detail at:
1568 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1570 Only Thumb-2 kernels are affected.
1572 Unless you are sure your tools don't have this problem, say Y.
1574 config ARM_ASM_UNIFIED
1578 bool "Use the ARM EABI to compile the kernel"
1580 This option allows for the kernel to be compiled using the latest
1581 ARM ABI (aka EABI). This is only useful if you are using a user
1582 space environment that is also compiled with EABI.
1584 Since there are major incompatibilities between the legacy ABI and
1585 EABI, especially with regard to structure member alignment, this
1586 option also changes the kernel syscall calling convention to
1587 disambiguate both ABIs and allow for backward compatibility support
1588 (selected with CONFIG_OABI_COMPAT).
1590 To use this you need GCC version 4.0.0 or later.
1593 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1594 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1597 This option preserves the old syscall interface along with the
1598 new (ARM EABI) one. It also provides a compatibility layer to
1599 intercept syscalls that have structure arguments which layout
1600 in memory differs between the legacy ABI and the new ARM EABI
1601 (only for non "thumb" binaries). This option adds a tiny
1602 overhead to all syscalls and produces a slightly larger kernel.
1603 If you know you'll be using only pure EABI user space then you
1604 can say N here. If this option is not selected and you attempt
1605 to execute a legacy ABI binary then the result will be
1606 UNPREDICTABLE (in fact it can be predicted that it won't work
1607 at all). If in doubt say Y.
1609 config ARCH_HAS_HOLES_MEMORYMODEL
1612 config ARCH_SPARSEMEM_ENABLE
1615 config ARCH_SPARSEMEM_DEFAULT
1616 def_bool ARCH_SPARSEMEM_ENABLE
1618 config ARCH_SELECT_MEMORY_MODEL
1619 def_bool ARCH_SPARSEMEM_ENABLE
1621 config HAVE_ARCH_PFN_VALID
1622 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1625 bool "High Memory Support"
1628 The address space of ARM processors is only 4 Gigabytes large
1629 and it has to accommodate user address space, kernel address
1630 space as well as some memory mapped IO. That means that, if you
1631 have a large amount of physical memory and/or IO, not all of the
1632 memory can be "permanently mapped" by the kernel. The physical
1633 memory that is not permanently mapped is called "high memory".
1635 Depending on the selected kernel/user memory split, minimum
1636 vmalloc space and actual amount of RAM, you may not need this
1637 option which should result in a slightly faster kernel.
1642 bool "Allocate 2nd-level pagetables from highmem"
1645 config HW_PERF_EVENTS
1646 bool "Enable hardware performance counter support for perf events"
1647 depends on PERF_EVENTS && CPU_HAS_PMU
1650 Enable hardware performance counter support for perf events. If
1651 disabled, perf events will use software events only.
1655 config FORCE_MAX_ZONEORDER
1656 int "Maximum zone order" if ARCH_SHMOBILE
1657 range 11 64 if ARCH_SHMOBILE
1658 default "9" if SA1111
1661 The kernel memory allocator divides physically contiguous memory
1662 blocks into "zones", where each zone is a power of two number of
1663 pages. This option selects the largest power of two that the kernel
1664 keeps in the memory allocator. If you need to allocate very large
1665 blocks of physically contiguous memory, then you may need to
1666 increase this value.
1668 This config option is actually maximum order plus one. For example,
1669 a value of 11 means that the largest free memory block is 2^10 pages.
1672 bool "Timer and CPU usage LEDs"
1673 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1674 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1675 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1676 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1677 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1678 ARCH_AT91 || ARCH_DAVINCI || \
1679 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1681 If you say Y here, the LEDs on your machine will be used
1682 to provide useful information about your current system status.
1684 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1685 be able to select which LEDs are active using the options below. If
1686 you are compiling a kernel for the EBSA-110 or the LART however, the
1687 red LED will simply flash regularly to indicate that the system is
1688 still functional. It is safe to say Y here if you have a CATS
1689 system, but the driver will do nothing.
1692 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1693 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1694 || MACH_OMAP_PERSEUS2
1696 depends on !GENERIC_CLOCKEVENTS
1697 default y if ARCH_EBSA110
1699 If you say Y here, one of the system LEDs (the green one on the
1700 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1701 will flash regularly to indicate that the system is still
1702 operational. This is mainly useful to kernel hackers who are
1703 debugging unstable kernels.
1705 The LART uses the same LED for both Timer LED and CPU usage LED
1706 functions. You may choose to use both, but the Timer LED function
1707 will overrule the CPU usage LED.
1710 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1712 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1713 || MACH_OMAP_PERSEUS2
1716 If you say Y here, the red LED will be used to give a good real
1717 time indication of CPU usage, by lighting whenever the idle task
1718 is not currently executing.
1720 The LART uses the same LED for both Timer LED and CPU usage LED
1721 functions. You may choose to use both, but the Timer LED function
1722 will overrule the CPU usage LED.
1724 config ALIGNMENT_TRAP
1726 depends on CPU_CP15_MMU
1727 default y if !ARCH_EBSA110
1728 select HAVE_PROC_CPU if PROC_FS
1730 ARM processors cannot fetch/store information which is not
1731 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1732 address divisible by 4. On 32-bit ARM processors, these non-aligned
1733 fetch/store instructions will be emulated in software if you say
1734 here, which has a severe performance impact. This is necessary for
1735 correct operation of some network protocols. With an IP-only
1736 configuration it is safe to say N, otherwise say Y.
1738 config UACCESS_WITH_MEMCPY
1739 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1740 depends on MMU && EXPERIMENTAL
1741 default y if CPU_FEROCEON
1743 Implement faster copy_to_user and clear_user methods for CPU
1744 cores where a 8-word STM instruction give significantly higher
1745 memory write throughput than a sequence of individual 32bit stores.
1747 A possible side effect is a slight increase in scheduling latency
1748 between threads sharing the same address space if they invoke
1749 such copy operations with large buffers.
1751 However, if the CPU data cache is using a write-allocate mode,
1752 this option is unlikely to provide any performance gain.
1756 prompt "Enable seccomp to safely compute untrusted bytecode"
1758 This kernel feature is useful for number crunching applications
1759 that may need to compute untrusted bytecode during their
1760 execution. By using pipes or other transports made available to
1761 the process as file descriptors supporting the read/write
1762 syscalls, it's possible to isolate those applications in
1763 their own address space using seccomp. Once seccomp is
1764 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1765 and the task is only allowed to execute a few safe syscalls
1766 defined by each seccomp mode.
1768 config CC_STACKPROTECTOR
1769 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1770 depends on EXPERIMENTAL
1772 This option turns on the -fstack-protector GCC feature. This
1773 feature puts, at the beginning of functions, a canary value on
1774 the stack just before the return address, and validates
1775 the value just before actually returning. Stack based buffer
1776 overflows (that need to overwrite this return address) now also
1777 overwrite the canary, which gets detected and the attack is then
1778 neutralized via a kernel panic.
1779 This feature requires gcc version 4.2 or above.
1781 config DEPRECATED_PARAM_STRUCT
1782 bool "Provide old way to pass kernel parameters"
1784 This was deprecated in 2001 and announced to live on for 5 years.
1785 Some old boot loaders still use this way.
1792 bool "Flattened Device Tree support"
1794 select OF_EARLY_FLATTREE
1797 Include support for flattened device tree machine descriptions.
1799 # Compressed boot loader in ROM. Yes, we really want to ask about
1800 # TEXT and BSS so we preserve their values in the config files.
1801 config ZBOOT_ROM_TEXT
1802 hex "Compressed ROM boot loader base address"
1805 The physical address at which the ROM-able zImage is to be
1806 placed in the target. Platforms which normally make use of
1807 ROM-able zImage formats normally set this to a suitable
1808 value in their defconfig file.
1810 If ZBOOT_ROM is not enabled, this has no effect.
1812 config ZBOOT_ROM_BSS
1813 hex "Compressed ROM boot loader BSS address"
1816 The base address of an area of read/write memory in the target
1817 for the ROM-able zImage which must be available while the
1818 decompressor is running. It must be large enough to hold the
1819 entire decompressed kernel plus an additional 128 KiB.
1820 Platforms which normally make use of ROM-able zImage formats
1821 normally set this to a suitable value in their defconfig file.
1823 If ZBOOT_ROM is not enabled, this has no effect.
1826 bool "Compressed boot loader in ROM/flash"
1827 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1829 Say Y here if you intend to execute your compressed kernel image
1830 (zImage) directly from ROM or flash. If unsure, say N.
1833 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1834 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1835 default ZBOOT_ROM_NONE
1837 Include experimental SD/MMC loading code in the ROM-able zImage.
1838 With this enabled it is possible to write the the ROM-able zImage
1839 kernel image to an MMC or SD card and boot the kernel straight
1840 from the reset vector. At reset the processor Mask ROM will load
1841 the first part of the the ROM-able zImage which in turn loads the
1842 rest the kernel image to RAM.
1844 config ZBOOT_ROM_NONE
1845 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1847 Do not load image from SD or MMC
1849 config ZBOOT_ROM_MMCIF
1850 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1852 Load image from MMCIF hardware block.
1854 config ZBOOT_ROM_SH_MOBILE_SDHI
1855 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1857 Load image from SDHI hardware block
1861 config ARM_APPENDED_DTB
1862 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1863 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1865 With this option, the boot code will look for a device tree binary
1866 (DTB) appended to zImage
1867 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1869 This is meant as a backward compatibility convenience for those
1870 systems with a bootloader that can't be upgraded to accommodate
1871 the documented boot protocol using a device tree.
1873 Beware that there is very little in terms of protection against
1874 this option being confused by leftover garbage in memory that might
1875 look like a DTB header after a reboot if no actual DTB is appended
1876 to zImage. Do not leave this option active in a production kernel
1877 if you don't intend to always append a DTB. Proper passing of the
1878 location into r2 of a bootloader provided DTB is always preferable
1881 config ARM_ATAG_DTB_COMPAT
1882 bool "Supplement the appended DTB with traditional ATAG information"
1883 depends on ARM_APPENDED_DTB
1885 Some old bootloaders can't be updated to a DTB capable one, yet
1886 they provide ATAGs with memory configuration, the ramdisk address,
1887 the kernel cmdline string, etc. Such information is dynamically
1888 provided by the bootloader and can't always be stored in a static
1889 DTB. To allow a device tree enabled kernel to be used with such
1890 bootloaders, this option allows zImage to extract the information
1891 from the ATAG list and store it at run time into the appended DTB.
1894 string "Default kernel command string"
1897 On some architectures (EBSA110 and CATS), there is currently no way
1898 for the boot loader to pass arguments to the kernel. For these
1899 architectures, you should supply some command-line options at build
1900 time by entering them here. As a minimum, you should specify the
1901 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1904 prompt "Kernel command line type" if CMDLINE != ""
1905 default CMDLINE_FROM_BOOTLOADER
1907 config CMDLINE_FROM_BOOTLOADER
1908 bool "Use bootloader kernel arguments if available"
1910 Uses the command-line options passed by the boot loader. If
1911 the boot loader doesn't provide any, the default kernel command
1912 string provided in CMDLINE will be used.
1914 config CMDLINE_EXTEND
1915 bool "Extend bootloader kernel arguments"
1917 The command-line arguments provided by the boot loader will be
1918 appended to the default kernel command string.
1920 config CMDLINE_FORCE
1921 bool "Always use the default kernel command string"
1923 Always use the default kernel command string, even if the boot
1924 loader passes other arguments to the kernel.
1925 This is useful if you cannot or don't want to change the
1926 command-line options your boot loader passes to the kernel.
1930 bool "Kernel Execute-In-Place from ROM"
1931 depends on !ZBOOT_ROM
1933 Execute-In-Place allows the kernel to run from non-volatile storage
1934 directly addressable by the CPU, such as NOR flash. This saves RAM
1935 space since the text section of the kernel is not loaded from flash
1936 to RAM. Read-write sections, such as the data section and stack,
1937 are still copied to RAM. The XIP kernel is not compressed since
1938 it has to run directly from flash, so it will take more space to
1939 store it. The flash address used to link the kernel object files,
1940 and for storing it, is configuration dependent. Therefore, if you
1941 say Y here, you must know the proper physical address where to
1942 store the kernel image depending on your own flash memory usage.
1944 Also note that the make target becomes "make xipImage" rather than
1945 "make zImage" or "make Image". The final kernel binary to put in
1946 ROM memory will be arch/arm/boot/xipImage.
1950 config XIP_PHYS_ADDR
1951 hex "XIP Kernel Physical Location"
1952 depends on XIP_KERNEL
1953 default "0x00080000"
1955 This is the physical address in your flash memory the kernel will
1956 be linked for and stored to. This address is dependent on your
1960 bool "Kexec system call (EXPERIMENTAL)"
1961 depends on EXPERIMENTAL
1963 kexec is a system call that implements the ability to shutdown your
1964 current kernel, and to start another kernel. It is like a reboot
1965 but it is independent of the system firmware. And like a reboot
1966 you can start any kernel with it, not just Linux.
1968 It is an ongoing process to be certain the hardware in a machine
1969 is properly shutdown, so do not be surprised if this code does not
1970 initially work for you. It may help to enable device hotplugging
1974 bool "Export atags in procfs"
1978 Should the atags used to boot the kernel be exported in an "atags"
1979 file in procfs. Useful with kexec.
1982 bool "Build kdump crash kernel (EXPERIMENTAL)"
1983 depends on EXPERIMENTAL
1985 Generate crash dump after being started by kexec. This should
1986 be normally only set in special crash dump kernels which are
1987 loaded in the main kernel with kexec-tools into a specially
1988 reserved region and then later executed after a crash by
1989 kdump/kexec. The crash dump kernel must be compiled to a
1990 memory address not used by the main kernel
1992 For more details see Documentation/kdump/kdump.txt
1994 config AUTO_ZRELADDR
1995 bool "Auto calculation of the decompressed kernel image address"
1996 depends on !ZBOOT_ROM && !ARCH_U300
1998 ZRELADDR is the physical address where the decompressed kernel
1999 image will be placed. If AUTO_ZRELADDR is selected, the address
2000 will be determined at run-time by masking the current IP with
2001 0xf8000000. This assumes the zImage being placed in the first 128MB
2002 from start of memory.
2006 menu "CPU Power Management"
2010 source "drivers/cpufreq/Kconfig"
2013 tristate "CPUfreq driver for i.MX CPUs"
2014 depends on ARCH_MXC && CPU_FREQ
2016 This enables the CPUfreq driver for i.MX CPUs.
2018 config CPU_FREQ_SA1100
2021 config CPU_FREQ_SA1110
2024 config CPU_FREQ_INTEGRATOR
2025 tristate "CPUfreq driver for ARM Integrator CPUs"
2026 depends on ARCH_INTEGRATOR && CPU_FREQ
2029 This enables the CPUfreq driver for ARM Integrator CPUs.
2031 For details, take a look at <file:Documentation/cpu-freq>.
2037 depends on CPU_FREQ && ARCH_PXA && PXA25x
2039 select CPU_FREQ_TABLE
2040 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2045 Internal configuration node for common cpufreq on Samsung SoC
2047 config CPU_FREQ_S3C24XX
2048 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2049 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2052 This enables the CPUfreq driver for the Samsung S3C24XX family
2055 For details, take a look at <file:Documentation/cpu-freq>.
2059 config CPU_FREQ_S3C24XX_PLL
2060 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2061 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2063 Compile in support for changing the PLL frequency from the
2064 S3C24XX series CPUfreq driver. The PLL takes time to settle
2065 after a frequency change, so by default it is not enabled.
2067 This also means that the PLL tables for the selected CPU(s) will
2068 be built which may increase the size of the kernel image.
2070 config CPU_FREQ_S3C24XX_DEBUG
2071 bool "Debug CPUfreq Samsung driver core"
2072 depends on CPU_FREQ_S3C24XX
2074 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2076 config CPU_FREQ_S3C24XX_IODEBUG
2077 bool "Debug CPUfreq Samsung driver IO timing"
2078 depends on CPU_FREQ_S3C24XX
2080 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2082 config CPU_FREQ_S3C24XX_DEBUGFS
2083 bool "Export debugfs for CPUFreq"
2084 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2086 Export status information via debugfs.
2090 source "drivers/cpuidle/Kconfig"
2094 menu "Floating point emulation"
2096 comment "At least one emulation must be selected"
2099 bool "NWFPE math emulation"
2100 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2102 Say Y to include the NWFPE floating point emulator in the kernel.
2103 This is necessary to run most binaries. Linux does not currently
2104 support floating point hardware so you need to say Y here even if
2105 your machine has an FPA or floating point co-processor podule.
2107 You may say N here if you are going to load the Acorn FPEmulator
2108 early in the bootup.
2111 bool "Support extended precision"
2112 depends on FPE_NWFPE
2114 Say Y to include 80-bit support in the kernel floating-point
2115 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2116 Note that gcc does not generate 80-bit operations by default,
2117 so in most cases this option only enlarges the size of the
2118 floating point emulator without any good reason.
2120 You almost surely want to say N here.
2123 bool "FastFPE math emulation (EXPERIMENTAL)"
2124 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2126 Say Y here to include the FAST floating point emulator in the kernel.
2127 This is an experimental much faster emulator which now also has full
2128 precision for the mantissa. It does not support any exceptions.
2129 It is very simple, and approximately 3-6 times faster than NWFPE.
2131 It should be sufficient for most programs. It may be not suitable
2132 for scientific calculations, but you have to check this for yourself.
2133 If you do not feel you need a faster FP emulation you should better
2137 bool "VFP-format floating point maths"
2138 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2140 Say Y to include VFP support code in the kernel. This is needed
2141 if your hardware includes a VFP unit.
2143 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2144 release notes and additional status information.
2146 Say N if your target does not have VFP hardware.
2154 bool "Advanced SIMD (NEON) Extension support"
2155 depends on VFPv3 && CPU_V7
2157 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2162 menu "Userspace binary formats"
2164 source "fs/Kconfig.binfmt"
2167 tristate "RISC OS personality"
2170 Say Y here to include the kernel code necessary if you want to run
2171 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2172 experimental; if this sounds frightening, say N and sleep in peace.
2173 You can also say M here to compile this support as a module (which
2174 will be called arthur).
2178 menu "Power management options"
2180 source "kernel/power/Kconfig"
2182 config ARCH_SUSPEND_POSSIBLE
2183 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2184 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2185 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2188 config ARM_CPU_SUSPEND
2193 source "net/Kconfig"
2195 source "drivers/Kconfig"
2199 source "arch/arm/Kconfig.debug"
2201 source "security/Kconfig"
2203 source "crypto/Kconfig"
2205 source "lib/Kconfig"