4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
28 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
30 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
31 select HAVE_ARCH_TRACEHOOK
33 select HAVE_CC_STACKPROTECTOR
34 select HAVE_CONTEXT_TRACKING
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_DEBUG_KMEMLEAK
37 select HAVE_DMA_API_DEBUG
39 select HAVE_DMA_CONTIGUOUS if MMU
40 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
41 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
42 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
43 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
44 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
45 select HAVE_GENERIC_DMA_COHERENT
46 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
47 select HAVE_IDE if PCI || ISA || PCMCIA
48 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_KERNEL_GZIP
50 select HAVE_KERNEL_LZ4
51 select HAVE_KERNEL_LZMA
52 select HAVE_KERNEL_LZO
54 select HAVE_KPROBES if !XIP_KERNEL
55 select HAVE_KRETPROBES if (HAVE_KPROBES)
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
59 select HAVE_PERF_EVENTS
61 select HAVE_PERF_USER_STACK_DUMP
62 select HAVE_REGS_AND_STACK_ACCESS_API
63 select HAVE_SYSCALL_TRACEPOINTS
65 select HAVE_VIRT_CPU_ACCOUNTING_GEN
66 select IRQ_FORCED_THREADING
68 select MODULES_USE_ELF_REL
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
88 config NEED_SG_DMA_LENGTH
91 config ARM_DMA_USE_IOMMU
93 select ARM_HAS_SG_CHAIN
94 select NEED_SG_DMA_LENGTH
98 config ARM_DMA_IOMMU_ALIGNMENT
99 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
103 DMA mapping framework by default aligns all buffers to the smallest
104 PAGE_SIZE order which is greater than or equal to the requested buffer
105 size. This works well for buffers up to a few hundreds kilobytes, but
106 for larger buffers it just a waste of address space. Drivers which has
107 relatively small addressing window (like 64Mib) might run out of
108 virtual space with just a few allocations.
110 With this parameter you can specify the maximum PAGE_SIZE order for
111 DMA IOMMU buffers. Larger buffers will be aligned only to this
112 specified order. The order is expressed as a power of two multiplied
117 config MIGHT_HAVE_PCI
120 config SYS_SUPPORTS_APM_EMULATION
125 select GENERIC_ALLOCATOR
136 The Extended Industry Standard Architecture (EISA) bus was
137 developed as an open alternative to the IBM MicroChannel bus.
139 The EISA bus provided some of the features of the IBM MicroChannel
140 bus while maintaining backward compatibility with cards made for
141 the older ISA bus. The EISA bus saw limited use between 1988 and
142 1995 when it was made obsolete by the PCI bus.
144 Say Y here if you are building a kernel for an EISA-based machine.
151 config STACKTRACE_SUPPORT
155 config HAVE_LATENCYTOP_SUPPORT
160 config LOCKDEP_SUPPORT
164 config TRACE_IRQFLAGS_SUPPORT
168 config RWSEM_GENERIC_SPINLOCK
172 config RWSEM_XCHGADD_ALGORITHM
175 config ARCH_HAS_ILOG2_U32
178 config ARCH_HAS_ILOG2_U64
181 config ARCH_HAS_CPUFREQ
184 Internal node to signify that the ARCH has CPUFREQ support
185 and that the relevant menu configurations are displayed for
188 config ARCH_HAS_BANDGAP
191 config GENERIC_HWEIGHT
195 config GENERIC_CALIBRATE_DELAY
199 config ARCH_MAY_HAVE_PC_FDC
205 config NEED_DMA_MAP_STATE
208 config ARCH_SUPPORTS_UPROBES
211 config ARCH_HAS_DMA_SET_COHERENT_MASK
214 config GENERIC_ISA_DMA
220 config NEED_RET_TO_USER
228 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
229 default DRAM_BASE if REMAP_VECTORS_TO_RAM
232 The base address of exception vectors. This must be two pages
235 config ARM_PATCH_PHYS_VIRT
236 bool "Patch physical to virtual translations at runtime" if EMBEDDED
238 depends on !XIP_KERNEL && MMU
239 depends on !ARCH_REALVIEW || !SPARSEMEM
241 Patch phys-to-virt and virt-to-phys translation functions at
242 boot and module load time according to the position of the
243 kernel in system memory.
245 This can only be used with non-XIP MMU kernels where the base
246 of physical memory is at a 16MB boundary.
248 Only disable this option if you know that you do not require
249 this feature (eg, building a kernel for a single machine) and
250 you need to shrink the kernel to the minimal size.
252 config NEED_MACH_GPIO_H
255 Select this when mach/gpio.h is required to provide special
256 definitions for this platform. The need for mach/gpio.h should
257 be avoided when possible.
259 config NEED_MACH_IO_H
262 Select this when mach/io.h is required to provide special
263 definitions for this platform. The need for mach/io.h should
264 be avoided when possible.
266 config NEED_MACH_MEMORY_H
269 Select this when mach/memory.h is required to provide special
270 definitions for this platform. The need for mach/memory.h should
271 be avoided when possible.
274 hex "Physical address of main memory" if MMU
275 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
276 default DRAM_BASE if !MMU
278 Please provide the physical address corresponding to the
279 location of main memory in your system.
285 source "init/Kconfig"
287 source "kernel/Kconfig.freezer"
292 bool "MMU-based Paged Memory Management Support"
295 Select if you want MMU-based virtualised addressing space
296 support by paged memory management. If unsure, say 'Y'.
299 # The "ARM system type" choice list is ordered alphabetically by option
300 # text. Please add new entries in the option alphabetic order.
303 prompt "ARM system type"
304 default ARCH_VERSATILE if !MMU
305 default ARCH_MULTIPLATFORM if MMU
307 config ARCH_MULTIPLATFORM
308 bool "Allow multiple platforms to be selected"
310 select ARCH_WANT_OPTIONAL_GPIOLIB
311 select ARM_HAS_SG_CHAIN
312 select ARM_PATCH_PHYS_VIRT
316 select GENERIC_CLOCKEVENTS
317 select MULTI_IRQ_HANDLER
321 config ARCH_INTEGRATOR
322 bool "ARM Ltd. Integrator family"
323 select ARCH_HAS_CPUFREQ
325 select ARM_PATCH_PHYS_VIRT
328 select COMMON_CLK_VERSATILE
329 select GENERIC_CLOCKEVENTS
332 select MULTI_IRQ_HANDLER
333 select NEED_MACH_MEMORY_H
334 select PLAT_VERSATILE
337 select VERSATILE_FPGA_IRQ
339 Support for ARM's Integrator platform.
342 bool "ARM Ltd. RealView family"
343 select ARCH_WANT_OPTIONAL_GPIOLIB
345 select ARM_TIMER_SP804
347 select COMMON_CLK_VERSATILE
348 select GENERIC_CLOCKEVENTS
349 select GPIO_PL061 if GPIOLIB
351 select NEED_MACH_MEMORY_H
352 select PLAT_VERSATILE
353 select PLAT_VERSATILE_CLCD
355 This enables support for ARM Ltd RealView boards.
357 config ARCH_VERSATILE
358 bool "ARM Ltd. Versatile family"
359 select ARCH_WANT_OPTIONAL_GPIOLIB
361 select ARM_TIMER_SP804
364 select GENERIC_CLOCKEVENTS
365 select HAVE_MACH_CLKDEV
367 select PLAT_VERSATILE
368 select PLAT_VERSATILE_CLCD
369 select PLAT_VERSATILE_CLOCK
370 select VERSATILE_FPGA_IRQ
372 This enables support for ARM Ltd Versatile board.
376 select ARCH_REQUIRE_GPIOLIB
379 select NEED_MACH_GPIO_H
380 select NEED_MACH_IO_H if PCCARD
382 select PINCTRL_AT91 if USE_OF
384 This enables support for systems based on Atmel
385 AT91RM9200 and AT91SAM9* processors.
388 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
389 select ARCH_REQUIRE_GPIOLIB
394 select GENERIC_CLOCKEVENTS
397 Support for Cirrus Logic 711x/721x/731x based boards.
400 bool "Cortina Systems Gemini"
401 select ARCH_REQUIRE_GPIOLIB
404 select GENERIC_CLOCKEVENTS
406 Support for the Cortina Systems Gemini family SoCs
410 select ARCH_USES_GETTIMEOFFSET
413 select NEED_MACH_IO_H
414 select NEED_MACH_MEMORY_H
417 This is an evaluation board for the StrongARM processor available
418 from Digital. It has limited hardware on-board, including an
419 Ethernet interface, two PCMCIA sockets, two serial ports and a
423 bool "Energy Micro efm32"
425 select ARCH_REQUIRE_GPIOLIB
431 select GENERIC_CLOCKEVENTS
437 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
442 select ARCH_HAS_HOLES_MEMORYMODEL
443 select ARCH_REQUIRE_GPIOLIB
444 select ARCH_USES_GETTIMEOFFSET
449 select NEED_MACH_MEMORY_H
451 This enables support for the Cirrus EP93xx series of CPUs.
453 config ARCH_FOOTBRIDGE
457 select GENERIC_CLOCKEVENTS
459 select NEED_MACH_IO_H if !MMU
460 select NEED_MACH_MEMORY_H
462 Support for systems based on the DC21285 companion chip
463 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
466 bool "Hilscher NetX based"
470 select GENERIC_CLOCKEVENTS
472 This enables support for systems based on the Hilscher NetX Soc
478 select NEED_MACH_MEMORY_H
479 select NEED_RET_TO_USER
484 Support for Intel's IOP13XX (XScale) family of processors.
489 select ARCH_REQUIRE_GPIOLIB
492 select NEED_RET_TO_USER
496 Support for Intel's 80219 and IOP32X (XScale) family of
502 select ARCH_REQUIRE_GPIOLIB
505 select NEED_RET_TO_USER
509 Support for Intel's IOP33X (XScale) family of processors.
514 select ARCH_HAS_DMA_SET_COHERENT_MASK
515 select ARCH_REQUIRE_GPIOLIB
516 select ARCH_SUPPORTS_BIG_ENDIAN
519 select DMABOUNCE if PCI
520 select GENERIC_CLOCKEVENTS
521 select MIGHT_HAVE_PCI
522 select NEED_MACH_IO_H
523 select USB_EHCI_BIG_ENDIAN_DESC
524 select USB_EHCI_BIG_ENDIAN_MMIO
526 Support for Intel's IXP4XX (XScale) family of processors.
530 select ARCH_REQUIRE_GPIOLIB
532 select GENERIC_CLOCKEVENTS
533 select MIGHT_HAVE_PCI
537 select PLAT_ORION_LEGACY
539 Support for the Marvell Dove SoC 88AP510
542 bool "Marvell Kirkwood"
543 select ARCH_HAS_CPUFREQ
544 select ARCH_REQUIRE_GPIOLIB
546 select GENERIC_CLOCKEVENTS
551 select PINCTRL_KIRKWOOD
552 select PLAT_ORION_LEGACY
554 Support for the following Marvell Kirkwood series SoCs:
555 88F6180, 88F6192 and 88F6281.
558 bool "Marvell MV78xx0"
559 select ARCH_REQUIRE_GPIOLIB
561 select GENERIC_CLOCKEVENTS
564 select PLAT_ORION_LEGACY
566 Support for the following Marvell MV78xx0 series SoCs:
572 select ARCH_REQUIRE_GPIOLIB
574 select GENERIC_CLOCKEVENTS
577 select PLAT_ORION_LEGACY
579 Support for the following Marvell Orion 5x series SoCs:
580 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
581 Orion-2 (5281), Orion-1-90 (6183).
584 bool "Marvell PXA168/910/MMP2"
586 select ARCH_REQUIRE_GPIOLIB
588 select GENERIC_ALLOCATOR
589 select GENERIC_CLOCKEVENTS
592 select MULTI_IRQ_HANDLER
597 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
600 bool "Micrel/Kendin KS8695"
601 select ARCH_REQUIRE_GPIOLIB
604 select GENERIC_CLOCKEVENTS
605 select NEED_MACH_MEMORY_H
607 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
608 System-on-Chip devices.
611 bool "Nuvoton W90X900 CPU"
612 select ARCH_REQUIRE_GPIOLIB
616 select GENERIC_CLOCKEVENTS
618 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
619 At present, the w90x900 has been renamed nuc900, regarding
620 the ARM series product line, you can login the following
621 link address to know more.
623 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
624 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
628 select ARCH_REQUIRE_GPIOLIB
633 select GENERIC_CLOCKEVENTS
637 Support for the NXP LPC32XX family of processors
640 bool "PXA2xx/PXA3xx-based"
642 select ARCH_HAS_CPUFREQ
644 select ARCH_REQUIRE_GPIOLIB
645 select ARM_CPU_SUSPEND if PM
649 select GENERIC_CLOCKEVENTS
652 select MULTI_IRQ_HANDLER
656 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
659 bool "Qualcomm MSM (non-multiplatform)"
660 select ARCH_REQUIRE_GPIOLIB
662 select GENERIC_CLOCKEVENTS
664 Support for Qualcomm MSM/QSD based systems. This runs on the
665 apps processor of the MSM/QSD and depends on a shared memory
666 interface to the modem processor which runs the baseband
667 stack and controls some vital subsystems
668 (clock and power control, etc).
670 config ARCH_SHMOBILE_LEGACY
671 bool "Renesas ARM SoCs (non-multiplatform)"
673 select ARM_PATCH_PHYS_VIRT
675 select GENERIC_CLOCKEVENTS
676 select HAVE_ARM_SCU if SMP
677 select HAVE_ARM_TWD if SMP
678 select HAVE_MACH_CLKDEV
680 select MIGHT_HAVE_CACHE_L2X0
681 select MULTI_IRQ_HANDLER
684 select PM_GENERIC_DOMAINS if PM
687 Support for Renesas ARM SoC platforms using a non-multiplatform
688 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
694 select ARCH_MAY_HAVE_PC_FDC
695 select ARCH_SPARSEMEM_ENABLE
696 select ARCH_USES_GETTIMEOFFSET
700 select HAVE_PATA_PLATFORM
702 select NEED_MACH_IO_H
703 select NEED_MACH_MEMORY_H
707 On the Acorn Risc-PC, Linux can support the internal IDE disk and
708 CD-ROM interface, serial and parallel port, and the floppy drive.
712 select ARCH_HAS_CPUFREQ
714 select ARCH_REQUIRE_GPIOLIB
715 select ARCH_SPARSEMEM_ENABLE
720 select GENERIC_CLOCKEVENTS
723 select NEED_MACH_MEMORY_H
726 Support for StrongARM 11x0 based boards.
729 bool "Samsung S3C24XX SoCs"
730 select ARCH_HAS_CPUFREQ
731 select ARCH_REQUIRE_GPIOLIB
734 select CLKSRC_SAMSUNG_PWM
735 select GENERIC_CLOCKEVENTS
737 select HAVE_S3C2410_I2C if I2C
738 select HAVE_S3C2410_WATCHDOG if WATCHDOG
739 select HAVE_S3C_RTC if RTC_CLASS
740 select MULTI_IRQ_HANDLER
741 select NEED_MACH_IO_H
744 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
745 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
746 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
747 Samsung SMDK2410 development board (and derivatives).
750 bool "Samsung S3C64XX"
751 select ARCH_HAS_CPUFREQ
752 select ARCH_REQUIRE_GPIOLIB
757 select CLKSRC_SAMSUNG_PWM
758 select COMMON_CLK_SAMSUNG
760 select GENERIC_CLOCKEVENTS
762 select HAVE_S3C2410_I2C if I2C
763 select HAVE_S3C2410_WATCHDOG if WATCHDOG
767 select PM_GENERIC_DOMAINS if PM
769 select S3C_GPIO_TRACK
771 select SAMSUNG_WAKEMASK
772 select SAMSUNG_WDT_RESET
774 Samsung S3C64XX series based systems
777 bool "Samsung S5P6440 S5P6450"
780 select CLKSRC_SAMSUNG_PWM
782 select GENERIC_CLOCKEVENTS
784 select HAVE_S3C2410_I2C if I2C
785 select HAVE_S3C2410_WATCHDOG if WATCHDOG
786 select HAVE_S3C_RTC if RTC_CLASS
787 select NEED_MACH_GPIO_H
789 select SAMSUNG_WDT_RESET
791 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
795 bool "Samsung S5PC100"
796 select ARCH_REQUIRE_GPIOLIB
799 select CLKSRC_SAMSUNG_PWM
801 select GENERIC_CLOCKEVENTS
803 select HAVE_S3C2410_I2C if I2C
804 select HAVE_S3C2410_WATCHDOG if WATCHDOG
805 select HAVE_S3C_RTC if RTC_CLASS
806 select NEED_MACH_GPIO_H
808 select SAMSUNG_WDT_RESET
810 Samsung S5PC100 series based systems
813 bool "Samsung S5PV210/S5PC110"
814 select ARCH_HAS_CPUFREQ
815 select ARCH_HAS_HOLES_MEMORYMODEL
816 select ARCH_SPARSEMEM_ENABLE
819 select CLKSRC_SAMSUNG_PWM
821 select GENERIC_CLOCKEVENTS
823 select HAVE_S3C2410_I2C if I2C
824 select HAVE_S3C2410_WATCHDOG if WATCHDOG
825 select HAVE_S3C_RTC if RTC_CLASS
826 select NEED_MACH_GPIO_H
827 select NEED_MACH_MEMORY_H
830 Samsung S5PV210/S5PC110 series based systems
833 bool "Samsung EXYNOS"
834 select ARCH_HAS_BANDGAP
835 select ARCH_HAS_CPUFREQ
836 select ARCH_HAS_HOLES_MEMORYMODEL
837 select ARCH_REQUIRE_GPIOLIB
838 select ARCH_SPARSEMEM_ENABLE
842 select COMMON_CLK_SAMSUNG
844 select GENERIC_CLOCKEVENTS
845 select HAVE_ARM_SCU if SMP
846 select HAVE_S3C2410_I2C if I2C
847 select HAVE_S3C2410_WATCHDOG if WATCHDOG
848 select HAVE_S3C_RTC if RTC_CLASS
850 select NEED_MACH_MEMORY_H
852 select PINCTRL_EXYNOS
853 select PM_GENERIC_DOMAINS if PM_RUNTIME
855 select SAMSUNG_DMADEV
859 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
863 select ARCH_HAS_HOLES_MEMORYMODEL
864 select ARCH_REQUIRE_GPIOLIB
866 select GENERIC_ALLOCATOR
867 select GENERIC_CLOCKEVENTS
868 select GENERIC_IRQ_CHIP
874 Support for TI's DaVinci platform.
879 select ARCH_HAS_CPUFREQ
880 select ARCH_HAS_HOLES_MEMORYMODEL
882 select ARCH_REQUIRE_GPIOLIB
885 select GENERIC_CLOCKEVENTS
886 select GENERIC_IRQ_CHIP
889 select NEED_MACH_IO_H if PCCARD
890 select NEED_MACH_MEMORY_H
892 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
896 menu "Multiple platform selection"
897 depends on ARCH_MULTIPLATFORM
899 comment "CPU Core family selection"
902 bool "ARMv4 based platforms (FA526)"
903 depends on !ARCH_MULTI_V6_V7
904 select ARCH_MULTI_V4_V5
907 config ARCH_MULTI_V4T
908 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
909 depends on !ARCH_MULTI_V6_V7
910 select ARCH_MULTI_V4_V5
911 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
912 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
913 CPU_ARM925T || CPU_ARM940T)
916 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
917 depends on !ARCH_MULTI_V6_V7
918 select ARCH_MULTI_V4_V5
919 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
920 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
921 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
923 config ARCH_MULTI_V4_V5
927 bool "ARMv6 based platforms (ARM11)"
928 select ARCH_MULTI_V6_V7
932 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
934 select ARCH_MULTI_V6_V7
938 config ARCH_MULTI_V6_V7
940 select MIGHT_HAVE_CACHE_L2X0
942 config ARCH_MULTI_CPU_AUTO
943 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
949 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
953 select HAVE_ARM_ARCH_TIMER
956 # This is sorted alphabetically by mach-* pathname. However, plat-*
957 # Kconfigs may be included either alphabetically (according to the
958 # plat- suffix) or along side the corresponding mach-* source.
960 source "arch/arm/mach-mvebu/Kconfig"
962 source "arch/arm/mach-at91/Kconfig"
964 source "arch/arm/mach-bcm/Kconfig"
966 source "arch/arm/mach-berlin/Kconfig"
968 source "arch/arm/mach-clps711x/Kconfig"
970 source "arch/arm/mach-cns3xxx/Kconfig"
972 source "arch/arm/mach-davinci/Kconfig"
974 source "arch/arm/mach-dove/Kconfig"
976 source "arch/arm/mach-ep93xx/Kconfig"
978 source "arch/arm/mach-footbridge/Kconfig"
980 source "arch/arm/mach-gemini/Kconfig"
982 source "arch/arm/mach-highbank/Kconfig"
984 source "arch/arm/mach-hisi/Kconfig"
986 source "arch/arm/mach-integrator/Kconfig"
988 source "arch/arm/mach-iop32x/Kconfig"
990 source "arch/arm/mach-iop33x/Kconfig"
992 source "arch/arm/mach-iop13xx/Kconfig"
994 source "arch/arm/mach-ixp4xx/Kconfig"
996 source "arch/arm/mach-keystone/Kconfig"
998 source "arch/arm/mach-kirkwood/Kconfig"
1000 source "arch/arm/mach-ks8695/Kconfig"
1002 source "arch/arm/mach-msm/Kconfig"
1004 source "arch/arm/mach-moxart/Kconfig"
1006 source "arch/arm/mach-mv78xx0/Kconfig"
1008 source "arch/arm/mach-imx/Kconfig"
1010 source "arch/arm/mach-mxs/Kconfig"
1012 source "arch/arm/mach-netx/Kconfig"
1014 source "arch/arm/mach-nomadik/Kconfig"
1016 source "arch/arm/mach-nspire/Kconfig"
1018 source "arch/arm/plat-omap/Kconfig"
1020 source "arch/arm/mach-omap1/Kconfig"
1022 source "arch/arm/mach-omap2/Kconfig"
1024 source "arch/arm/mach-orion5x/Kconfig"
1026 source "arch/arm/mach-picoxcell/Kconfig"
1028 source "arch/arm/mach-pxa/Kconfig"
1029 source "arch/arm/plat-pxa/Kconfig"
1031 source "arch/arm/mach-mmp/Kconfig"
1033 source "arch/arm/mach-qcom/Kconfig"
1035 source "arch/arm/mach-realview/Kconfig"
1037 source "arch/arm/mach-rockchip/Kconfig"
1039 source "arch/arm/mach-sa1100/Kconfig"
1041 source "arch/arm/plat-samsung/Kconfig"
1043 source "arch/arm/mach-socfpga/Kconfig"
1045 source "arch/arm/mach-spear/Kconfig"
1047 source "arch/arm/mach-sti/Kconfig"
1049 source "arch/arm/mach-s3c24xx/Kconfig"
1051 source "arch/arm/mach-s3c64xx/Kconfig"
1053 source "arch/arm/mach-s5p64x0/Kconfig"
1055 source "arch/arm/mach-s5pc100/Kconfig"
1057 source "arch/arm/mach-s5pv210/Kconfig"
1059 source "arch/arm/mach-exynos/Kconfig"
1061 source "arch/arm/mach-shmobile/Kconfig"
1063 source "arch/arm/mach-sunxi/Kconfig"
1065 source "arch/arm/mach-prima2/Kconfig"
1067 source "arch/arm/mach-tegra/Kconfig"
1069 source "arch/arm/mach-u300/Kconfig"
1071 source "arch/arm/mach-ux500/Kconfig"
1073 source "arch/arm/mach-versatile/Kconfig"
1075 source "arch/arm/mach-vexpress/Kconfig"
1076 source "arch/arm/plat-versatile/Kconfig"
1078 source "arch/arm/mach-vt8500/Kconfig"
1080 source "arch/arm/mach-w90x900/Kconfig"
1082 source "arch/arm/mach-zynq/Kconfig"
1084 # Definitions to make life easier
1090 select GENERIC_CLOCKEVENTS
1096 select GENERIC_IRQ_CHIP
1099 config PLAT_ORION_LEGACY
1106 config PLAT_VERSATILE
1109 config ARM_TIMER_SP804
1112 select CLKSRC_OF if OF
1114 source "arch/arm/firmware/Kconfig"
1116 source arch/arm/mm/Kconfig
1120 default 16 if ARCH_EP93XX
1124 bool "Enable iWMMXt support"
1125 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1126 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1128 Enable support for iWMMXt context switching at run time if
1129 running on a CPU that supports it.
1131 config MULTI_IRQ_HANDLER
1134 Allow each machine to specify it's own IRQ handler at run time.
1137 source "arch/arm/Kconfig-nommu"
1140 config PJ4B_ERRATA_4742
1141 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1142 depends on CPU_PJ4B && MACH_ARMADA_370
1145 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1146 Event (WFE) IDLE states, a specific timing sensitivity exists between
1147 the retiring WFI/WFE instructions and the newly issued subsequent
1148 instructions. This sensitivity can result in a CPU hang scenario.
1150 The software must insert either a Data Synchronization Barrier (DSB)
1151 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1154 config ARM_ERRATA_326103
1155 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1158 Executing a SWP instruction to read-only memory does not set bit 11
1159 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1160 treat the access as a read, preventing a COW from occurring and
1161 causing the faulting task to livelock.
1163 config ARM_ERRATA_411920
1164 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1165 depends on CPU_V6 || CPU_V6K
1167 Invalidation of the Instruction Cache operation can
1168 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1169 It does not affect the MPCore. This option enables the ARM Ltd.
1170 recommended workaround.
1172 config ARM_ERRATA_430973
1173 bool "ARM errata: Stale prediction on replaced interworking branch"
1176 This option enables the workaround for the 430973 Cortex-A8
1177 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1178 interworking branch is replaced with another code sequence at the
1179 same virtual address, whether due to self-modifying code or virtual
1180 to physical address re-mapping, Cortex-A8 does not recover from the
1181 stale interworking branch prediction. This results in Cortex-A8
1182 executing the new code sequence in the incorrect ARM or Thumb state.
1183 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1184 and also flushes the branch target cache at every context switch.
1185 Note that setting specific bits in the ACTLR register may not be
1186 available in non-secure mode.
1188 config ARM_ERRATA_458693
1189 bool "ARM errata: Processor deadlock when a false hazard is created"
1191 depends on !ARCH_MULTIPLATFORM
1193 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1194 erratum. For very specific sequences of memory operations, it is
1195 possible for a hazard condition intended for a cache line to instead
1196 be incorrectly associated with a different cache line. This false
1197 hazard might then cause a processor deadlock. The workaround enables
1198 the L1 caching of the NEON accesses and disables the PLD instruction
1199 in the ACTLR register. Note that setting specific bits in the ACTLR
1200 register may not be available in non-secure mode.
1202 config ARM_ERRATA_460075
1203 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1205 depends on !ARCH_MULTIPLATFORM
1207 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1208 erratum. Any asynchronous access to the L2 cache may encounter a
1209 situation in which recent store transactions to the L2 cache are lost
1210 and overwritten with stale memory contents from external memory. The
1211 workaround disables the write-allocate mode for the L2 cache via the
1212 ACTLR register. Note that setting specific bits in the ACTLR register
1213 may not be available in non-secure mode.
1215 config ARM_ERRATA_742230
1216 bool "ARM errata: DMB operation may be faulty"
1217 depends on CPU_V7 && SMP
1218 depends on !ARCH_MULTIPLATFORM
1220 This option enables the workaround for the 742230 Cortex-A9
1221 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1222 between two write operations may not ensure the correct visibility
1223 ordering of the two writes. This workaround sets a specific bit in
1224 the diagnostic register of the Cortex-A9 which causes the DMB
1225 instruction to behave as a DSB, ensuring the correct behaviour of
1228 config ARM_ERRATA_742231
1229 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1230 depends on CPU_V7 && SMP
1231 depends on !ARCH_MULTIPLATFORM
1233 This option enables the workaround for the 742231 Cortex-A9
1234 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1235 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1236 accessing some data located in the same cache line, may get corrupted
1237 data due to bad handling of the address hazard when the line gets
1238 replaced from one of the CPUs at the same time as another CPU is
1239 accessing it. This workaround sets specific bits in the diagnostic
1240 register of the Cortex-A9 which reduces the linefill issuing
1241 capabilities of the processor.
1243 config PL310_ERRATA_588369
1244 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1245 depends on CACHE_L2X0
1247 The PL310 L2 cache controller implements three types of Clean &
1248 Invalidate maintenance operations: by Physical Address
1249 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1250 They are architecturally defined to behave as the execution of a
1251 clean operation followed immediately by an invalidate operation,
1252 both performing to the same memory location. This functionality
1253 is not correctly implemented in PL310 as clean lines are not
1254 invalidated as a result of these operations.
1256 config ARM_ERRATA_643719
1257 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1258 depends on CPU_V7 && SMP
1260 This option enables the workaround for the 643719 Cortex-A9 (prior to
1261 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1262 register returns zero when it should return one. The workaround
1263 corrects this value, ensuring cache maintenance operations which use
1264 it behave as intended and avoiding data corruption.
1266 config ARM_ERRATA_720789
1267 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1270 This option enables the workaround for the 720789 Cortex-A9 (prior to
1271 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1272 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1273 As a consequence of this erratum, some TLB entries which should be
1274 invalidated are not, resulting in an incoherency in the system page
1275 tables. The workaround changes the TLB flushing routines to invalidate
1276 entries regardless of the ASID.
1278 config PL310_ERRATA_727915
1279 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1280 depends on CACHE_L2X0
1282 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1283 operation (offset 0x7FC). This operation runs in background so that
1284 PL310 can handle normal accesses while it is in progress. Under very
1285 rare circumstances, due to this erratum, write data can be lost when
1286 PL310 treats a cacheable write transaction during a Clean &
1287 Invalidate by Way operation.
1289 config ARM_ERRATA_743622
1290 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1292 depends on !ARCH_MULTIPLATFORM
1294 This option enables the workaround for the 743622 Cortex-A9
1295 (r2p*) erratum. Under very rare conditions, a faulty
1296 optimisation in the Cortex-A9 Store Buffer may lead to data
1297 corruption. This workaround sets a specific bit in the diagnostic
1298 register of the Cortex-A9 which disables the Store Buffer
1299 optimisation, preventing the defect from occurring. This has no
1300 visible impact on the overall performance or power consumption of the
1303 config ARM_ERRATA_751472
1304 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1306 depends on !ARCH_MULTIPLATFORM
1308 This option enables the workaround for the 751472 Cortex-A9 (prior
1309 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1310 completion of a following broadcasted operation if the second
1311 operation is received by a CPU before the ICIALLUIS has completed,
1312 potentially leading to corrupted entries in the cache or TLB.
1314 config PL310_ERRATA_753970
1315 bool "PL310 errata: cache sync operation may be faulty"
1316 depends on CACHE_PL310
1318 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1320 Under some condition the effect of cache sync operation on
1321 the store buffer still remains when the operation completes.
1322 This means that the store buffer is always asked to drain and
1323 this prevents it from merging any further writes. The workaround
1324 is to replace the normal offset of cache sync operation (0x730)
1325 by another offset targeting an unmapped PL310 register 0x740.
1326 This has the same effect as the cache sync operation: store buffer
1327 drain and waiting for all buffers empty.
1329 config ARM_ERRATA_754322
1330 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1333 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1334 r3p*) erratum. A speculative memory access may cause a page table walk
1335 which starts prior to an ASID switch but completes afterwards. This
1336 can populate the micro-TLB with a stale entry which may be hit with
1337 the new ASID. This workaround places two dsb instructions in the mm
1338 switching code so that no page table walks can cross the ASID switch.
1340 config ARM_ERRATA_754327
1341 bool "ARM errata: no automatic Store Buffer drain"
1342 depends on CPU_V7 && SMP
1344 This option enables the workaround for the 754327 Cortex-A9 (prior to
1345 r2p0) erratum. The Store Buffer does not have any automatic draining
1346 mechanism and therefore a livelock may occur if an external agent
1347 continuously polls a memory location waiting to observe an update.
1348 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1349 written polling loops from denying visibility of updates to memory.
1351 config ARM_ERRATA_364296
1352 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1355 This options enables the workaround for the 364296 ARM1136
1356 r0p2 erratum (possible cache data corruption with
1357 hit-under-miss enabled). It sets the undocumented bit 31 in
1358 the auxiliary control register and the FI bit in the control
1359 register, thus disabling hit-under-miss without putting the
1360 processor into full low interrupt latency mode. ARM11MPCore
1363 config ARM_ERRATA_764369
1364 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1365 depends on CPU_V7 && SMP
1367 This option enables the workaround for erratum 764369
1368 affecting Cortex-A9 MPCore with two or more processors (all
1369 current revisions). Under certain timing circumstances, a data
1370 cache line maintenance operation by MVA targeting an Inner
1371 Shareable memory region may fail to proceed up to either the
1372 Point of Coherency or to the Point of Unification of the
1373 system. This workaround adds a DSB instruction before the
1374 relevant cache maintenance functions and sets a specific bit
1375 in the diagnostic control register of the SCU.
1377 config PL310_ERRATA_769419
1378 bool "PL310 errata: no automatic Store Buffer drain"
1379 depends on CACHE_L2X0
1381 On revisions of the PL310 prior to r3p2, the Store Buffer does
1382 not automatically drain. This can cause normal, non-cacheable
1383 writes to be retained when the memory system is idle, leading
1384 to suboptimal I/O performance for drivers using coherent DMA.
1385 This option adds a write barrier to the cpu_idle loop so that,
1386 on systems with an outer cache, the store buffer is drained
1389 config ARM_ERRATA_775420
1390 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1393 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1394 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1395 operation aborts with MMU exception, it might cause the processor
1396 to deadlock. This workaround puts DSB before executing ISB if
1397 an abort may occur on cache maintenance.
1399 config ARM_ERRATA_798181
1400 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1401 depends on CPU_V7 && SMP
1403 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1404 adequately shooting down all use of the old entries. This
1405 option enables the Linux kernel workaround for this erratum
1406 which sends an IPI to the CPUs that are running the same ASID
1407 as the one being invalidated.
1409 config ARM_ERRATA_773022
1410 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1413 This option enables the workaround for the 773022 Cortex-A15
1414 (up to r0p4) erratum. In certain rare sequences of code, the
1415 loop buffer may deliver incorrect instructions. This
1416 workaround disables the loop buffer to avoid the erratum.
1420 source "arch/arm/common/Kconfig"
1430 Find out whether you have ISA slots on your motherboard. ISA is the
1431 name of a bus system, i.e. the way the CPU talks to the other stuff
1432 inside your box. Other bus systems are PCI, EISA, MicroChannel
1433 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1434 newer boards don't support it. If you have ISA, say Y, otherwise N.
1436 # Select ISA DMA controller support
1441 # Select ISA DMA interface
1446 bool "PCI support" if MIGHT_HAVE_PCI
1448 Find out whether you have a PCI motherboard. PCI is the name of a
1449 bus system, i.e. the way the CPU talks to the other stuff inside
1450 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1451 VESA. If you have PCI, say Y, otherwise N.
1457 config PCI_NANOENGINE
1458 bool "BSE nanoEngine PCI support"
1459 depends on SA1100_NANOENGINE
1461 Enable PCI on the BSE nanoEngine board.
1466 config PCI_HOST_ITE8152
1468 depends on PCI && MACH_ARMCORE
1472 source "drivers/pci/Kconfig"
1473 source "drivers/pci/pcie/Kconfig"
1475 source "drivers/pcmcia/Kconfig"
1479 menu "Kernel Features"
1484 This option should be selected by machines which have an SMP-
1487 The only effect of this option is to make the SMP-related
1488 options available to the user for configuration.
1491 bool "Symmetric Multi-Processing"
1492 depends on CPU_V6K || CPU_V7
1493 depends on GENERIC_CLOCKEVENTS
1495 depends on MMU || ARM_MPU
1497 This enables support for systems with more than one CPU. If you have
1498 a system with only one CPU, say N. If you have a system with more
1499 than one CPU, say Y.
1501 If you say N here, the kernel will run on uni- and multiprocessor
1502 machines, but will use only one CPU of a multiprocessor machine. If
1503 you say Y here, the kernel will run on many, but not all,
1504 uniprocessor machines. On a uniprocessor machine, the kernel
1505 will run faster if you say N here.
1507 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1508 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1509 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1511 If you don't know what to do here, say N.
1514 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1515 depends on SMP && !XIP_KERNEL && MMU
1518 SMP kernels contain instructions which fail on non-SMP processors.
1519 Enabling this option allows the kernel to modify itself to make
1520 these instructions safe. Disabling it allows about 1K of space
1523 If you don't know what to do here, say Y.
1525 config ARM_CPU_TOPOLOGY
1526 bool "Support cpu topology definition"
1527 depends on SMP && CPU_V7
1530 Support ARM cpu topology definition. The MPIDR register defines
1531 affinity between processors which is then used to describe the cpu
1532 topology of an ARM System.
1535 bool "Multi-core scheduler support"
1536 depends on ARM_CPU_TOPOLOGY
1538 Multi-core scheduler support improves the CPU scheduler's decision
1539 making when dealing with multi-core CPU chips at a cost of slightly
1540 increased overhead in some places. If unsure say N here.
1543 bool "SMT scheduler support"
1544 depends on ARM_CPU_TOPOLOGY
1546 Improves the CPU scheduler's decision making when dealing with
1547 MultiThreading at a cost of slightly increased overhead in some
1548 places. If unsure say N here.
1553 This option enables support for the ARM system coherency unit
1555 config HAVE_ARM_ARCH_TIMER
1556 bool "Architected timer support"
1558 select ARM_ARCH_TIMER
1559 select GENERIC_CLOCKEVENTS
1561 This option enables support for the ARM architected timer
1566 select CLKSRC_OF if OF
1568 This options enables support for the ARM timer and watchdog unit
1571 bool "Multi-Cluster Power Management"
1572 depends on CPU_V7 && SMP
1574 This option provides the common power management infrastructure
1575 for (multi-)cluster based systems, such as big.LITTLE based
1579 bool "big.LITTLE support (Experimental)"
1580 depends on CPU_V7 && SMP
1583 This option enables support selections for the big.LITTLE
1584 system architecture.
1587 bool "big.LITTLE switcher support"
1588 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1589 select ARM_CPU_SUSPEND
1592 The big.LITTLE "switcher" provides the core functionality to
1593 transparently handle transition between a cluster of A15's
1594 and a cluster of A7's in a big.LITTLE system.
1596 config BL_SWITCHER_DUMMY_IF
1597 tristate "Simple big.LITTLE switcher user interface"
1598 depends on BL_SWITCHER && DEBUG_KERNEL
1600 This is a simple and dummy char dev interface to control
1601 the big.LITTLE switcher core code. It is meant for
1602 debugging purposes only.
1605 prompt "Memory split"
1609 Select the desired split between kernel and user memory.
1611 If you are not absolutely sure what you are doing, leave this
1615 bool "3G/1G user/kernel split"
1617 bool "2G/2G user/kernel split"
1619 bool "1G/3G user/kernel split"
1624 default PHYS_OFFSET if !MMU
1625 default 0x40000000 if VMSPLIT_1G
1626 default 0x80000000 if VMSPLIT_2G
1630 int "Maximum number of CPUs (2-32)"
1636 bool "Support for hot-pluggable CPUs"
1639 Say Y here to experiment with turning CPUs off and on. CPUs
1640 can be controlled through /sys/devices/system/cpu.
1643 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1646 Say Y here if you want Linux to communicate with system firmware
1647 implementing the PSCI specification for CPU-centric power
1648 management operations described in ARM document number ARM DEN
1649 0022A ("Power State Coordination Interface System Software on
1652 # The GPIO number here must be sorted by descending number. In case of
1653 # a multiplatform kernel, we just want the highest value required by the
1654 # selected platforms.
1657 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1658 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1659 default 392 if ARCH_U8500
1660 default 352 if ARCH_VT8500
1661 default 288 if ARCH_SUNXI
1662 default 264 if MACH_H4700
1665 Maximum number of GPIOs in the system.
1667 If unsure, leave the default value.
1669 source kernel/Kconfig.preempt
1673 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1674 ARCH_S5PV210 || ARCH_EXYNOS4
1675 default AT91_TIMER_HZ if ARCH_AT91
1676 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1680 depends on HZ_FIXED = 0
1681 prompt "Timer frequency"
1705 default HZ_FIXED if HZ_FIXED != 0
1706 default 100 if HZ_100
1707 default 200 if HZ_200
1708 default 250 if HZ_250
1709 default 300 if HZ_300
1710 default 500 if HZ_500
1714 def_bool HIGH_RES_TIMERS
1716 config THUMB2_KERNEL
1717 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1718 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1719 default y if CPU_THUMBONLY
1721 select ARM_ASM_UNIFIED
1724 By enabling this option, the kernel will be compiled in
1725 Thumb-2 mode. A compiler/assembler that understand the unified
1726 ARM-Thumb syntax is needed.
1730 config THUMB2_AVOID_R_ARM_THM_JUMP11
1731 bool "Work around buggy Thumb-2 short branch relocations in gas"
1732 depends on THUMB2_KERNEL && MODULES
1735 Various binutils versions can resolve Thumb-2 branches to
1736 locally-defined, preemptible global symbols as short-range "b.n"
1737 branch instructions.
1739 This is a problem, because there's no guarantee the final
1740 destination of the symbol, or any candidate locations for a
1741 trampoline, are within range of the branch. For this reason, the
1742 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1743 relocation in modules at all, and it makes little sense to add
1746 The symptom is that the kernel fails with an "unsupported
1747 relocation" error when loading some modules.
1749 Until fixed tools are available, passing
1750 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1751 code which hits this problem, at the cost of a bit of extra runtime
1752 stack usage in some cases.
1754 The problem is described in more detail at:
1755 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1757 Only Thumb-2 kernels are affected.
1759 Unless you are sure your tools don't have this problem, say Y.
1761 config ARM_ASM_UNIFIED
1765 bool "Use the ARM EABI to compile the kernel"
1767 This option allows for the kernel to be compiled using the latest
1768 ARM ABI (aka EABI). This is only useful if you are using a user
1769 space environment that is also compiled with EABI.
1771 Since there are major incompatibilities between the legacy ABI and
1772 EABI, especially with regard to structure member alignment, this
1773 option also changes the kernel syscall calling convention to
1774 disambiguate both ABIs and allow for backward compatibility support
1775 (selected with CONFIG_OABI_COMPAT).
1777 To use this you need GCC version 4.0.0 or later.
1780 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1781 depends on AEABI && !THUMB2_KERNEL
1783 This option preserves the old syscall interface along with the
1784 new (ARM EABI) one. It also provides a compatibility layer to
1785 intercept syscalls that have structure arguments which layout
1786 in memory differs between the legacy ABI and the new ARM EABI
1787 (only for non "thumb" binaries). This option adds a tiny
1788 overhead to all syscalls and produces a slightly larger kernel.
1790 The seccomp filter system will not be available when this is
1791 selected, since there is no way yet to sensibly distinguish
1792 between calling conventions during filtering.
1794 If you know you'll be using only pure EABI user space then you
1795 can say N here. If this option is not selected and you attempt
1796 to execute a legacy ABI binary then the result will be
1797 UNPREDICTABLE (in fact it can be predicted that it won't work
1798 at all). If in doubt say N.
1800 config ARCH_HAS_HOLES_MEMORYMODEL
1803 config ARCH_SPARSEMEM_ENABLE
1806 config ARCH_SPARSEMEM_DEFAULT
1807 def_bool ARCH_SPARSEMEM_ENABLE
1809 config ARCH_SELECT_MEMORY_MODEL
1810 def_bool ARCH_SPARSEMEM_ENABLE
1812 config HAVE_ARCH_PFN_VALID
1813 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1816 bool "High Memory Support"
1819 The address space of ARM processors is only 4 Gigabytes large
1820 and it has to accommodate user address space, kernel address
1821 space as well as some memory mapped IO. That means that, if you
1822 have a large amount of physical memory and/or IO, not all of the
1823 memory can be "permanently mapped" by the kernel. The physical
1824 memory that is not permanently mapped is called "high memory".
1826 Depending on the selected kernel/user memory split, minimum
1827 vmalloc space and actual amount of RAM, you may not need this
1828 option which should result in a slightly faster kernel.
1833 bool "Allocate 2nd-level pagetables from highmem"
1836 config HW_PERF_EVENTS
1837 bool "Enable hardware performance counter support for perf events"
1838 depends on PERF_EVENTS
1841 Enable hardware performance counter support for perf events. If
1842 disabled, perf events will use software events only.
1844 config SYS_SUPPORTS_HUGETLBFS
1848 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1852 config ARCH_WANT_GENERAL_HUGETLB
1857 config FORCE_MAX_ZONEORDER
1858 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1859 range 11 64 if ARCH_SHMOBILE_LEGACY
1860 default "12" if SOC_AM33XX
1861 default "9" if SA1111 || ARCH_EFM32
1864 The kernel memory allocator divides physically contiguous memory
1865 blocks into "zones", where each zone is a power of two number of
1866 pages. This option selects the largest power of two that the kernel
1867 keeps in the memory allocator. If you need to allocate very large
1868 blocks of physically contiguous memory, then you may need to
1869 increase this value.
1871 This config option is actually maximum order plus one. For example,
1872 a value of 11 means that the largest free memory block is 2^10 pages.
1874 config ALIGNMENT_TRAP
1876 depends on CPU_CP15_MMU
1877 default y if !ARCH_EBSA110
1878 select HAVE_PROC_CPU if PROC_FS
1880 ARM processors cannot fetch/store information which is not
1881 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1882 address divisible by 4. On 32-bit ARM processors, these non-aligned
1883 fetch/store instructions will be emulated in software if you say
1884 here, which has a severe performance impact. This is necessary for
1885 correct operation of some network protocols. With an IP-only
1886 configuration it is safe to say N, otherwise say Y.
1888 config UACCESS_WITH_MEMCPY
1889 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1891 default y if CPU_FEROCEON
1893 Implement faster copy_to_user and clear_user methods for CPU
1894 cores where a 8-word STM instruction give significantly higher
1895 memory write throughput than a sequence of individual 32bit stores.
1897 A possible side effect is a slight increase in scheduling latency
1898 between threads sharing the same address space if they invoke
1899 such copy operations with large buffers.
1901 However, if the CPU data cache is using a write-allocate mode,
1902 this option is unlikely to provide any performance gain.
1906 prompt "Enable seccomp to safely compute untrusted bytecode"
1908 This kernel feature is useful for number crunching applications
1909 that may need to compute untrusted bytecode during their
1910 execution. By using pipes or other transports made available to
1911 the process as file descriptors supporting the read/write
1912 syscalls, it's possible to isolate those applications in
1913 their own address space using seccomp. Once seccomp is
1914 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1915 and the task is only allowed to execute a few safe syscalls
1916 defined by each seccomp mode.
1929 bool "Xen guest support on ARM (EXPERIMENTAL)"
1930 depends on ARM && AEABI && OF
1931 depends on CPU_V7 && !CPU_V6
1932 depends on !GENERIC_ATOMIC64
1934 select ARCH_DMA_ADDR_T_64BIT
1938 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1945 bool "Flattened Device Tree support"
1948 select OF_EARLY_FLATTREE
1949 select OF_RESERVED_MEM
1951 Include support for flattened device tree machine descriptions.
1954 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1957 This is the traditional way of passing data to the kernel at boot
1958 time. If you are solely relying on the flattened device tree (or
1959 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1960 to remove ATAGS support from your kernel binary. If unsure,
1963 config DEPRECATED_PARAM_STRUCT
1964 bool "Provide old way to pass kernel parameters"
1967 This was deprecated in 2001 and announced to live on for 5 years.
1968 Some old boot loaders still use this way.
1970 # Compressed boot loader in ROM. Yes, we really want to ask about
1971 # TEXT and BSS so we preserve their values in the config files.
1972 config ZBOOT_ROM_TEXT
1973 hex "Compressed ROM boot loader base address"
1976 The physical address at which the ROM-able zImage is to be
1977 placed in the target. Platforms which normally make use of
1978 ROM-able zImage formats normally set this to a suitable
1979 value in their defconfig file.
1981 If ZBOOT_ROM is not enabled, this has no effect.
1983 config ZBOOT_ROM_BSS
1984 hex "Compressed ROM boot loader BSS address"
1987 The base address of an area of read/write memory in the target
1988 for the ROM-able zImage which must be available while the
1989 decompressor is running. It must be large enough to hold the
1990 entire decompressed kernel plus an additional 128 KiB.
1991 Platforms which normally make use of ROM-able zImage formats
1992 normally set this to a suitable value in their defconfig file.
1994 If ZBOOT_ROM is not enabled, this has no effect.
1997 bool "Compressed boot loader in ROM/flash"
1998 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1999 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
2001 Say Y here if you intend to execute your compressed kernel image
2002 (zImage) directly from ROM or flash. If unsure, say N.
2005 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
2006 depends on ZBOOT_ROM && ARCH_SH7372
2007 default ZBOOT_ROM_NONE
2009 Include experimental SD/MMC loading code in the ROM-able zImage.
2010 With this enabled it is possible to write the ROM-able zImage
2011 kernel image to an MMC or SD card and boot the kernel straight
2012 from the reset vector. At reset the processor Mask ROM will load
2013 the first part of the ROM-able zImage which in turn loads the
2014 rest the kernel image to RAM.
2016 config ZBOOT_ROM_NONE
2017 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
2019 Do not load image from SD or MMC
2021 config ZBOOT_ROM_MMCIF
2022 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
2024 Load image from MMCIF hardware block.
2026 config ZBOOT_ROM_SH_MOBILE_SDHI
2027 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2029 Load image from SDHI hardware block
2033 config ARM_APPENDED_DTB
2034 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2037 With this option, the boot code will look for a device tree binary
2038 (DTB) appended to zImage
2039 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2041 This is meant as a backward compatibility convenience for those
2042 systems with a bootloader that can't be upgraded to accommodate
2043 the documented boot protocol using a device tree.
2045 Beware that there is very little in terms of protection against
2046 this option being confused by leftover garbage in memory that might
2047 look like a DTB header after a reboot if no actual DTB is appended
2048 to zImage. Do not leave this option active in a production kernel
2049 if you don't intend to always append a DTB. Proper passing of the
2050 location into r2 of a bootloader provided DTB is always preferable
2053 config ARM_ATAG_DTB_COMPAT
2054 bool "Supplement the appended DTB with traditional ATAG information"
2055 depends on ARM_APPENDED_DTB
2057 Some old bootloaders can't be updated to a DTB capable one, yet
2058 they provide ATAGs with memory configuration, the ramdisk address,
2059 the kernel cmdline string, etc. Such information is dynamically
2060 provided by the bootloader and can't always be stored in a static
2061 DTB. To allow a device tree enabled kernel to be used with such
2062 bootloaders, this option allows zImage to extract the information
2063 from the ATAG list and store it at run time into the appended DTB.
2066 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2067 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2069 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2070 bool "Use bootloader kernel arguments if available"
2072 Uses the command-line options passed by the boot loader instead of
2073 the device tree bootargs property. If the boot loader doesn't provide
2074 any, the device tree bootargs property will be used.
2076 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2077 bool "Extend with bootloader kernel arguments"
2079 The command-line arguments provided by the boot loader will be
2080 appended to the the device tree bootargs property.
2085 string "Default kernel command string"
2088 On some architectures (EBSA110 and CATS), there is currently no way
2089 for the boot loader to pass arguments to the kernel. For these
2090 architectures, you should supply some command-line options at build
2091 time by entering them here. As a minimum, you should specify the
2092 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2095 prompt "Kernel command line type" if CMDLINE != ""
2096 default CMDLINE_FROM_BOOTLOADER
2099 config CMDLINE_FROM_BOOTLOADER
2100 bool "Use bootloader kernel arguments if available"
2102 Uses the command-line options passed by the boot loader. If
2103 the boot loader doesn't provide any, the default kernel command
2104 string provided in CMDLINE will be used.
2106 config CMDLINE_EXTEND
2107 bool "Extend bootloader kernel arguments"
2109 The command-line arguments provided by the boot loader will be
2110 appended to the default kernel command string.
2112 config CMDLINE_FORCE
2113 bool "Always use the default kernel command string"
2115 Always use the default kernel command string, even if the boot
2116 loader passes other arguments to the kernel.
2117 This is useful if you cannot or don't want to change the
2118 command-line options your boot loader passes to the kernel.
2122 bool "Kernel Execute-In-Place from ROM"
2123 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2125 Execute-In-Place allows the kernel to run from non-volatile storage
2126 directly addressable by the CPU, such as NOR flash. This saves RAM
2127 space since the text section of the kernel is not loaded from flash
2128 to RAM. Read-write sections, such as the data section and stack,
2129 are still copied to RAM. The XIP kernel is not compressed since
2130 it has to run directly from flash, so it will take more space to
2131 store it. The flash address used to link the kernel object files,
2132 and for storing it, is configuration dependent. Therefore, if you
2133 say Y here, you must know the proper physical address where to
2134 store the kernel image depending on your own flash memory usage.
2136 Also note that the make target becomes "make xipImage" rather than
2137 "make zImage" or "make Image". The final kernel binary to put in
2138 ROM memory will be arch/arm/boot/xipImage.
2142 config XIP_PHYS_ADDR
2143 hex "XIP Kernel Physical Location"
2144 depends on XIP_KERNEL
2145 default "0x00080000"
2147 This is the physical address in your flash memory the kernel will
2148 be linked for and stored to. This address is dependent on your
2152 bool "Kexec system call (EXPERIMENTAL)"
2153 depends on (!SMP || PM_SLEEP_SMP)
2155 kexec is a system call that implements the ability to shutdown your
2156 current kernel, and to start another kernel. It is like a reboot
2157 but it is independent of the system firmware. And like a reboot
2158 you can start any kernel with it, not just Linux.
2160 It is an ongoing process to be certain the hardware in a machine
2161 is properly shutdown, so do not be surprised if this code does not
2162 initially work for you.
2165 bool "Export atags in procfs"
2166 depends on ATAGS && KEXEC
2169 Should the atags used to boot the kernel be exported in an "atags"
2170 file in procfs. Useful with kexec.
2173 bool "Build kdump crash kernel (EXPERIMENTAL)"
2175 Generate crash dump after being started by kexec. This should
2176 be normally only set in special crash dump kernels which are
2177 loaded in the main kernel with kexec-tools into a specially
2178 reserved region and then later executed after a crash by
2179 kdump/kexec. The crash dump kernel must be compiled to a
2180 memory address not used by the main kernel
2182 For more details see Documentation/kdump/kdump.txt
2184 config AUTO_ZRELADDR
2185 bool "Auto calculation of the decompressed kernel image address"
2187 ZRELADDR is the physical address where the decompressed kernel
2188 image will be placed. If AUTO_ZRELADDR is selected, the address
2189 will be determined at run-time by masking the current IP with
2190 0xf8000000. This assumes the zImage being placed in the first 128MB
2191 from start of memory.
2195 menu "CPU Power Management"
2198 source "drivers/cpufreq/Kconfig"
2201 source "drivers/cpuidle/Kconfig"
2205 menu "Floating point emulation"
2207 comment "At least one emulation must be selected"
2210 bool "NWFPE math emulation"
2211 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2213 Say Y to include the NWFPE floating point emulator in the kernel.
2214 This is necessary to run most binaries. Linux does not currently
2215 support floating point hardware so you need to say Y here even if
2216 your machine has an FPA or floating point co-processor podule.
2218 You may say N here if you are going to load the Acorn FPEmulator
2219 early in the bootup.
2222 bool "Support extended precision"
2223 depends on FPE_NWFPE
2225 Say Y to include 80-bit support in the kernel floating-point
2226 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2227 Note that gcc does not generate 80-bit operations by default,
2228 so in most cases this option only enlarges the size of the
2229 floating point emulator without any good reason.
2231 You almost surely want to say N here.
2234 bool "FastFPE math emulation (EXPERIMENTAL)"
2235 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2237 Say Y here to include the FAST floating point emulator in the kernel.
2238 This is an experimental much faster emulator which now also has full
2239 precision for the mantissa. It does not support any exceptions.
2240 It is very simple, and approximately 3-6 times faster than NWFPE.
2242 It should be sufficient for most programs. It may be not suitable
2243 for scientific calculations, but you have to check this for yourself.
2244 If you do not feel you need a faster FP emulation you should better
2248 bool "VFP-format floating point maths"
2249 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2251 Say Y to include VFP support code in the kernel. This is needed
2252 if your hardware includes a VFP unit.
2254 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2255 release notes and additional status information.
2257 Say N if your target does not have VFP hardware.
2265 bool "Advanced SIMD (NEON) Extension support"
2266 depends on VFPv3 && CPU_V7
2268 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2271 config KERNEL_MODE_NEON
2272 bool "Support for NEON in kernel mode"
2273 depends on NEON && AEABI
2275 Say Y to include support for NEON in kernel mode.
2279 menu "Userspace binary formats"
2281 source "fs/Kconfig.binfmt"
2284 tristate "RISC OS personality"
2287 Say Y here to include the kernel code necessary if you want to run
2288 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2289 experimental; if this sounds frightening, say N and sleep in peace.
2290 You can also say M here to compile this support as a module (which
2291 will be called arthur).
2295 menu "Power management options"
2297 source "kernel/power/Kconfig"
2299 config ARCH_SUSPEND_POSSIBLE
2300 depends on !ARCH_S5PC100
2301 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2302 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2305 config ARM_CPU_SUSPEND
2310 source "net/Kconfig"
2312 source "drivers/Kconfig"
2316 source "arch/arm/Kconfig.debug"
2318 source "security/Kconfig"
2320 source "crypto/Kconfig"
2322 source "lib/Kconfig"
2324 source "arch/arm/kvm/Kconfig"