4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_SUPPORTS_ATOMIC_RMW
8 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
9 select ARCH_WANT_IPC_PARSE_VERSION
10 select BUILDTIME_EXTABLE_SORT if MMU
11 select CPU_PM if (SUSPEND || CPU_IDLE)
12 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
15 select GENERIC_IRQ_PROBE
16 select GENERIC_IRQ_SHOW
17 select GENERIC_PCI_IOMAP
18 select GENERIC_SMP_IDLE_THREAD
19 select GENERIC_IDLE_POLL_SETUP
20 select GENERIC_STRNCPY_FROM_USER
21 select GENERIC_STRNLEN_USER
22 select HARDIRQS_SW_RESEND
23 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
25 select HAVE_ARCH_SECCOMP_FILTER
26 select HAVE_ARCH_TRACEHOOK
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_DEBUG_KMEMLEAK
30 select HAVE_DMA_API_DEBUG
32 select HAVE_DMA_CONTIGUOUS if MMU
33 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
34 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
35 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
36 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
37 select HAVE_GENERIC_DMA_COHERENT
38 select HAVE_GENERIC_HARDIRQS
39 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
40 select HAVE_IDE if PCI || ISA || PCMCIA
41 select HAVE_IRQ_TIME_ACCOUNTING
42 select HAVE_KERNEL_GZIP
43 select HAVE_KERNEL_LZMA
44 select HAVE_KERNEL_LZO
46 select HAVE_KPROBES if !XIP_KERNEL
47 select HAVE_KRETPROBES if (HAVE_KPROBES)
49 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
50 select HAVE_PERF_EVENTS
51 select HAVE_REGS_AND_STACK_ACCESS_API
52 select HAVE_SYSCALL_TRACEPOINTS
55 select PERF_USE_VMALLOC
57 select SYS_SUPPORTS_APM_EMULATION
58 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
59 select MODULES_USE_ELF_REL
60 select CLONE_BACKWARDS
61 select OLD_SIGSUSPEND3
63 select HAVE_CONTEXT_TRACKING
65 The ARM series is a line of low-power-consumption RISC chip designs
66 licensed by ARM Ltd and targeted at embedded applications and
67 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
68 manufactured, but legacy ARM-based PC hardware remains popular in
69 Europe. There is an ARM Linux project with a web page at
70 <http://www.arm.linux.org.uk/>.
72 config ARM_HAS_SG_CHAIN
75 config NEED_SG_DMA_LENGTH
78 config ARM_DMA_USE_IOMMU
80 select ARM_HAS_SG_CHAIN
81 select NEED_SG_DMA_LENGTH
85 config ARM_DMA_IOMMU_ALIGNMENT
86 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
90 DMA mapping framework by default aligns all buffers to the smallest
91 PAGE_SIZE order which is greater than or equal to the requested buffer
92 size. This works well for buffers up to a few hundreds kilobytes, but
93 for larger buffers it just a waste of address space. Drivers which has
94 relatively small addressing window (like 64Mib) might run out of
95 virtual space with just a few allocations.
97 With this parameter you can specify the maximum PAGE_SIZE order for
98 DMA IOMMU buffers. Larger buffers will be aligned only to this
99 specified order. The order is expressed as a power of two multiplied
107 config MIGHT_HAVE_PCI
110 config SYS_SUPPORTS_APM_EMULATION
115 select GENERIC_ALLOCATOR
126 The Extended Industry Standard Architecture (EISA) bus was
127 developed as an open alternative to the IBM MicroChannel bus.
129 The EISA bus provided some of the features of the IBM MicroChannel
130 bus while maintaining backward compatibility with cards made for
131 the older ISA bus. The EISA bus saw limited use between 1988 and
132 1995 when it was made obsolete by the PCI bus.
134 Say Y here if you are building a kernel for an EISA-based machine.
141 config STACKTRACE_SUPPORT
145 config HAVE_LATENCYTOP_SUPPORT
150 config LOCKDEP_SUPPORT
154 config TRACE_IRQFLAGS_SUPPORT
158 config RWSEM_GENERIC_SPINLOCK
162 config RWSEM_XCHGADD_ALGORITHM
165 config ARCH_HAS_ILOG2_U32
168 config ARCH_HAS_ILOG2_U64
171 config ARCH_HAS_CPUFREQ
174 Internal node to signify that the ARCH has CPUFREQ support
175 and that the relevant menu configurations are displayed for
178 config GENERIC_HWEIGHT
182 config GENERIC_CALIBRATE_DELAY
186 config ARCH_MAY_HAVE_PC_FDC
192 config NEED_DMA_MAP_STATE
195 config ARCH_HAS_DMA_SET_COHERENT_MASK
198 config GENERIC_ISA_DMA
204 config NEED_RET_TO_USER
212 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
213 default DRAM_BASE if REMAP_VECTORS_TO_RAM
216 The base address of exception vectors. This must be two pages
219 config ARM_PATCH_PHYS_VIRT
220 bool "Patch physical to virtual translations at runtime" if EMBEDDED
222 depends on !XIP_KERNEL && MMU
223 depends on !ARCH_REALVIEW || !SPARSEMEM
225 Patch phys-to-virt and virt-to-phys translation functions at
226 boot and module load time according to the position of the
227 kernel in system memory.
229 This can only be used with non-XIP MMU kernels where the base
230 of physical memory is at a 16MB boundary.
232 Only disable this option if you know that you do not require
233 this feature (eg, building a kernel for a single machine) and
234 you need to shrink the kernel to the minimal size.
236 config NEED_MACH_GPIO_H
239 Select this when mach/gpio.h is required to provide special
240 definitions for this platform. The need for mach/gpio.h should
241 be avoided when possible.
243 config NEED_MACH_IO_H
246 Select this when mach/io.h is required to provide special
247 definitions for this platform. The need for mach/io.h should
248 be avoided when possible.
250 config NEED_MACH_MEMORY_H
253 Select this when mach/memory.h is required to provide special
254 definitions for this platform. The need for mach/memory.h should
255 be avoided when possible.
258 hex "Physical address of main memory" if MMU
259 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
260 default DRAM_BASE if !MMU
262 Please provide the physical address corresponding to the
263 location of main memory in your system.
269 source "init/Kconfig"
271 source "kernel/Kconfig.freezer"
276 bool "MMU-based Paged Memory Management Support"
279 Select if you want MMU-based virtualised addressing space
280 support by paged memory management. If unsure, say 'Y'.
283 # The "ARM system type" choice list is ordered alphabetically by option
284 # text. Please add new entries in the option alphabetic order.
287 prompt "ARM system type"
288 default ARCH_VERSATILE if !MMU
289 default ARCH_MULTIPLATFORM if MMU
291 config ARCH_MULTIPLATFORM
292 bool "Allow multiple platforms to be selected"
294 select ARM_PATCH_PHYS_VIRT
297 select MULTI_IRQ_HANDLER
301 config ARCH_INTEGRATOR
302 bool "ARM Ltd. Integrator family"
303 select ARCH_HAS_CPUFREQ
306 select COMMON_CLK_VERSATILE
307 select GENERIC_CLOCKEVENTS
310 select MULTI_IRQ_HANDLER
311 select NEED_MACH_MEMORY_H
312 select PLAT_VERSATILE
314 select VERSATILE_FPGA_IRQ
316 Support for ARM's Integrator platform.
319 bool "ARM Ltd. RealView family"
320 select ARCH_WANT_OPTIONAL_GPIOLIB
322 select ARM_TIMER_SP804
324 select COMMON_CLK_VERSATILE
325 select GENERIC_CLOCKEVENTS
326 select GPIO_PL061 if GPIOLIB
328 select NEED_MACH_MEMORY_H
329 select PLAT_VERSATILE
330 select PLAT_VERSATILE_CLCD
332 This enables support for ARM Ltd RealView boards.
334 config ARCH_VERSATILE
335 bool "ARM Ltd. Versatile family"
336 select ARCH_WANT_OPTIONAL_GPIOLIB
338 select ARM_TIMER_SP804
341 select GENERIC_CLOCKEVENTS
342 select HAVE_MACH_CLKDEV
344 select PLAT_VERSATILE
345 select PLAT_VERSATILE_CLCD
346 select PLAT_VERSATILE_CLOCK
347 select VERSATILE_FPGA_IRQ
349 This enables support for ARM Ltd Versatile board.
353 select ARCH_REQUIRE_GPIOLIB
357 select NEED_MACH_GPIO_H
358 select NEED_MACH_IO_H if PCCARD
360 select PINCTRL_AT91 if USE_OF
362 This enables support for systems based on Atmel
363 AT91RM9200 and AT91SAM9* processors.
366 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
367 select ARCH_REQUIRE_GPIOLIB
372 select GENERIC_CLOCKEVENTS
373 select MULTI_IRQ_HANDLER
374 select NEED_MACH_MEMORY_H
377 Support for Cirrus Logic 711x/721x/731x based boards.
380 bool "Cortina Systems Gemini"
381 select ARCH_REQUIRE_GPIOLIB
382 select ARCH_USES_GETTIMEOFFSET
383 select NEED_MACH_GPIO_H
386 Support for the Cortina Systems Gemini family SoCs
390 select ARCH_USES_GETTIMEOFFSET
393 select NEED_MACH_IO_H
394 select NEED_MACH_MEMORY_H
397 This is an evaluation board for the StrongARM processor available
398 from Digital. It has limited hardware on-board, including an
399 Ethernet interface, two PCMCIA sockets, two serial ports and a
404 select ARCH_HAS_HOLES_MEMORYMODEL
405 select ARCH_REQUIRE_GPIOLIB
406 select ARCH_USES_GETTIMEOFFSET
411 select NEED_MACH_MEMORY_H
413 This enables support for the Cirrus EP93xx series of CPUs.
415 config ARCH_FOOTBRIDGE
419 select GENERIC_CLOCKEVENTS
421 select NEED_MACH_IO_H if !MMU
422 select NEED_MACH_MEMORY_H
424 Support for systems based on the DC21285 companion chip
425 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
428 bool "Hilscher NetX based"
432 select GENERIC_CLOCKEVENTS
434 This enables support for systems based on the Hilscher NetX Soc
439 select ARCH_SUPPORTS_MSI
441 select NEED_MACH_MEMORY_H
442 select NEED_RET_TO_USER
447 Support for Intel's IOP13XX (XScale) family of processors.
452 select ARCH_REQUIRE_GPIOLIB
454 select NEED_MACH_GPIO_H
455 select NEED_RET_TO_USER
459 Support for Intel's 80219 and IOP32X (XScale) family of
465 select ARCH_REQUIRE_GPIOLIB
467 select NEED_MACH_GPIO_H
468 select NEED_RET_TO_USER
472 Support for Intel's IOP33X (XScale) family of processors.
477 select ARCH_HAS_DMA_SET_COHERENT_MASK
478 select ARCH_REQUIRE_GPIOLIB
481 select DMABOUNCE if PCI
482 select GENERIC_CLOCKEVENTS
483 select MIGHT_HAVE_PCI
484 select NEED_MACH_IO_H
485 select USB_EHCI_BIG_ENDIAN_MMIO
486 select USB_EHCI_BIG_ENDIAN_DESC
488 Support for Intel's IXP4XX (XScale) family of processors.
492 select ARCH_REQUIRE_GPIOLIB
494 select GENERIC_CLOCKEVENTS
495 select MIGHT_HAVE_PCI
498 select PLAT_ORION_LEGACY
499 select USB_ARCH_HAS_EHCI
502 Support for the Marvell Dove SoC 88AP510
505 bool "Marvell Kirkwood"
506 select ARCH_REQUIRE_GPIOLIB
508 select GENERIC_CLOCKEVENTS
512 select PINCTRL_KIRKWOOD
513 select PLAT_ORION_LEGACY
516 Support for the following Marvell Kirkwood series SoCs:
517 88F6180, 88F6192 and 88F6281.
520 bool "Marvell MV78xx0"
521 select ARCH_REQUIRE_GPIOLIB
523 select GENERIC_CLOCKEVENTS
525 select PLAT_ORION_LEGACY
528 Support for the following Marvell MV78xx0 series SoCs:
534 select ARCH_REQUIRE_GPIOLIB
536 select GENERIC_CLOCKEVENTS
538 select PLAT_ORION_LEGACY
541 Support for the following Marvell Orion 5x series SoCs:
542 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
543 Orion-2 (5281), Orion-1-90 (6183).
546 bool "Marvell PXA168/910/MMP2"
548 select ARCH_REQUIRE_GPIOLIB
550 select GENERIC_ALLOCATOR
551 select GENERIC_CLOCKEVENTS
554 select NEED_MACH_GPIO_H
559 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
562 bool "Micrel/Kendin KS8695"
563 select ARCH_REQUIRE_GPIOLIB
566 select GENERIC_CLOCKEVENTS
567 select NEED_MACH_MEMORY_H
569 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
570 System-on-Chip devices.
573 bool "Nuvoton W90X900 CPU"
574 select ARCH_REQUIRE_GPIOLIB
578 select GENERIC_CLOCKEVENTS
580 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
581 At present, the w90x900 has been renamed nuc900, regarding
582 the ARM series product line, you can login the following
583 link address to know more.
585 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
586 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
590 select ARCH_REQUIRE_GPIOLIB
595 select GENERIC_CLOCKEVENTS
598 select USB_ARCH_HAS_OHCI
601 Support for the NXP LPC32XX family of processors
604 bool "PXA2xx/PXA3xx-based"
606 select ARCH_HAS_CPUFREQ
608 select ARCH_REQUIRE_GPIOLIB
609 select ARM_CPU_SUSPEND if PM
613 select GENERIC_CLOCKEVENTS
616 select MULTI_IRQ_HANDLER
617 select NEED_MACH_GPIO_H
621 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
625 select ARCH_REQUIRE_GPIOLIB
627 select GENERIC_CLOCKEVENTS
630 Support for Qualcomm MSM/QSD based systems. This runs on the
631 apps processor of the MSM/QSD and depends on a shared memory
632 interface to the modem processor which runs the baseband
633 stack and controls some vital subsystems
634 (clock and power control, etc).
637 bool "Renesas SH-Mobile / R-Mobile"
639 select GENERIC_CLOCKEVENTS
640 select HAVE_ARM_SCU if SMP
641 select HAVE_ARM_TWD if LOCAL_TIMERS
643 select HAVE_MACH_CLKDEV
645 select MIGHT_HAVE_CACHE_L2X0
646 select MULTI_IRQ_HANDLER
647 select NEED_MACH_MEMORY_H
649 select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
650 select PM_GENERIC_DOMAINS if PM
653 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
658 select ARCH_MAY_HAVE_PC_FDC
659 select ARCH_SPARSEMEM_ENABLE
660 select ARCH_USES_GETTIMEOFFSET
663 select HAVE_PATA_PLATFORM
665 select NEED_MACH_IO_H
666 select NEED_MACH_MEMORY_H
670 On the Acorn Risc-PC, Linux can support the internal IDE disk and
671 CD-ROM interface, serial and parallel port, and the floppy drive.
675 select ARCH_HAS_CPUFREQ
677 select ARCH_REQUIRE_GPIOLIB
678 select ARCH_SPARSEMEM_ENABLE
683 select GENERIC_CLOCKEVENTS
686 select NEED_MACH_GPIO_H
687 select NEED_MACH_MEMORY_H
690 Support for StrongARM 11x0 based boards.
693 bool "Samsung S3C24XX SoCs"
694 select ARCH_HAS_CPUFREQ
695 select ARCH_REQUIRE_GPIOLIB
698 select GENERIC_CLOCKEVENTS
700 select HAVE_S3C2410_I2C if I2C
701 select HAVE_S3C2410_WATCHDOG if WATCHDOG
702 select HAVE_S3C_RTC if RTC_CLASS
703 select MULTI_IRQ_HANDLER
704 select NEED_MACH_GPIO_H
705 select NEED_MACH_IO_H
707 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
708 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
709 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
710 Samsung SMDK2410 development board (and derivatives).
713 bool "Samsung S3C64XX"
714 select ARCH_HAS_CPUFREQ
715 select ARCH_REQUIRE_GPIOLIB
720 select GENERIC_CLOCKEVENTS
722 select HAVE_S3C2410_I2C if I2C
723 select HAVE_S3C2410_WATCHDOG if WATCHDOG
725 select NEED_MACH_GPIO_H
729 select S3C_GPIO_TRACK
730 select SAMSUNG_CLKSRC
731 select SAMSUNG_GPIOLIB_4BIT
732 select SAMSUNG_IRQ_VIC_TIMER
733 select USB_ARCH_HAS_OHCI
735 Samsung S3C64XX series based systems
738 bool "Samsung S5P6440 S5P6450"
742 select GENERIC_CLOCKEVENTS
744 select HAVE_S3C2410_I2C if I2C
745 select HAVE_S3C2410_WATCHDOG if WATCHDOG
746 select HAVE_S3C_RTC if RTC_CLASS
747 select NEED_MACH_GPIO_H
749 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
753 bool "Samsung S5PC100"
754 select ARCH_REQUIRE_GPIOLIB
758 select GENERIC_CLOCKEVENTS
760 select HAVE_S3C2410_I2C if I2C
761 select HAVE_S3C2410_WATCHDOG if WATCHDOG
762 select HAVE_S3C_RTC if RTC_CLASS
763 select NEED_MACH_GPIO_H
765 Samsung S5PC100 series based systems
768 bool "Samsung S5PV210/S5PC110"
769 select ARCH_HAS_CPUFREQ
770 select ARCH_HAS_HOLES_MEMORYMODEL
771 select ARCH_SPARSEMEM_ENABLE
775 select GENERIC_CLOCKEVENTS
777 select HAVE_S3C2410_I2C if I2C
778 select HAVE_S3C2410_WATCHDOG if WATCHDOG
779 select HAVE_S3C_RTC if RTC_CLASS
780 select NEED_MACH_GPIO_H
781 select NEED_MACH_MEMORY_H
783 Samsung S5PV210/S5PC110 series based systems
786 bool "Samsung EXYNOS"
787 select ARCH_HAS_CPUFREQ
788 select ARCH_HAS_HOLES_MEMORYMODEL
789 select ARCH_SPARSEMEM_ENABLE
793 select GENERIC_CLOCKEVENTS
795 select HAVE_S3C2410_I2C if I2C
796 select HAVE_S3C2410_WATCHDOG if WATCHDOG
797 select HAVE_S3C_RTC if RTC_CLASS
798 select NEED_MACH_GPIO_H
799 select NEED_MACH_MEMORY_H
801 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
805 select ARCH_USES_GETTIMEOFFSET
809 select NEED_MACH_MEMORY_H
814 Support for the StrongARM based Digital DNARD machine, also known
815 as "Shark" (<http://www.shark-linux.de/shark.html>).
818 bool "ST-Ericsson U300 Series"
820 select ARCH_REQUIRE_GPIOLIB
822 select ARM_PATCH_PHYS_VIRT
828 select GENERIC_CLOCKEVENTS
832 Support for ST-Ericsson U300 series mobile platforms.
836 select ARCH_HAS_HOLES_MEMORYMODEL
837 select ARCH_REQUIRE_GPIOLIB
839 select GENERIC_ALLOCATOR
840 select GENERIC_CLOCKEVENTS
841 select GENERIC_IRQ_CHIP
843 select NEED_MACH_GPIO_H
847 Support for TI's DaVinci platform.
852 select ARCH_HAS_CPUFREQ
853 select ARCH_HAS_HOLES_MEMORYMODEL
855 select ARCH_REQUIRE_GPIOLIB
858 select GENERIC_CLOCKEVENTS
859 select GENERIC_IRQ_CHIP
863 select NEED_MACH_IO_H if PCCARD
864 select NEED_MACH_MEMORY_H
866 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
870 menu "Multiple platform selection"
871 depends on ARCH_MULTIPLATFORM
873 comment "CPU Core family selection"
876 bool "ARMv4 based platforms (FA526, StrongARM)"
877 depends on !ARCH_MULTI_V6_V7
878 select ARCH_MULTI_V4_V5
880 config ARCH_MULTI_V4T
881 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
882 depends on !ARCH_MULTI_V6_V7
883 select ARCH_MULTI_V4_V5
886 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
887 depends on !ARCH_MULTI_V6_V7
888 select ARCH_MULTI_V4_V5
890 config ARCH_MULTI_V4_V5
894 bool "ARMv6 based platforms (ARM11)"
895 select ARCH_MULTI_V6_V7
899 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
901 select ARCH_MULTI_V6_V7
904 config ARCH_MULTI_V6_V7
907 config ARCH_MULTI_CPU_AUTO
908 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
914 # This is sorted alphabetically by mach-* pathname. However, plat-*
915 # Kconfigs may be included either alphabetically (according to the
916 # plat- suffix) or along side the corresponding mach-* source.
918 source "arch/arm/mach-mvebu/Kconfig"
920 source "arch/arm/mach-at91/Kconfig"
922 source "arch/arm/mach-bcm/Kconfig"
924 source "arch/arm/mach-bcm2835/Kconfig"
926 source "arch/arm/mach-clps711x/Kconfig"
928 source "arch/arm/mach-cns3xxx/Kconfig"
930 source "arch/arm/mach-davinci/Kconfig"
932 source "arch/arm/mach-dove/Kconfig"
934 source "arch/arm/mach-ep93xx/Kconfig"
936 source "arch/arm/mach-footbridge/Kconfig"
938 source "arch/arm/mach-gemini/Kconfig"
940 source "arch/arm/mach-highbank/Kconfig"
942 source "arch/arm/mach-integrator/Kconfig"
944 source "arch/arm/mach-iop32x/Kconfig"
946 source "arch/arm/mach-iop33x/Kconfig"
948 source "arch/arm/mach-iop13xx/Kconfig"
950 source "arch/arm/mach-ixp4xx/Kconfig"
952 source "arch/arm/mach-kirkwood/Kconfig"
954 source "arch/arm/mach-ks8695/Kconfig"
956 source "arch/arm/mach-msm/Kconfig"
958 source "arch/arm/mach-mv78xx0/Kconfig"
960 source "arch/arm/mach-imx/Kconfig"
962 source "arch/arm/mach-mxs/Kconfig"
964 source "arch/arm/mach-netx/Kconfig"
966 source "arch/arm/mach-nomadik/Kconfig"
968 source "arch/arm/plat-omap/Kconfig"
970 source "arch/arm/mach-omap1/Kconfig"
972 source "arch/arm/mach-omap2/Kconfig"
974 source "arch/arm/mach-orion5x/Kconfig"
976 source "arch/arm/mach-picoxcell/Kconfig"
978 source "arch/arm/mach-pxa/Kconfig"
979 source "arch/arm/plat-pxa/Kconfig"
981 source "arch/arm/mach-mmp/Kconfig"
983 source "arch/arm/mach-realview/Kconfig"
985 source "arch/arm/mach-sa1100/Kconfig"
987 source "arch/arm/plat-samsung/Kconfig"
989 source "arch/arm/mach-socfpga/Kconfig"
991 source "arch/arm/mach-spear/Kconfig"
993 source "arch/arm/mach-s3c24xx/Kconfig"
996 source "arch/arm/mach-s3c64xx/Kconfig"
999 source "arch/arm/mach-s5p64x0/Kconfig"
1001 source "arch/arm/mach-s5pc100/Kconfig"
1003 source "arch/arm/mach-s5pv210/Kconfig"
1005 source "arch/arm/mach-exynos/Kconfig"
1007 source "arch/arm/mach-shmobile/Kconfig"
1009 source "arch/arm/mach-sunxi/Kconfig"
1011 source "arch/arm/mach-prima2/Kconfig"
1013 source "arch/arm/mach-tegra/Kconfig"
1015 source "arch/arm/mach-u300/Kconfig"
1017 source "arch/arm/mach-ux500/Kconfig"
1019 source "arch/arm/mach-versatile/Kconfig"
1021 source "arch/arm/mach-vexpress/Kconfig"
1022 source "arch/arm/plat-versatile/Kconfig"
1024 source "arch/arm/mach-virt/Kconfig"
1026 source "arch/arm/mach-vt8500/Kconfig"
1028 source "arch/arm/mach-w90x900/Kconfig"
1030 source "arch/arm/mach-zynq/Kconfig"
1032 # Definitions to make life easier
1038 select GENERIC_CLOCKEVENTS
1044 select GENERIC_IRQ_CHIP
1047 config PLAT_ORION_LEGACY
1054 config PLAT_VERSATILE
1057 config ARM_TIMER_SP804
1060 select CLKSRC_OF if OF
1062 source arch/arm/mm/Kconfig
1066 default 16 if ARCH_EP93XX
1070 bool "Enable iWMMXt support" if !CPU_PJ4
1071 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1072 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1074 Enable support for iWMMXt context switching at run time if
1075 running on a CPU that supports it.
1079 depends on CPU_XSCALE
1082 config MULTI_IRQ_HANDLER
1085 Allow each machine to specify it's own IRQ handler at run time.
1088 source "arch/arm/Kconfig-nommu"
1091 config PJ4B_ERRATA_4742
1092 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1093 depends on CPU_PJ4B && MACH_ARMADA_370
1096 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1097 Event (WFE) IDLE states, a specific timing sensitivity exists between
1098 the retiring WFI/WFE instructions and the newly issued subsequent
1099 instructions. This sensitivity can result in a CPU hang scenario.
1101 The software must insert either a Data Synchronization Barrier (DSB)
1102 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1105 config ARM_ERRATA_326103
1106 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1109 Executing a SWP instruction to read-only memory does not set bit 11
1110 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1111 treat the access as a read, preventing a COW from occurring and
1112 causing the faulting task to livelock.
1114 config ARM_ERRATA_411920
1115 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1116 depends on CPU_V6 || CPU_V6K
1118 Invalidation of the Instruction Cache operation can
1119 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1120 It does not affect the MPCore. This option enables the ARM Ltd.
1121 recommended workaround.
1123 config ARM_ERRATA_430973
1124 bool "ARM errata: Stale prediction on replaced interworking branch"
1127 This option enables the workaround for the 430973 Cortex-A8
1128 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1129 interworking branch is replaced with another code sequence at the
1130 same virtual address, whether due to self-modifying code or virtual
1131 to physical address re-mapping, Cortex-A8 does not recover from the
1132 stale interworking branch prediction. This results in Cortex-A8
1133 executing the new code sequence in the incorrect ARM or Thumb state.
1134 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1135 and also flushes the branch target cache at every context switch.
1136 Note that setting specific bits in the ACTLR register may not be
1137 available in non-secure mode.
1139 config ARM_ERRATA_458693
1140 bool "ARM errata: Processor deadlock when a false hazard is created"
1142 depends on !ARCH_MULTIPLATFORM
1144 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1145 erratum. For very specific sequences of memory operations, it is
1146 possible for a hazard condition intended for a cache line to instead
1147 be incorrectly associated with a different cache line. This false
1148 hazard might then cause a processor deadlock. The workaround enables
1149 the L1 caching of the NEON accesses and disables the PLD instruction
1150 in the ACTLR register. Note that setting specific bits in the ACTLR
1151 register may not be available in non-secure mode.
1153 config ARM_ERRATA_460075
1154 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1156 depends on !ARCH_MULTIPLATFORM
1158 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1159 erratum. Any asynchronous access to the L2 cache may encounter a
1160 situation in which recent store transactions to the L2 cache are lost
1161 and overwritten with stale memory contents from external memory. The
1162 workaround disables the write-allocate mode for the L2 cache via the
1163 ACTLR register. Note that setting specific bits in the ACTLR register
1164 may not be available in non-secure mode.
1166 config ARM_ERRATA_742230
1167 bool "ARM errata: DMB operation may be faulty"
1168 depends on CPU_V7 && SMP
1169 depends on !ARCH_MULTIPLATFORM
1171 This option enables the workaround for the 742230 Cortex-A9
1172 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1173 between two write operations may not ensure the correct visibility
1174 ordering of the two writes. This workaround sets a specific bit in
1175 the diagnostic register of the Cortex-A9 which causes the DMB
1176 instruction to behave as a DSB, ensuring the correct behaviour of
1179 config ARM_ERRATA_742231
1180 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1181 depends on CPU_V7 && SMP
1182 depends on !ARCH_MULTIPLATFORM
1184 This option enables the workaround for the 742231 Cortex-A9
1185 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1186 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1187 accessing some data located in the same cache line, may get corrupted
1188 data due to bad handling of the address hazard when the line gets
1189 replaced from one of the CPUs at the same time as another CPU is
1190 accessing it. This workaround sets specific bits in the diagnostic
1191 register of the Cortex-A9 which reduces the linefill issuing
1192 capabilities of the processor.
1194 config PL310_ERRATA_588369
1195 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1196 depends on CACHE_L2X0
1198 The PL310 L2 cache controller implements three types of Clean &
1199 Invalidate maintenance operations: by Physical Address
1200 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1201 They are architecturally defined to behave as the execution of a
1202 clean operation followed immediately by an invalidate operation,
1203 both performing to the same memory location. This functionality
1204 is not correctly implemented in PL310 as clean lines are not
1205 invalidated as a result of these operations.
1207 config ARM_ERRATA_643719
1208 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1209 depends on CPU_V7 && SMP
1211 This option enables the workaround for the 643719 Cortex-A9 (prior to
1212 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1213 register returns zero when it should return one. The workaround
1214 corrects this value, ensuring cache maintenance operations which use
1215 it behave as intended and avoiding data corruption.
1217 config ARM_ERRATA_720789
1218 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1221 This option enables the workaround for the 720789 Cortex-A9 (prior to
1222 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1223 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1224 As a consequence of this erratum, some TLB entries which should be
1225 invalidated are not, resulting in an incoherency in the system page
1226 tables. The workaround changes the TLB flushing routines to invalidate
1227 entries regardless of the ASID.
1229 config PL310_ERRATA_727915
1230 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1231 depends on CACHE_L2X0
1233 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1234 operation (offset 0x7FC). This operation runs in background so that
1235 PL310 can handle normal accesses while it is in progress. Under very
1236 rare circumstances, due to this erratum, write data can be lost when
1237 PL310 treats a cacheable write transaction during a Clean &
1238 Invalidate by Way operation.
1240 config ARM_ERRATA_743622
1241 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1243 depends on !ARCH_MULTIPLATFORM
1245 This option enables the workaround for the 743622 Cortex-A9
1246 (r2p*) erratum. Under very rare conditions, a faulty
1247 optimisation in the Cortex-A9 Store Buffer may lead to data
1248 corruption. This workaround sets a specific bit in the diagnostic
1249 register of the Cortex-A9 which disables the Store Buffer
1250 optimisation, preventing the defect from occurring. This has no
1251 visible impact on the overall performance or power consumption of the
1254 config ARM_ERRATA_751472
1255 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1257 depends on !ARCH_MULTIPLATFORM
1259 This option enables the workaround for the 751472 Cortex-A9 (prior
1260 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1261 completion of a following broadcasted operation if the second
1262 operation is received by a CPU before the ICIALLUIS has completed,
1263 potentially leading to corrupted entries in the cache or TLB.
1265 config PL310_ERRATA_753970
1266 bool "PL310 errata: cache sync operation may be faulty"
1267 depends on CACHE_PL310
1269 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1271 Under some condition the effect of cache sync operation on
1272 the store buffer still remains when the operation completes.
1273 This means that the store buffer is always asked to drain and
1274 this prevents it from merging any further writes. The workaround
1275 is to replace the normal offset of cache sync operation (0x730)
1276 by another offset targeting an unmapped PL310 register 0x740.
1277 This has the same effect as the cache sync operation: store buffer
1278 drain and waiting for all buffers empty.
1280 config ARM_ERRATA_754322
1281 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1284 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1285 r3p*) erratum. A speculative memory access may cause a page table walk
1286 which starts prior to an ASID switch but completes afterwards. This
1287 can populate the micro-TLB with a stale entry which may be hit with
1288 the new ASID. This workaround places two dsb instructions in the mm
1289 switching code so that no page table walks can cross the ASID switch.
1291 config ARM_ERRATA_754327
1292 bool "ARM errata: no automatic Store Buffer drain"
1293 depends on CPU_V7 && SMP
1295 This option enables the workaround for the 754327 Cortex-A9 (prior to
1296 r2p0) erratum. The Store Buffer does not have any automatic draining
1297 mechanism and therefore a livelock may occur if an external agent
1298 continuously polls a memory location waiting to observe an update.
1299 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1300 written polling loops from denying visibility of updates to memory.
1302 config ARM_ERRATA_364296
1303 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1304 depends on CPU_V6 && !SMP
1306 This options enables the workaround for the 364296 ARM1136
1307 r0p2 erratum (possible cache data corruption with
1308 hit-under-miss enabled). It sets the undocumented bit 31 in
1309 the auxiliary control register and the FI bit in the control
1310 register, thus disabling hit-under-miss without putting the
1311 processor into full low interrupt latency mode. ARM11MPCore
1314 config ARM_ERRATA_764369
1315 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1316 depends on CPU_V7 && SMP
1318 This option enables the workaround for erratum 764369
1319 affecting Cortex-A9 MPCore with two or more processors (all
1320 current revisions). Under certain timing circumstances, a data
1321 cache line maintenance operation by MVA targeting an Inner
1322 Shareable memory region may fail to proceed up to either the
1323 Point of Coherency or to the Point of Unification of the
1324 system. This workaround adds a DSB instruction before the
1325 relevant cache maintenance functions and sets a specific bit
1326 in the diagnostic control register of the SCU.
1328 config PL310_ERRATA_769419
1329 bool "PL310 errata: no automatic Store Buffer drain"
1330 depends on CACHE_L2X0
1332 On revisions of the PL310 prior to r3p2, the Store Buffer does
1333 not automatically drain. This can cause normal, non-cacheable
1334 writes to be retained when the memory system is idle, leading
1335 to suboptimal I/O performance for drivers using coherent DMA.
1336 This option adds a write barrier to the cpu_idle loop so that,
1337 on systems with an outer cache, the store buffer is drained
1340 config ARM_ERRATA_775420
1341 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1344 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1345 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1346 operation aborts with MMU exception, it might cause the processor
1347 to deadlock. This workaround puts DSB before executing ISB if
1348 an abort may occur on cache maintenance.
1350 config ARM_ERRATA_798181
1351 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1352 depends on CPU_V7 && SMP
1354 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1355 adequately shooting down all use of the old entries. This
1356 option enables the Linux kernel workaround for this erratum
1357 which sends an IPI to the CPUs that are running the same ASID
1358 as the one being invalidated.
1362 source "arch/arm/common/Kconfig"
1372 Find out whether you have ISA slots on your motherboard. ISA is the
1373 name of a bus system, i.e. the way the CPU talks to the other stuff
1374 inside your box. Other bus systems are PCI, EISA, MicroChannel
1375 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1376 newer boards don't support it. If you have ISA, say Y, otherwise N.
1378 # Select ISA DMA controller support
1383 # Select ISA DMA interface
1388 bool "PCI support" if MIGHT_HAVE_PCI
1390 Find out whether you have a PCI motherboard. PCI is the name of a
1391 bus system, i.e. the way the CPU talks to the other stuff inside
1392 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1393 VESA. If you have PCI, say Y, otherwise N.
1399 config PCI_NANOENGINE
1400 bool "BSE nanoEngine PCI support"
1401 depends on SA1100_NANOENGINE
1403 Enable PCI on the BSE nanoEngine board.
1408 # Select the host bridge type
1409 config PCI_HOST_VIA82C505
1411 depends on PCI && ARCH_SHARK
1414 config PCI_HOST_ITE8152
1416 depends on PCI && MACH_ARMCORE
1420 source "drivers/pci/Kconfig"
1422 source "drivers/pcmcia/Kconfig"
1426 menu "Kernel Features"
1431 This option should be selected by machines which have an SMP-
1434 The only effect of this option is to make the SMP-related
1435 options available to the user for configuration.
1438 bool "Symmetric Multi-Processing"
1439 depends on CPU_V6K || CPU_V7
1440 depends on GENERIC_CLOCKEVENTS
1443 select USE_GENERIC_SMP_HELPERS
1445 This enables support for systems with more than one CPU. If you have
1446 a system with only one CPU, like most personal computers, say N. If
1447 you have a system with more than one CPU, say Y.
1449 If you say N here, the kernel will run on single and multiprocessor
1450 machines, but will use only one CPU of a multiprocessor machine. If
1451 you say Y here, the kernel will run on many, but not all, single
1452 processor machines. On a single processor machine, the kernel will
1453 run faster if you say N here.
1455 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1456 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1457 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1459 If you don't know what to do here, say N.
1462 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1463 depends on SMP && !XIP_KERNEL
1466 SMP kernels contain instructions which fail on non-SMP processors.
1467 Enabling this option allows the kernel to modify itself to make
1468 these instructions safe. Disabling it allows about 1K of space
1471 If you don't know what to do here, say Y.
1473 config ARM_CPU_TOPOLOGY
1474 bool "Support cpu topology definition"
1475 depends on SMP && CPU_V7
1478 Support ARM cpu topology definition. The MPIDR register defines
1479 affinity between processors which is then used to describe the cpu
1480 topology of an ARM System.
1483 bool "Multi-core scheduler support"
1484 depends on ARM_CPU_TOPOLOGY
1486 Multi-core scheduler support improves the CPU scheduler's decision
1487 making when dealing with multi-core CPU chips at a cost of slightly
1488 increased overhead in some places. If unsure say N here.
1491 bool "SMT scheduler support"
1492 depends on ARM_CPU_TOPOLOGY
1494 Improves the CPU scheduler's decision making when dealing with
1495 MultiThreading at a cost of slightly increased overhead in some
1496 places. If unsure say N here.
1501 This option enables support for the ARM system coherency unit
1503 config HAVE_ARM_ARCH_TIMER
1504 bool "Architected timer support"
1506 select ARM_ARCH_TIMER
1508 This option enables support for the ARM architected timer
1513 select CLKSRC_OF if OF
1515 This options enables support for the ARM timer and watchdog unit
1518 bool "Multi-Cluster Power Management"
1519 depends on CPU_V7 && SMP
1521 This option provides the common power management infrastructure
1522 for (multi-)cluster based systems, such as big.LITTLE based
1526 prompt "Memory split"
1529 Select the desired split between kernel and user memory.
1531 If you are not absolutely sure what you are doing, leave this
1535 bool "3G/1G user/kernel split"
1537 bool "2G/2G user/kernel split"
1539 bool "1G/3G user/kernel split"
1544 default 0x40000000 if VMSPLIT_1G
1545 default 0x80000000 if VMSPLIT_2G
1549 int "Maximum number of CPUs (2-32)"
1555 bool "Support for hot-pluggable CPUs"
1556 depends on SMP && HOTPLUG
1558 Say Y here to experiment with turning CPUs off and on. CPUs
1559 can be controlled through /sys/devices/system/cpu.
1562 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1565 Say Y here if you want Linux to communicate with system firmware
1566 implementing the PSCI specification for CPU-centric power
1567 management operations described in ARM document number ARM DEN
1568 0022A ("Power State Coordination Interface System Software on
1572 bool "Use local timer interrupts"
1576 Enable support for local timers on SMP platforms, rather then the
1577 legacy IPI broadcast method. Local timers allows the system
1578 accounting to be spread across the timer interval, preventing a
1579 "thundering herd" at every timer tick.
1581 # The GPIO number here must be sorted by descending number. In case of
1582 # a multiplatform kernel, we just want the highest value required by the
1583 # selected platforms.
1586 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1587 default 512 if SOC_OMAP5
1588 default 392 if ARCH_U8500
1589 default 352 if ARCH_VT8500
1590 default 288 if ARCH_SUNXI
1591 default 264 if MACH_H4700
1594 Maximum number of GPIOs in the system.
1596 If unsure, leave the default value.
1598 source kernel/Kconfig.preempt
1602 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1603 ARCH_S5PV210 || ARCH_EXYNOS4
1604 default AT91_TIMER_HZ if ARCH_AT91
1605 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1609 def_bool HIGH_RES_TIMERS
1611 config THUMB2_KERNEL
1612 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1613 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1614 default y if CPU_THUMBONLY
1616 select ARM_ASM_UNIFIED
1619 By enabling this option, the kernel will be compiled in
1620 Thumb-2 mode. A compiler/assembler that understand the unified
1621 ARM-Thumb syntax is needed.
1625 config THUMB2_AVOID_R_ARM_THM_JUMP11
1626 bool "Work around buggy Thumb-2 short branch relocations in gas"
1627 depends on THUMB2_KERNEL && MODULES
1630 Various binutils versions can resolve Thumb-2 branches to
1631 locally-defined, preemptible global symbols as short-range "b.n"
1632 branch instructions.
1634 This is a problem, because there's no guarantee the final
1635 destination of the symbol, or any candidate locations for a
1636 trampoline, are within range of the branch. For this reason, the
1637 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1638 relocation in modules at all, and it makes little sense to add
1641 The symptom is that the kernel fails with an "unsupported
1642 relocation" error when loading some modules.
1644 Until fixed tools are available, passing
1645 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1646 code which hits this problem, at the cost of a bit of extra runtime
1647 stack usage in some cases.
1649 The problem is described in more detail at:
1650 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1652 Only Thumb-2 kernels are affected.
1654 Unless you are sure your tools don't have this problem, say Y.
1656 config ARM_ASM_UNIFIED
1660 bool "Use the ARM EABI to compile the kernel"
1662 This option allows for the kernel to be compiled using the latest
1663 ARM ABI (aka EABI). This is only useful if you are using a user
1664 space environment that is also compiled with EABI.
1666 Since there are major incompatibilities between the legacy ABI and
1667 EABI, especially with regard to structure member alignment, this
1668 option also changes the kernel syscall calling convention to
1669 disambiguate both ABIs and allow for backward compatibility support
1670 (selected with CONFIG_OABI_COMPAT).
1672 To use this you need GCC version 4.0.0 or later.
1675 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1676 depends on AEABI && !THUMB2_KERNEL
1679 This option preserves the old syscall interface along with the
1680 new (ARM EABI) one. It also provides a compatibility layer to
1681 intercept syscalls that have structure arguments which layout
1682 in memory differs between the legacy ABI and the new ARM EABI
1683 (only for non "thumb" binaries). This option adds a tiny
1684 overhead to all syscalls and produces a slightly larger kernel.
1685 If you know you'll be using only pure EABI user space then you
1686 can say N here. If this option is not selected and you attempt
1687 to execute a legacy ABI binary then the result will be
1688 UNPREDICTABLE (in fact it can be predicted that it won't work
1689 at all). If in doubt say Y.
1691 config ARCH_HAS_HOLES_MEMORYMODEL
1694 config ARCH_SPARSEMEM_ENABLE
1697 config ARCH_SPARSEMEM_DEFAULT
1698 def_bool ARCH_SPARSEMEM_ENABLE
1700 config ARCH_SELECT_MEMORY_MODEL
1701 def_bool ARCH_SPARSEMEM_ENABLE
1703 config HAVE_ARCH_PFN_VALID
1704 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1707 bool "High Memory Support"
1710 The address space of ARM processors is only 4 Gigabytes large
1711 and it has to accommodate user address space, kernel address
1712 space as well as some memory mapped IO. That means that, if you
1713 have a large amount of physical memory and/or IO, not all of the
1714 memory can be "permanently mapped" by the kernel. The physical
1715 memory that is not permanently mapped is called "high memory".
1717 Depending on the selected kernel/user memory split, minimum
1718 vmalloc space and actual amount of RAM, you may not need this
1719 option which should result in a slightly faster kernel.
1724 bool "Allocate 2nd-level pagetables from highmem"
1727 config HW_PERF_EVENTS
1728 bool "Enable hardware performance counter support for perf events"
1729 depends on PERF_EVENTS
1732 Enable hardware performance counter support for perf events. If
1733 disabled, perf events will use software events only.
1737 config FORCE_MAX_ZONEORDER
1738 int "Maximum zone order" if ARCH_SHMOBILE
1739 range 11 64 if ARCH_SHMOBILE
1740 default "12" if SOC_AM33XX
1741 default "9" if SA1111
1744 The kernel memory allocator divides physically contiguous memory
1745 blocks into "zones", where each zone is a power of two number of
1746 pages. This option selects the largest power of two that the kernel
1747 keeps in the memory allocator. If you need to allocate very large
1748 blocks of physically contiguous memory, then you may need to
1749 increase this value.
1751 This config option is actually maximum order plus one. For example,
1752 a value of 11 means that the largest free memory block is 2^10 pages.
1754 config ALIGNMENT_TRAP
1756 depends on CPU_CP15_MMU
1757 default y if !ARCH_EBSA110
1758 select HAVE_PROC_CPU if PROC_FS
1760 ARM processors cannot fetch/store information which is not
1761 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1762 address divisible by 4. On 32-bit ARM processors, these non-aligned
1763 fetch/store instructions will be emulated in software if you say
1764 here, which has a severe performance impact. This is necessary for
1765 correct operation of some network protocols. With an IP-only
1766 configuration it is safe to say N, otherwise say Y.
1768 config UACCESS_WITH_MEMCPY
1769 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1771 default y if CPU_FEROCEON
1773 Implement faster copy_to_user and clear_user methods for CPU
1774 cores where a 8-word STM instruction give significantly higher
1775 memory write throughput than a sequence of individual 32bit stores.
1777 A possible side effect is a slight increase in scheduling latency
1778 between threads sharing the same address space if they invoke
1779 such copy operations with large buffers.
1781 However, if the CPU data cache is using a write-allocate mode,
1782 this option is unlikely to provide any performance gain.
1786 prompt "Enable seccomp to safely compute untrusted bytecode"
1788 This kernel feature is useful for number crunching applications
1789 that may need to compute untrusted bytecode during their
1790 execution. By using pipes or other transports made available to
1791 the process as file descriptors supporting the read/write
1792 syscalls, it's possible to isolate those applications in
1793 their own address space using seccomp. Once seccomp is
1794 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1795 and the task is only allowed to execute a few safe syscalls
1796 defined by each seccomp mode.
1798 config CC_STACKPROTECTOR
1799 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1801 This option turns on the -fstack-protector GCC feature. This
1802 feature puts, at the beginning of functions, a canary value on
1803 the stack just before the return address, and validates
1804 the value just before actually returning. Stack based buffer
1805 overflows (that need to overwrite this return address) now also
1806 overwrite the canary, which gets detected and the attack is then
1807 neutralized via a kernel panic.
1808 This feature requires gcc version 4.2 or above.
1815 bool "Xen guest support on ARM (EXPERIMENTAL)"
1816 depends on ARM && AEABI && OF
1817 depends on CPU_V7 && !CPU_V6
1818 depends on !GENERIC_ATOMIC64
1821 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1828 bool "Flattened Device Tree support"
1831 select OF_EARLY_FLATTREE
1833 Include support for flattened device tree machine descriptions.
1836 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1839 This is the traditional way of passing data to the kernel at boot
1840 time. If you are solely relying on the flattened device tree (or
1841 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1842 to remove ATAGS support from your kernel binary. If unsure,
1845 config DEPRECATED_PARAM_STRUCT
1846 bool "Provide old way to pass kernel parameters"
1849 This was deprecated in 2001 and announced to live on for 5 years.
1850 Some old boot loaders still use this way.
1852 # Compressed boot loader in ROM. Yes, we really want to ask about
1853 # TEXT and BSS so we preserve their values in the config files.
1854 config ZBOOT_ROM_TEXT
1855 hex "Compressed ROM boot loader base address"
1858 The physical address at which the ROM-able zImage is to be
1859 placed in the target. Platforms which normally make use of
1860 ROM-able zImage formats normally set this to a suitable
1861 value in their defconfig file.
1863 If ZBOOT_ROM is not enabled, this has no effect.
1865 config ZBOOT_ROM_BSS
1866 hex "Compressed ROM boot loader BSS address"
1869 The base address of an area of read/write memory in the target
1870 for the ROM-able zImage which must be available while the
1871 decompressor is running. It must be large enough to hold the
1872 entire decompressed kernel plus an additional 128 KiB.
1873 Platforms which normally make use of ROM-able zImage formats
1874 normally set this to a suitable value in their defconfig file.
1876 If ZBOOT_ROM is not enabled, this has no effect.
1879 bool "Compressed boot loader in ROM/flash"
1880 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1882 Say Y here if you intend to execute your compressed kernel image
1883 (zImage) directly from ROM or flash. If unsure, say N.
1886 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1887 depends on ZBOOT_ROM && ARCH_SH7372
1888 default ZBOOT_ROM_NONE
1890 Include experimental SD/MMC loading code in the ROM-able zImage.
1891 With this enabled it is possible to write the ROM-able zImage
1892 kernel image to an MMC or SD card and boot the kernel straight
1893 from the reset vector. At reset the processor Mask ROM will load
1894 the first part of the ROM-able zImage which in turn loads the
1895 rest the kernel image to RAM.
1897 config ZBOOT_ROM_NONE
1898 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1900 Do not load image from SD or MMC
1902 config ZBOOT_ROM_MMCIF
1903 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1905 Load image from MMCIF hardware block.
1907 config ZBOOT_ROM_SH_MOBILE_SDHI
1908 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1910 Load image from SDHI hardware block
1914 config ARM_APPENDED_DTB
1915 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1916 depends on OF && !ZBOOT_ROM
1918 With this option, the boot code will look for a device tree binary
1919 (DTB) appended to zImage
1920 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1922 This is meant as a backward compatibility convenience for those
1923 systems with a bootloader that can't be upgraded to accommodate
1924 the documented boot protocol using a device tree.
1926 Beware that there is very little in terms of protection against
1927 this option being confused by leftover garbage in memory that might
1928 look like a DTB header after a reboot if no actual DTB is appended
1929 to zImage. Do not leave this option active in a production kernel
1930 if you don't intend to always append a DTB. Proper passing of the
1931 location into r2 of a bootloader provided DTB is always preferable
1934 config ARM_ATAG_DTB_COMPAT
1935 bool "Supplement the appended DTB with traditional ATAG information"
1936 depends on ARM_APPENDED_DTB
1938 Some old bootloaders can't be updated to a DTB capable one, yet
1939 they provide ATAGs with memory configuration, the ramdisk address,
1940 the kernel cmdline string, etc. Such information is dynamically
1941 provided by the bootloader and can't always be stored in a static
1942 DTB. To allow a device tree enabled kernel to be used with such
1943 bootloaders, this option allows zImage to extract the information
1944 from the ATAG list and store it at run time into the appended DTB.
1947 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1948 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1950 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1951 bool "Use bootloader kernel arguments if available"
1953 Uses the command-line options passed by the boot loader instead of
1954 the device tree bootargs property. If the boot loader doesn't provide
1955 any, the device tree bootargs property will be used.
1957 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1958 bool "Extend with bootloader kernel arguments"
1960 The command-line arguments provided by the boot loader will be
1961 appended to the the device tree bootargs property.
1966 string "Default kernel command string"
1969 On some architectures (EBSA110 and CATS), there is currently no way
1970 for the boot loader to pass arguments to the kernel. For these
1971 architectures, you should supply some command-line options at build
1972 time by entering them here. As a minimum, you should specify the
1973 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1976 prompt "Kernel command line type" if CMDLINE != ""
1977 default CMDLINE_FROM_BOOTLOADER
1980 config CMDLINE_FROM_BOOTLOADER
1981 bool "Use bootloader kernel arguments if available"
1983 Uses the command-line options passed by the boot loader. If
1984 the boot loader doesn't provide any, the default kernel command
1985 string provided in CMDLINE will be used.
1987 config CMDLINE_EXTEND
1988 bool "Extend bootloader kernel arguments"
1990 The command-line arguments provided by the boot loader will be
1991 appended to the default kernel command string.
1993 config CMDLINE_FORCE
1994 bool "Always use the default kernel command string"
1996 Always use the default kernel command string, even if the boot
1997 loader passes other arguments to the kernel.
1998 This is useful if you cannot or don't want to change the
1999 command-line options your boot loader passes to the kernel.
2003 bool "Kernel Execute-In-Place from ROM"
2004 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2006 Execute-In-Place allows the kernel to run from non-volatile storage
2007 directly addressable by the CPU, such as NOR flash. This saves RAM
2008 space since the text section of the kernel is not loaded from flash
2009 to RAM. Read-write sections, such as the data section and stack,
2010 are still copied to RAM. The XIP kernel is not compressed since
2011 it has to run directly from flash, so it will take more space to
2012 store it. The flash address used to link the kernel object files,
2013 and for storing it, is configuration dependent. Therefore, if you
2014 say Y here, you must know the proper physical address where to
2015 store the kernel image depending on your own flash memory usage.
2017 Also note that the make target becomes "make xipImage" rather than
2018 "make zImage" or "make Image". The final kernel binary to put in
2019 ROM memory will be arch/arm/boot/xipImage.
2023 config XIP_PHYS_ADDR
2024 hex "XIP Kernel Physical Location"
2025 depends on XIP_KERNEL
2026 default "0x00080000"
2028 This is the physical address in your flash memory the kernel will
2029 be linked for and stored to. This address is dependent on your
2033 bool "Kexec system call (EXPERIMENTAL)"
2034 depends on (!SMP || PM_SLEEP_SMP)
2036 kexec is a system call that implements the ability to shutdown your
2037 current kernel, and to start another kernel. It is like a reboot
2038 but it is independent of the system firmware. And like a reboot
2039 you can start any kernel with it, not just Linux.
2041 It is an ongoing process to be certain the hardware in a machine
2042 is properly shutdown, so do not be surprised if this code does not
2043 initially work for you. It may help to enable device hotplugging
2047 bool "Export atags in procfs"
2048 depends on ATAGS && KEXEC
2051 Should the atags used to boot the kernel be exported in an "atags"
2052 file in procfs. Useful with kexec.
2055 bool "Build kdump crash kernel (EXPERIMENTAL)"
2057 Generate crash dump after being started by kexec. This should
2058 be normally only set in special crash dump kernels which are
2059 loaded in the main kernel with kexec-tools into a specially
2060 reserved region and then later executed after a crash by
2061 kdump/kexec. The crash dump kernel must be compiled to a
2062 memory address not used by the main kernel
2064 For more details see Documentation/kdump/kdump.txt
2066 config AUTO_ZRELADDR
2067 bool "Auto calculation of the decompressed kernel image address"
2068 depends on !ZBOOT_ROM && !ARCH_U300
2070 ZRELADDR is the physical address where the decompressed kernel
2071 image will be placed. If AUTO_ZRELADDR is selected, the address
2072 will be determined at run-time by masking the current IP with
2073 0xf8000000. This assumes the zImage being placed in the first 128MB
2074 from start of memory.
2078 menu "CPU Power Management"
2081 source "drivers/cpufreq/Kconfig"
2086 Internal configuration node for common cpufreq on Samsung SoC
2088 config CPU_FREQ_S3C24XX
2089 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2090 depends on ARCH_S3C24XX && CPU_FREQ
2093 This enables the CPUfreq driver for the Samsung S3C24XX family
2096 For details, take a look at <file:Documentation/cpu-freq>.
2100 config CPU_FREQ_S3C24XX_PLL
2101 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2102 depends on CPU_FREQ_S3C24XX
2104 Compile in support for changing the PLL frequency from the
2105 S3C24XX series CPUfreq driver. The PLL takes time to settle
2106 after a frequency change, so by default it is not enabled.
2108 This also means that the PLL tables for the selected CPU(s) will
2109 be built which may increase the size of the kernel image.
2111 config CPU_FREQ_S3C24XX_DEBUG
2112 bool "Debug CPUfreq Samsung driver core"
2113 depends on CPU_FREQ_S3C24XX
2115 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2117 config CPU_FREQ_S3C24XX_IODEBUG
2118 bool "Debug CPUfreq Samsung driver IO timing"
2119 depends on CPU_FREQ_S3C24XX
2121 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2123 config CPU_FREQ_S3C24XX_DEBUGFS
2124 bool "Export debugfs for CPUFreq"
2125 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2127 Export status information via debugfs.
2131 source "drivers/cpuidle/Kconfig"
2135 menu "Floating point emulation"
2137 comment "At least one emulation must be selected"
2140 bool "NWFPE math emulation"
2141 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2143 Say Y to include the NWFPE floating point emulator in the kernel.
2144 This is necessary to run most binaries. Linux does not currently
2145 support floating point hardware so you need to say Y here even if
2146 your machine has an FPA or floating point co-processor podule.
2148 You may say N here if you are going to load the Acorn FPEmulator
2149 early in the bootup.
2152 bool "Support extended precision"
2153 depends on FPE_NWFPE
2155 Say Y to include 80-bit support in the kernel floating-point
2156 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2157 Note that gcc does not generate 80-bit operations by default,
2158 so in most cases this option only enlarges the size of the
2159 floating point emulator without any good reason.
2161 You almost surely want to say N here.
2164 bool "FastFPE math emulation (EXPERIMENTAL)"
2165 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2167 Say Y here to include the FAST floating point emulator in the kernel.
2168 This is an experimental much faster emulator which now also has full
2169 precision for the mantissa. It does not support any exceptions.
2170 It is very simple, and approximately 3-6 times faster than NWFPE.
2172 It should be sufficient for most programs. It may be not suitable
2173 for scientific calculations, but you have to check this for yourself.
2174 If you do not feel you need a faster FP emulation you should better
2178 bool "VFP-format floating point maths"
2179 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2181 Say Y to include VFP support code in the kernel. This is needed
2182 if your hardware includes a VFP unit.
2184 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2185 release notes and additional status information.
2187 Say N if your target does not have VFP hardware.
2195 bool "Advanced SIMD (NEON) Extension support"
2196 depends on VFPv3 && CPU_V7
2198 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2203 menu "Userspace binary formats"
2205 source "fs/Kconfig.binfmt"
2208 tristate "RISC OS personality"
2211 Say Y here to include the kernel code necessary if you want to run
2212 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2213 experimental; if this sounds frightening, say N and sleep in peace.
2214 You can also say M here to compile this support as a module (which
2215 will be called arthur).
2219 menu "Power management options"
2221 source "kernel/power/Kconfig"
2223 config ARCH_SUSPEND_POSSIBLE
2224 depends on !ARCH_S5PC100
2225 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2226 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2229 config ARM_CPU_SUSPEND
2234 source "net/Kconfig"
2236 source "drivers/Kconfig"
2240 source "arch/arm/Kconfig.debug"
2242 source "security/Kconfig"
2244 source "crypto/Kconfig"
2246 source "lib/Kconfig"
2248 source "arch/arm/kvm/Kconfig"