4 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
5 select ARCH_HAS_ELF_RANDOMIZE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_HAS_GCOV_PROFILE_ALL
9 select ARCH_MIGHT_HAVE_PC_PARPORT
10 select ARCH_SUPPORTS_ATOMIC_RMW
11 select ARCH_USE_BUILTIN_BSWAP
12 select ARCH_USE_CMPXCHG_LOCKREF
13 select ARCH_WANT_IPC_PARSE_VERSION
14 select BUILDTIME_EXTABLE_SORT if MMU
15 select CLONE_BACKWARDS
16 select CPU_PM if (SUSPEND || CPU_IDLE)
17 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
19 select EDAC_ATOMIC_SCRUB
20 select GENERIC_ALLOCATOR
21 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
22 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
23 select GENERIC_IDLE_POLL_SETUP
24 select GENERIC_IRQ_PROBE
25 select GENERIC_IRQ_SHOW
26 select GENERIC_IRQ_SHOW_LEVEL
27 select GENERIC_PCI_IOMAP
28 select GENERIC_SCHED_CLOCK
29 select GENERIC_SMP_IDLE_THREAD
30 select GENERIC_STRNCPY_FROM_USER
31 select GENERIC_STRNLEN_USER
32 select HANDLE_DOMAIN_IRQ
33 select HARDIRQS_SW_RESEND
34 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
35 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
36 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32
37 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32
38 select HAVE_ARCH_MMAP_RND_BITS if MMU
39 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
40 select HAVE_ARCH_TRACEHOOK
42 select HAVE_CC_STACKPROTECTOR
43 select HAVE_CONTEXT_TRACKING
44 select HAVE_C_RECORDMCOUNT
45 select HAVE_DEBUG_KMEMLEAK
46 select HAVE_DMA_API_DEBUG
48 select HAVE_DMA_CONTIGUOUS if MMU
49 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32
50 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
51 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
52 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
53 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
54 select HAVE_GENERIC_DMA_COHERENT
55 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
56 select HAVE_IDE if PCI || ISA || PCMCIA
57 select HAVE_IRQ_TIME_ACCOUNTING
58 select HAVE_KERNEL_GZIP
59 select HAVE_KERNEL_LZ4
60 select HAVE_KERNEL_LZMA
61 select HAVE_KERNEL_LZO
63 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
64 select HAVE_KRETPROBES if (HAVE_KPROBES)
66 select HAVE_MOD_ARCH_SPECIFIC
67 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
68 select HAVE_OPTPROBES if !THUMB2_KERNEL
69 select HAVE_PERF_EVENTS
71 select HAVE_PERF_USER_STACK_DUMP
72 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
73 select HAVE_REGS_AND_STACK_ACCESS_API
74 select HAVE_SYSCALL_TRACEPOINTS
76 select HAVE_VIRT_CPU_ACCOUNTING_GEN
77 select IRQ_FORCED_THREADING
78 select MODULES_USE_ELF_REL
80 select OF_EARLY_FLATTREE if OF
81 select OF_RESERVED_MEM if OF
83 select OLD_SIGSUSPEND3
84 select PERF_USE_VMALLOC
86 select SYS_SUPPORTS_APM_EMULATION
87 # Above selects are sorted alphabetically; please add new ones
88 # according to that. Thanks.
90 The ARM series is a line of low-power-consumption RISC chip designs
91 licensed by ARM Ltd and targeted at embedded applications and
92 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
93 manufactured, but legacy ARM-based PC hardware remains popular in
94 Europe. There is an ARM Linux project with a web page at
95 <http://www.arm.linux.org.uk/>.
97 config ARM_HAS_SG_CHAIN
98 select ARCH_HAS_SG_CHAIN
101 config NEED_SG_DMA_LENGTH
104 config ARM_DMA_USE_IOMMU
106 select ARM_HAS_SG_CHAIN
107 select NEED_SG_DMA_LENGTH
110 config MIGHT_HAVE_PCI
113 config SYS_SUPPORTS_APM_EMULATION
118 select GENERIC_ALLOCATOR
129 The Extended Industry Standard Architecture (EISA) bus was
130 developed as an open alternative to the IBM MicroChannel bus.
132 The EISA bus provided some of the features of the IBM MicroChannel
133 bus while maintaining backward compatibility with cards made for
134 the older ISA bus. The EISA bus saw limited use between 1988 and
135 1995 when it was made obsolete by the PCI bus.
137 Say Y here if you are building a kernel for an EISA-based machine.
144 config STACKTRACE_SUPPORT
148 config HAVE_LATENCYTOP_SUPPORT
153 config LOCKDEP_SUPPORT
157 config TRACE_IRQFLAGS_SUPPORT
161 config RWSEM_XCHGADD_ALGORITHM
165 config ARCH_HAS_ILOG2_U32
168 config ARCH_HAS_ILOG2_U64
171 config ARCH_HAS_BANDGAP
174 config FIX_EARLYCON_MEM
177 config GENERIC_HWEIGHT
181 config GENERIC_CALIBRATE_DELAY
185 config ARCH_MAY_HAVE_PC_FDC
191 config NEED_DMA_MAP_STATE
194 config ARCH_SUPPORTS_UPROBES
197 config ARCH_HAS_DMA_SET_COHERENT_MASK
200 config GENERIC_ISA_DMA
206 config NEED_RET_TO_USER
214 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
215 default DRAM_BASE if REMAP_VECTORS_TO_RAM
218 The base address of exception vectors. This must be two pages
221 config ARM_PATCH_PHYS_VIRT
222 bool "Patch physical to virtual translations at runtime" if EMBEDDED
224 depends on !XIP_KERNEL && MMU
225 depends on !ARCH_REALVIEW || !SPARSEMEM
227 Patch phys-to-virt and virt-to-phys translation functions at
228 boot and module load time according to the position of the
229 kernel in system memory.
231 This can only be used with non-XIP MMU kernels where the base
232 of physical memory is at a 16MB boundary.
234 Only disable this option if you know that you do not require
235 this feature (eg, building a kernel for a single machine) and
236 you need to shrink the kernel to the minimal size.
238 config NEED_MACH_IO_H
241 Select this when mach/io.h is required to provide special
242 definitions for this platform. The need for mach/io.h should
243 be avoided when possible.
245 config NEED_MACH_MEMORY_H
248 Select this when mach/memory.h is required to provide special
249 definitions for this platform. The need for mach/memory.h should
250 be avoided when possible.
253 hex "Physical address of main memory" if MMU
254 depends on !ARM_PATCH_PHYS_VIRT
255 default DRAM_BASE if !MMU
256 default 0x00000000 if ARCH_EBSA110 || \
261 (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
262 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
263 default 0x20000000 if ARCH_S5PV210
264 default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
265 default 0xc0000000 if ARCH_SA1100
267 Please provide the physical address corresponding to the
268 location of main memory in your system.
274 config PGTABLE_LEVELS
276 default 3 if ARM_LPAE
279 source "init/Kconfig"
281 source "kernel/Kconfig.freezer"
286 bool "MMU-based Paged Memory Management Support"
289 Select if you want MMU-based virtualised addressing space
290 support by paged memory management. If unsure, say 'Y'.
292 config ARCH_MMAP_RND_BITS_MIN
295 config ARCH_MMAP_RND_BITS_MAX
296 default 14 if PAGE_OFFSET=0x40000000
297 default 15 if PAGE_OFFSET=0x80000000
301 # The "ARM system type" choice list is ordered alphabetically by option
302 # text. Please add new entries in the option alphabetic order.
305 prompt "ARM system type"
306 default ARCH_VERSATILE if !MMU
307 default ARCH_MULTIPLATFORM if MMU
309 config ARCH_MULTIPLATFORM
310 bool "Allow multiple platforms to be selected"
312 select ARCH_WANT_OPTIONAL_GPIOLIB
313 select ARM_HAS_SG_CHAIN
314 select ARM_PATCH_PHYS_VIRT
318 select GENERIC_CLOCKEVENTS
319 select MIGHT_HAVE_PCI
320 select MULTI_IRQ_HANDLER
324 config ARM_SINGLE_ARMV7M
325 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
327 select ARCH_WANT_OPTIONAL_GPIOLIB
333 select GENERIC_CLOCKEVENTS
339 bool "ARM Ltd. RealView family"
340 select ARCH_WANT_OPTIONAL_GPIOLIB
342 select ARM_TIMER_SP804
344 select COMMON_CLK_VERSATILE
345 select GENERIC_CLOCKEVENTS
346 select GPIO_PL061 if GPIOLIB
348 select NEED_MACH_MEMORY_H
349 select PLAT_VERSATILE
350 select PLAT_VERSATILE_SCHED_CLOCK
352 This enables support for ARM Ltd RealView boards.
354 config ARCH_VERSATILE
355 bool "ARM Ltd. Versatile family"
356 select ARCH_WANT_OPTIONAL_GPIOLIB
358 select ARM_TIMER_SP804
361 select GENERIC_CLOCKEVENTS
362 select HAVE_MACH_CLKDEV
364 select PLAT_VERSATILE
365 select PLAT_VERSATILE_CLOCK
366 select PLAT_VERSATILE_SCHED_CLOCK
367 select VERSATILE_FPGA_IRQ
369 This enables support for ARM Ltd Versatile board.
372 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
373 select ARCH_REQUIRE_GPIOLIB
378 select GENERIC_CLOCKEVENTS
382 Support for Cirrus Logic 711x/721x/731x based boards.
385 bool "Cortina Systems Gemini"
386 select ARCH_REQUIRE_GPIOLIB
389 select GENERIC_CLOCKEVENTS
391 Support for the Cortina Systems Gemini family SoCs
395 select ARCH_USES_GETTIMEOFFSET
398 select NEED_MACH_IO_H
399 select NEED_MACH_MEMORY_H
402 This is an evaluation board for the StrongARM processor available
403 from Digital. It has limited hardware on-board, including an
404 Ethernet interface, two PCMCIA sockets, two serial ports and a
409 select ARCH_HAS_HOLES_MEMORYMODEL
410 select ARCH_REQUIRE_GPIOLIB
412 select ARM_PATCH_PHYS_VIRT
418 select GENERIC_CLOCKEVENTS
420 This enables support for the Cirrus EP93xx series of CPUs.
422 config ARCH_FOOTBRIDGE
426 select GENERIC_CLOCKEVENTS
428 select NEED_MACH_IO_H if !MMU
429 select NEED_MACH_MEMORY_H
431 Support for systems based on the DC21285 companion chip
432 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
435 bool "Hilscher NetX based"
439 select GENERIC_CLOCKEVENTS
441 This enables support for systems based on the Hilscher NetX Soc
447 select NEED_MACH_MEMORY_H
448 select NEED_RET_TO_USER
454 Support for Intel's IOP13XX (XScale) family of processors.
459 select ARCH_REQUIRE_GPIOLIB
462 select NEED_RET_TO_USER
466 Support for Intel's 80219 and IOP32X (XScale) family of
472 select ARCH_REQUIRE_GPIOLIB
475 select NEED_RET_TO_USER
479 Support for Intel's IOP33X (XScale) family of processors.
484 select ARCH_HAS_DMA_SET_COHERENT_MASK
485 select ARCH_REQUIRE_GPIOLIB
486 select ARCH_SUPPORTS_BIG_ENDIAN
489 select DMABOUNCE if PCI
490 select GENERIC_CLOCKEVENTS
491 select MIGHT_HAVE_PCI
492 select NEED_MACH_IO_H
493 select USB_EHCI_BIG_ENDIAN_DESC
494 select USB_EHCI_BIG_ENDIAN_MMIO
496 Support for Intel's IXP4XX (XScale) family of processors.
500 select ARCH_REQUIRE_GPIOLIB
502 select GENERIC_CLOCKEVENTS
503 select MIGHT_HAVE_PCI
507 select PLAT_ORION_LEGACY
509 Support for the Marvell Dove SoC 88AP510
512 bool "Marvell MV78xx0"
513 select ARCH_REQUIRE_GPIOLIB
515 select GENERIC_CLOCKEVENTS
518 select PLAT_ORION_LEGACY
520 Support for the following Marvell MV78xx0 series SoCs:
526 select ARCH_REQUIRE_GPIOLIB
528 select GENERIC_CLOCKEVENTS
531 select PLAT_ORION_LEGACY
532 select MULTI_IRQ_HANDLER
534 Support for the following Marvell Orion 5x series SoCs:
535 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
536 Orion-2 (5281), Orion-1-90 (6183).
539 bool "Marvell PXA168/910/MMP2"
541 select ARCH_REQUIRE_GPIOLIB
543 select GENERIC_ALLOCATOR
544 select GENERIC_CLOCKEVENTS
547 select MULTI_IRQ_HANDLER
552 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
555 bool "Micrel/Kendin KS8695"
556 select ARCH_REQUIRE_GPIOLIB
559 select GENERIC_CLOCKEVENTS
560 select NEED_MACH_MEMORY_H
562 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
563 System-on-Chip devices.
566 bool "Nuvoton W90X900 CPU"
567 select ARCH_REQUIRE_GPIOLIB
571 select GENERIC_CLOCKEVENTS
573 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
574 At present, the w90x900 has been renamed nuc900, regarding
575 the ARM series product line, you can login the following
576 link address to know more.
578 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
579 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
583 select ARCH_REQUIRE_GPIOLIB
588 select GENERIC_CLOCKEVENTS
592 Support for the NXP LPC32XX family of processors
595 bool "PXA2xx/PXA3xx-based"
598 select ARCH_REQUIRE_GPIOLIB
599 select ARM_CPU_SUSPEND if PM
605 select GENERIC_CLOCKEVENTS
609 select MULTI_IRQ_HANDLER
613 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
619 select ARCH_MAY_HAVE_PC_FDC
620 select ARCH_SPARSEMEM_ENABLE
621 select ARCH_USES_GETTIMEOFFSET
625 select HAVE_PATA_PLATFORM
627 select NEED_MACH_IO_H
628 select NEED_MACH_MEMORY_H
632 On the Acorn Risc-PC, Linux can support the internal IDE disk and
633 CD-ROM interface, serial and parallel port, and the floppy drive.
638 select ARCH_REQUIRE_GPIOLIB
639 select ARCH_SPARSEMEM_ENABLE
644 select GENERIC_CLOCKEVENTS
648 select MULTI_IRQ_HANDLER
649 select NEED_MACH_MEMORY_H
652 Support for StrongARM 11x0 based boards.
655 bool "Samsung S3C24XX SoCs"
656 select ARCH_REQUIRE_GPIOLIB
659 select CLKSRC_SAMSUNG_PWM
660 select GENERIC_CLOCKEVENTS
662 select HAVE_S3C2410_I2C if I2C
663 select HAVE_S3C2410_WATCHDOG if WATCHDOG
664 select HAVE_S3C_RTC if RTC_CLASS
665 select MULTI_IRQ_HANDLER
666 select NEED_MACH_IO_H
669 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
670 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
671 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
672 Samsung SMDK2410 development board (and derivatives).
675 bool "Samsung S3C64XX"
676 select ARCH_REQUIRE_GPIOLIB
681 select CLKSRC_SAMSUNG_PWM
682 select COMMON_CLK_SAMSUNG
684 select GENERIC_CLOCKEVENTS
686 select HAVE_S3C2410_I2C if I2C
687 select HAVE_S3C2410_WATCHDOG if WATCHDOG
691 select PM_GENERIC_DOMAINS if PM
693 select S3C_GPIO_TRACK
695 select SAMSUNG_WAKEMASK
696 select SAMSUNG_WDT_RESET
698 Samsung S3C64XX series based systems
702 select ARCH_HAS_HOLES_MEMORYMODEL
703 select ARCH_REQUIRE_GPIOLIB
705 select GENERIC_ALLOCATOR
706 select GENERIC_CLOCKEVENTS
707 select GENERIC_IRQ_CHIP
712 Support for TI's DaVinci platform.
717 select ARCH_HAS_HOLES_MEMORYMODEL
719 select ARCH_REQUIRE_GPIOLIB
722 select GENERIC_CLOCKEVENTS
723 select GENERIC_IRQ_CHIP
726 select MULTI_IRQ_HANDLER
727 select NEED_MACH_IO_H if PCCARD
728 select NEED_MACH_MEMORY_H
731 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
735 menu "Multiple platform selection"
736 depends on ARCH_MULTIPLATFORM
738 comment "CPU Core family selection"
741 bool "ARMv4 based platforms (FA526)"
742 depends on !ARCH_MULTI_V6_V7
743 select ARCH_MULTI_V4_V5
746 config ARCH_MULTI_V4T
747 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
748 depends on !ARCH_MULTI_V6_V7
749 select ARCH_MULTI_V4_V5
750 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
751 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
752 CPU_ARM925T || CPU_ARM940T)
755 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
756 depends on !ARCH_MULTI_V6_V7
757 select ARCH_MULTI_V4_V5
758 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
759 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
760 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
762 config ARCH_MULTI_V4_V5
766 bool "ARMv6 based platforms (ARM11)"
767 select ARCH_MULTI_V6_V7
771 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
773 select ARCH_MULTI_V6_V7
777 config ARCH_MULTI_V6_V7
779 select MIGHT_HAVE_CACHE_L2X0
781 config ARCH_MULTI_CPU_AUTO
782 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
788 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
793 select HAVE_ARM_ARCH_TIMER
796 # This is sorted alphabetically by mach-* pathname. However, plat-*
797 # Kconfigs may be included either alphabetically (according to the
798 # plat- suffix) or along side the corresponding mach-* source.
800 source "arch/arm/mach-mvebu/Kconfig"
802 source "arch/arm/mach-alpine/Kconfig"
804 source "arch/arm/mach-asm9260/Kconfig"
806 source "arch/arm/mach-at91/Kconfig"
808 source "arch/arm/mach-axxia/Kconfig"
810 source "arch/arm/mach-bcm/Kconfig"
812 source "arch/arm/mach-berlin/Kconfig"
814 source "arch/arm/mach-clps711x/Kconfig"
816 source "arch/arm/mach-cns3xxx/Kconfig"
818 source "arch/arm/mach-davinci/Kconfig"
820 source "arch/arm/mach-digicolor/Kconfig"
822 source "arch/arm/mach-dove/Kconfig"
824 source "arch/arm/mach-ep93xx/Kconfig"
826 source "arch/arm/mach-footbridge/Kconfig"
828 source "arch/arm/mach-gemini/Kconfig"
830 source "arch/arm/mach-highbank/Kconfig"
832 source "arch/arm/mach-hisi/Kconfig"
834 source "arch/arm/mach-integrator/Kconfig"
836 source "arch/arm/mach-iop32x/Kconfig"
838 source "arch/arm/mach-iop33x/Kconfig"
840 source "arch/arm/mach-iop13xx/Kconfig"
842 source "arch/arm/mach-ixp4xx/Kconfig"
844 source "arch/arm/mach-keystone/Kconfig"
846 source "arch/arm/mach-ks8695/Kconfig"
848 source "arch/arm/mach-meson/Kconfig"
850 source "arch/arm/mach-moxart/Kconfig"
852 source "arch/arm/mach-mv78xx0/Kconfig"
854 source "arch/arm/mach-imx/Kconfig"
856 source "arch/arm/mach-mediatek/Kconfig"
858 source "arch/arm/mach-mxs/Kconfig"
860 source "arch/arm/mach-netx/Kconfig"
862 source "arch/arm/mach-nomadik/Kconfig"
864 source "arch/arm/mach-nspire/Kconfig"
866 source "arch/arm/plat-omap/Kconfig"
868 source "arch/arm/mach-omap1/Kconfig"
870 source "arch/arm/mach-omap2/Kconfig"
872 source "arch/arm/mach-orion5x/Kconfig"
874 source "arch/arm/mach-picoxcell/Kconfig"
876 source "arch/arm/mach-pxa/Kconfig"
877 source "arch/arm/plat-pxa/Kconfig"
879 source "arch/arm/mach-mmp/Kconfig"
881 source "arch/arm/mach-qcom/Kconfig"
883 source "arch/arm/mach-realview/Kconfig"
885 source "arch/arm/mach-rockchip/Kconfig"
887 source "arch/arm/mach-sa1100/Kconfig"
889 source "arch/arm/mach-socfpga/Kconfig"
891 source "arch/arm/mach-spear/Kconfig"
893 source "arch/arm/mach-sti/Kconfig"
895 source "arch/arm/mach-s3c24xx/Kconfig"
897 source "arch/arm/mach-s3c64xx/Kconfig"
899 source "arch/arm/mach-s5pv210/Kconfig"
901 source "arch/arm/mach-exynos/Kconfig"
902 source "arch/arm/plat-samsung/Kconfig"
904 source "arch/arm/mach-shmobile/Kconfig"
906 source "arch/arm/mach-sunxi/Kconfig"
908 source "arch/arm/mach-prima2/Kconfig"
910 source "arch/arm/mach-tegra/Kconfig"
912 source "arch/arm/mach-u300/Kconfig"
914 source "arch/arm/mach-uniphier/Kconfig"
916 source "arch/arm/mach-ux500/Kconfig"
918 source "arch/arm/mach-versatile/Kconfig"
920 source "arch/arm/mach-vexpress/Kconfig"
921 source "arch/arm/plat-versatile/Kconfig"
923 source "arch/arm/mach-vt8500/Kconfig"
925 source "arch/arm/mach-w90x900/Kconfig"
927 source "arch/arm/mach-zx/Kconfig"
929 source "arch/arm/mach-zynq/Kconfig"
931 # ARMv7-M architecture
933 bool "Energy Micro efm32"
934 depends on ARM_SINGLE_ARMV7M
935 select ARCH_REQUIRE_GPIOLIB
937 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
941 bool "NXP LPC18xx/LPC43xx"
942 depends on ARM_SINGLE_ARMV7M
943 select ARCH_HAS_RESET_CONTROLLER
945 select CLKSRC_LPC32XX
948 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
949 high performance microcontrollers.
952 bool "STMicrolectronics STM32"
953 depends on ARM_SINGLE_ARMV7M
954 select ARCH_HAS_RESET_CONTROLLER
955 select ARMV7M_SYSTICK
957 select RESET_CONTROLLER
959 Support for STMicroelectronics STM32 processors.
961 # Definitions to make life easier
967 select GENERIC_CLOCKEVENTS
973 select GENERIC_IRQ_CHIP
976 config PLAT_ORION_LEGACY
983 config PLAT_VERSATILE
986 source "arch/arm/firmware/Kconfig"
988 source arch/arm/mm/Kconfig
991 bool "Enable iWMMXt support"
992 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
993 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
995 Enable support for iWMMXt context switching at run time if
996 running on a CPU that supports it.
998 config MULTI_IRQ_HANDLER
1001 Allow each machine to specify it's own IRQ handler at run time.
1004 source "arch/arm/Kconfig-nommu"
1007 config PJ4B_ERRATA_4742
1008 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1009 depends on CPU_PJ4B && MACH_ARMADA_370
1012 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1013 Event (WFE) IDLE states, a specific timing sensitivity exists between
1014 the retiring WFI/WFE instructions and the newly issued subsequent
1015 instructions. This sensitivity can result in a CPU hang scenario.
1017 The software must insert either a Data Synchronization Barrier (DSB)
1018 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1021 config ARM_ERRATA_326103
1022 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1025 Executing a SWP instruction to read-only memory does not set bit 11
1026 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1027 treat the access as a read, preventing a COW from occurring and
1028 causing the faulting task to livelock.
1030 config ARM_ERRATA_411920
1031 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1032 depends on CPU_V6 || CPU_V6K
1034 Invalidation of the Instruction Cache operation can
1035 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1036 It does not affect the MPCore. This option enables the ARM Ltd.
1037 recommended workaround.
1039 config ARM_ERRATA_430973
1040 bool "ARM errata: Stale prediction on replaced interworking branch"
1043 This option enables the workaround for the 430973 Cortex-A8
1044 r1p* erratum. If a code sequence containing an ARM/Thumb
1045 interworking branch is replaced with another code sequence at the
1046 same virtual address, whether due to self-modifying code or virtual
1047 to physical address re-mapping, Cortex-A8 does not recover from the
1048 stale interworking branch prediction. This results in Cortex-A8
1049 executing the new code sequence in the incorrect ARM or Thumb state.
1050 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1051 and also flushes the branch target cache at every context switch.
1052 Note that setting specific bits in the ACTLR register may not be
1053 available in non-secure mode.
1055 config ARM_ERRATA_458693
1056 bool "ARM errata: Processor deadlock when a false hazard is created"
1058 depends on !ARCH_MULTIPLATFORM
1060 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1061 erratum. For very specific sequences of memory operations, it is
1062 possible for a hazard condition intended for a cache line to instead
1063 be incorrectly associated with a different cache line. This false
1064 hazard might then cause a processor deadlock. The workaround enables
1065 the L1 caching of the NEON accesses and disables the PLD instruction
1066 in the ACTLR register. Note that setting specific bits in the ACTLR
1067 register may not be available in non-secure mode.
1069 config ARM_ERRATA_460075
1070 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1072 depends on !ARCH_MULTIPLATFORM
1074 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1075 erratum. Any asynchronous access to the L2 cache may encounter a
1076 situation in which recent store transactions to the L2 cache are lost
1077 and overwritten with stale memory contents from external memory. The
1078 workaround disables the write-allocate mode for the L2 cache via the
1079 ACTLR register. Note that setting specific bits in the ACTLR register
1080 may not be available in non-secure mode.
1082 config ARM_ERRATA_742230
1083 bool "ARM errata: DMB operation may be faulty"
1084 depends on CPU_V7 && SMP
1085 depends on !ARCH_MULTIPLATFORM
1087 This option enables the workaround for the 742230 Cortex-A9
1088 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1089 between two write operations may not ensure the correct visibility
1090 ordering of the two writes. This workaround sets a specific bit in
1091 the diagnostic register of the Cortex-A9 which causes the DMB
1092 instruction to behave as a DSB, ensuring the correct behaviour of
1095 config ARM_ERRATA_742231
1096 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1097 depends on CPU_V7 && SMP
1098 depends on !ARCH_MULTIPLATFORM
1100 This option enables the workaround for the 742231 Cortex-A9
1101 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1102 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1103 accessing some data located in the same cache line, may get corrupted
1104 data due to bad handling of the address hazard when the line gets
1105 replaced from one of the CPUs at the same time as another CPU is
1106 accessing it. This workaround sets specific bits in the diagnostic
1107 register of the Cortex-A9 which reduces the linefill issuing
1108 capabilities of the processor.
1110 config ARM_ERRATA_643719
1111 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1112 depends on CPU_V7 && SMP
1115 This option enables the workaround for the 643719 Cortex-A9 (prior to
1116 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1117 register returns zero when it should return one. The workaround
1118 corrects this value, ensuring cache maintenance operations which use
1119 it behave as intended and avoiding data corruption.
1121 config ARM_ERRATA_720789
1122 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1125 This option enables the workaround for the 720789 Cortex-A9 (prior to
1126 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1127 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1128 As a consequence of this erratum, some TLB entries which should be
1129 invalidated are not, resulting in an incoherency in the system page
1130 tables. The workaround changes the TLB flushing routines to invalidate
1131 entries regardless of the ASID.
1133 config ARM_ERRATA_743622
1134 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1136 depends on !ARCH_MULTIPLATFORM
1138 This option enables the workaround for the 743622 Cortex-A9
1139 (r2p*) erratum. Under very rare conditions, a faulty
1140 optimisation in the Cortex-A9 Store Buffer may lead to data
1141 corruption. This workaround sets a specific bit in the diagnostic
1142 register of the Cortex-A9 which disables the Store Buffer
1143 optimisation, preventing the defect from occurring. This has no
1144 visible impact on the overall performance or power consumption of the
1147 config ARM_ERRATA_751472
1148 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1150 depends on !ARCH_MULTIPLATFORM
1152 This option enables the workaround for the 751472 Cortex-A9 (prior
1153 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1154 completion of a following broadcasted operation if the second
1155 operation is received by a CPU before the ICIALLUIS has completed,
1156 potentially leading to corrupted entries in the cache or TLB.
1158 config ARM_ERRATA_754322
1159 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1162 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1163 r3p*) erratum. A speculative memory access may cause a page table walk
1164 which starts prior to an ASID switch but completes afterwards. This
1165 can populate the micro-TLB with a stale entry which may be hit with
1166 the new ASID. This workaround places two dsb instructions in the mm
1167 switching code so that no page table walks can cross the ASID switch.
1169 config ARM_ERRATA_754327
1170 bool "ARM errata: no automatic Store Buffer drain"
1171 depends on CPU_V7 && SMP
1173 This option enables the workaround for the 754327 Cortex-A9 (prior to
1174 r2p0) erratum. The Store Buffer does not have any automatic draining
1175 mechanism and therefore a livelock may occur if an external agent
1176 continuously polls a memory location waiting to observe an update.
1177 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1178 written polling loops from denying visibility of updates to memory.
1180 config ARM_ERRATA_364296
1181 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1184 This options enables the workaround for the 364296 ARM1136
1185 r0p2 erratum (possible cache data corruption with
1186 hit-under-miss enabled). It sets the undocumented bit 31 in
1187 the auxiliary control register and the FI bit in the control
1188 register, thus disabling hit-under-miss without putting the
1189 processor into full low interrupt latency mode. ARM11MPCore
1192 config ARM_ERRATA_764369
1193 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1194 depends on CPU_V7 && SMP
1196 This option enables the workaround for erratum 764369
1197 affecting Cortex-A9 MPCore with two or more processors (all
1198 current revisions). Under certain timing circumstances, a data
1199 cache line maintenance operation by MVA targeting an Inner
1200 Shareable memory region may fail to proceed up to either the
1201 Point of Coherency or to the Point of Unification of the
1202 system. This workaround adds a DSB instruction before the
1203 relevant cache maintenance functions and sets a specific bit
1204 in the diagnostic control register of the SCU.
1206 config ARM_ERRATA_775420
1207 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1210 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1211 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1212 operation aborts with MMU exception, it might cause the processor
1213 to deadlock. This workaround puts DSB before executing ISB if
1214 an abort may occur on cache maintenance.
1216 config ARM_ERRATA_798181
1217 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1218 depends on CPU_V7 && SMP
1220 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1221 adequately shooting down all use of the old entries. This
1222 option enables the Linux kernel workaround for this erratum
1223 which sends an IPI to the CPUs that are running the same ASID
1224 as the one being invalidated.
1226 config ARM_ERRATA_773022
1227 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1230 This option enables the workaround for the 773022 Cortex-A15
1231 (up to r0p4) erratum. In certain rare sequences of code, the
1232 loop buffer may deliver incorrect instructions. This
1233 workaround disables the loop buffer to avoid the erratum.
1237 source "arch/arm/common/Kconfig"
1244 Find out whether you have ISA slots on your motherboard. ISA is the
1245 name of a bus system, i.e. the way the CPU talks to the other stuff
1246 inside your box. Other bus systems are PCI, EISA, MicroChannel
1247 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1248 newer boards don't support it. If you have ISA, say Y, otherwise N.
1250 # Select ISA DMA controller support
1255 # Select ISA DMA interface
1260 bool "PCI support" if MIGHT_HAVE_PCI
1262 Find out whether you have a PCI motherboard. PCI is the name of a
1263 bus system, i.e. the way the CPU talks to the other stuff inside
1264 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1265 VESA. If you have PCI, say Y, otherwise N.
1271 config PCI_DOMAINS_GENERIC
1272 def_bool PCI_DOMAINS
1274 config PCI_NANOENGINE
1275 bool "BSE nanoEngine PCI support"
1276 depends on SA1100_NANOENGINE
1278 Enable PCI on the BSE nanoEngine board.
1283 config PCI_HOST_ITE8152
1285 depends on PCI && MACH_ARMCORE
1289 source "drivers/pci/Kconfig"
1290 source "drivers/pci/pcie/Kconfig"
1292 source "drivers/pcmcia/Kconfig"
1296 menu "Kernel Features"
1301 This option should be selected by machines which have an SMP-
1304 The only effect of this option is to make the SMP-related
1305 options available to the user for configuration.
1308 bool "Symmetric Multi-Processing"
1309 depends on CPU_V6K || CPU_V7
1310 depends on GENERIC_CLOCKEVENTS
1312 depends on MMU || ARM_MPU
1315 This enables support for systems with more than one CPU. If you have
1316 a system with only one CPU, say N. If you have a system with more
1317 than one CPU, say Y.
1319 If you say N here, the kernel will run on uni- and multiprocessor
1320 machines, but will use only one CPU of a multiprocessor machine. If
1321 you say Y here, the kernel will run on many, but not all,
1322 uniprocessor machines. On a uniprocessor machine, the kernel
1323 will run faster if you say N here.
1325 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1326 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1327 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1329 If you don't know what to do here, say N.
1332 bool "Allow booting SMP kernel on uniprocessor systems"
1333 depends on SMP && !XIP_KERNEL && MMU
1336 SMP kernels contain instructions which fail on non-SMP processors.
1337 Enabling this option allows the kernel to modify itself to make
1338 these instructions safe. Disabling it allows about 1K of space
1341 If you don't know what to do here, say Y.
1343 config ARM_CPU_TOPOLOGY
1344 bool "Support cpu topology definition"
1345 depends on SMP && CPU_V7
1348 Support ARM cpu topology definition. The MPIDR register defines
1349 affinity between processors which is then used to describe the cpu
1350 topology of an ARM System.
1353 bool "Multi-core scheduler support"
1354 depends on ARM_CPU_TOPOLOGY
1356 Multi-core scheduler support improves the CPU scheduler's decision
1357 making when dealing with multi-core CPU chips at a cost of slightly
1358 increased overhead in some places. If unsure say N here.
1361 bool "SMT scheduler support"
1362 depends on ARM_CPU_TOPOLOGY
1364 Improves the CPU scheduler's decision making when dealing with
1365 MultiThreading at a cost of slightly increased overhead in some
1366 places. If unsure say N here.
1371 This option enables support for the ARM system coherency unit
1373 config HAVE_ARM_ARCH_TIMER
1374 bool "Architected timer support"
1376 select ARM_ARCH_TIMER
1377 select GENERIC_CLOCKEVENTS
1379 This option enables support for the ARM architected timer
1383 select CLKSRC_OF if OF
1385 This options enables support for the ARM timer and watchdog unit
1388 bool "Multi-Cluster Power Management"
1389 depends on CPU_V7 && SMP
1391 This option provides the common power management infrastructure
1392 for (multi-)cluster based systems, such as big.LITTLE based
1395 config MCPM_QUAD_CLUSTER
1399 To avoid wasting resources unnecessarily, MCPM only supports up
1400 to 2 clusters by default.
1401 Platforms with 3 or 4 clusters that use MCPM must select this
1402 option to allow the additional clusters to be managed.
1405 bool "big.LITTLE support (Experimental)"
1406 depends on CPU_V7 && SMP
1409 This option enables support selections for the big.LITTLE
1410 system architecture.
1413 bool "big.LITTLE switcher support"
1414 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1415 select ARM_CPU_SUSPEND
1418 The big.LITTLE "switcher" provides the core functionality to
1419 transparently handle transition between a cluster of A15's
1420 and a cluster of A7's in a big.LITTLE system.
1422 config BL_SWITCHER_DUMMY_IF
1423 tristate "Simple big.LITTLE switcher user interface"
1424 depends on BL_SWITCHER && DEBUG_KERNEL
1426 This is a simple and dummy char dev interface to control
1427 the big.LITTLE switcher core code. It is meant for
1428 debugging purposes only.
1431 prompt "Memory split"
1435 Select the desired split between kernel and user memory.
1437 If you are not absolutely sure what you are doing, leave this
1441 bool "3G/1G user/kernel split"
1442 config VMSPLIT_3G_OPT
1443 bool "3G/1G user/kernel split (for full 1G low memory)"
1445 bool "2G/2G user/kernel split"
1447 bool "1G/3G user/kernel split"
1452 default PHYS_OFFSET if !MMU
1453 default 0x40000000 if VMSPLIT_1G
1454 default 0x80000000 if VMSPLIT_2G
1455 default 0xB0000000 if VMSPLIT_3G_OPT
1459 int "Maximum number of CPUs (2-32)"
1465 bool "Support for hot-pluggable CPUs"
1468 Say Y here to experiment with turning CPUs off and on. CPUs
1469 can be controlled through /sys/devices/system/cpu.
1472 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1476 Say Y here if you want Linux to communicate with system firmware
1477 implementing the PSCI specification for CPU-centric power
1478 management operations described in ARM document number ARM DEN
1479 0022A ("Power State Coordination Interface System Software on
1482 # The GPIO number here must be sorted by descending number. In case of
1483 # a multiplatform kernel, we just want the highest value required by the
1484 # selected platforms.
1487 default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1489 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1490 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1491 default 416 if ARCH_SUNXI
1492 default 392 if ARCH_U8500
1493 default 352 if ARCH_VT8500
1494 default 288 if ARCH_ROCKCHIP
1495 default 264 if MACH_H4700
1498 Maximum number of GPIOs in the system.
1500 If unsure, leave the default value.
1502 source kernel/Kconfig.preempt
1506 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1507 ARCH_S5PV210 || ARCH_EXYNOS4
1508 default 128 if SOC_AT91RM9200
1512 depends on HZ_FIXED = 0
1513 prompt "Timer frequency"
1537 default HZ_FIXED if HZ_FIXED != 0
1538 default 100 if HZ_100
1539 default 200 if HZ_200
1540 default 250 if HZ_250
1541 default 300 if HZ_300
1542 default 500 if HZ_500
1546 def_bool HIGH_RES_TIMERS
1548 config THUMB2_KERNEL
1549 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1550 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1551 default y if CPU_THUMBONLY
1553 select ARM_ASM_UNIFIED
1556 By enabling this option, the kernel will be compiled in
1557 Thumb-2 mode. A compiler/assembler that understand the unified
1558 ARM-Thumb syntax is needed.
1562 config THUMB2_AVOID_R_ARM_THM_JUMP11
1563 bool "Work around buggy Thumb-2 short branch relocations in gas"
1564 depends on THUMB2_KERNEL && MODULES
1567 Various binutils versions can resolve Thumb-2 branches to
1568 locally-defined, preemptible global symbols as short-range "b.n"
1569 branch instructions.
1571 This is a problem, because there's no guarantee the final
1572 destination of the symbol, or any candidate locations for a
1573 trampoline, are within range of the branch. For this reason, the
1574 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1575 relocation in modules at all, and it makes little sense to add
1578 The symptom is that the kernel fails with an "unsupported
1579 relocation" error when loading some modules.
1581 Until fixed tools are available, passing
1582 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1583 code which hits this problem, at the cost of a bit of extra runtime
1584 stack usage in some cases.
1586 The problem is described in more detail at:
1587 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1589 Only Thumb-2 kernels are affected.
1591 Unless you are sure your tools don't have this problem, say Y.
1593 config ARM_ASM_UNIFIED
1597 bool "Use the ARM EABI to compile the kernel"
1599 This option allows for the kernel to be compiled using the latest
1600 ARM ABI (aka EABI). This is only useful if you are using a user
1601 space environment that is also compiled with EABI.
1603 Since there are major incompatibilities between the legacy ABI and
1604 EABI, especially with regard to structure member alignment, this
1605 option also changes the kernel syscall calling convention to
1606 disambiguate both ABIs and allow for backward compatibility support
1607 (selected with CONFIG_OABI_COMPAT).
1609 To use this you need GCC version 4.0.0 or later.
1612 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1613 depends on AEABI && !THUMB2_KERNEL
1615 This option preserves the old syscall interface along with the
1616 new (ARM EABI) one. It also provides a compatibility layer to
1617 intercept syscalls that have structure arguments which layout
1618 in memory differs between the legacy ABI and the new ARM EABI
1619 (only for non "thumb" binaries). This option adds a tiny
1620 overhead to all syscalls and produces a slightly larger kernel.
1622 The seccomp filter system will not be available when this is
1623 selected, since there is no way yet to sensibly distinguish
1624 between calling conventions during filtering.
1626 If you know you'll be using only pure EABI user space then you
1627 can say N here. If this option is not selected and you attempt
1628 to execute a legacy ABI binary then the result will be
1629 UNPREDICTABLE (in fact it can be predicted that it won't work
1630 at all). If in doubt say N.
1632 config ARCH_HAS_HOLES_MEMORYMODEL
1635 config ARCH_SPARSEMEM_ENABLE
1638 config ARCH_SPARSEMEM_DEFAULT
1639 def_bool ARCH_SPARSEMEM_ENABLE
1641 config ARCH_SELECT_MEMORY_MODEL
1642 def_bool ARCH_SPARSEMEM_ENABLE
1644 config HAVE_ARCH_PFN_VALID
1645 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1647 config HAVE_GENERIC_RCU_GUP
1652 bool "High Memory Support"
1655 The address space of ARM processors is only 4 Gigabytes large
1656 and it has to accommodate user address space, kernel address
1657 space as well as some memory mapped IO. That means that, if you
1658 have a large amount of physical memory and/or IO, not all of the
1659 memory can be "permanently mapped" by the kernel. The physical
1660 memory that is not permanently mapped is called "high memory".
1662 Depending on the selected kernel/user memory split, minimum
1663 vmalloc space and actual amount of RAM, you may not need this
1664 option which should result in a slightly faster kernel.
1669 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1673 The VM uses one page of physical memory for each page table.
1674 For systems with a lot of processes, this can use a lot of
1675 precious low memory, eventually leading to low memory being
1676 consumed by page tables. Setting this option will allow
1677 user-space 2nd level page tables to reside in high memory.
1679 config CPU_SW_DOMAIN_PAN
1680 bool "Enable use of CPU domains to implement privileged no-access"
1681 depends on MMU && !ARM_LPAE
1684 Increase kernel security by ensuring that normal kernel accesses
1685 are unable to access userspace addresses. This can help prevent
1686 use-after-free bugs becoming an exploitable privilege escalation
1687 by ensuring that magic values (such as LIST_POISON) will always
1688 fault when dereferenced.
1690 CPUs with low-vector mappings use a best-efforts implementation.
1691 Their lower 1MB needs to remain accessible for the vectors, but
1692 the remainder of userspace will become appropriately inaccessible.
1694 config HW_PERF_EVENTS
1698 config SYS_SUPPORTS_HUGETLBFS
1702 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1706 config ARCH_WANT_GENERAL_HUGETLB
1709 config ARM_MODULE_PLTS
1710 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1713 Allocate PLTs when loading modules so that jumps and calls whose
1714 targets are too far away for their relative offsets to be encoded
1715 in the instructions themselves can be bounced via veneers in the
1716 module's PLT. This allows modules to be allocated in the generic
1717 vmalloc area after the dedicated module memory area has been
1718 exhausted. The modules will use slightly more memory, but after
1719 rounding up to page size, the actual memory footprint is usually
1722 Say y if you are getting out of memory errors while loading modules
1726 config FORCE_MAX_ZONEORDER
1727 int "Maximum zone order"
1728 default "12" if SOC_AM33XX
1729 default "9" if SA1111 || ARCH_EFM32
1732 The kernel memory allocator divides physically contiguous memory
1733 blocks into "zones", where each zone is a power of two number of
1734 pages. This option selects the largest power of two that the kernel
1735 keeps in the memory allocator. If you need to allocate very large
1736 blocks of physically contiguous memory, then you may need to
1737 increase this value.
1739 This config option is actually maximum order plus one. For example,
1740 a value of 11 means that the largest free memory block is 2^10 pages.
1742 config ALIGNMENT_TRAP
1744 depends on CPU_CP15_MMU
1745 default y if !ARCH_EBSA110
1746 select HAVE_PROC_CPU if PROC_FS
1748 ARM processors cannot fetch/store information which is not
1749 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1750 address divisible by 4. On 32-bit ARM processors, these non-aligned
1751 fetch/store instructions will be emulated in software if you say
1752 here, which has a severe performance impact. This is necessary for
1753 correct operation of some network protocols. With an IP-only
1754 configuration it is safe to say N, otherwise say Y.
1756 config UACCESS_WITH_MEMCPY
1757 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1759 default y if CPU_FEROCEON
1761 Implement faster copy_to_user and clear_user methods for CPU
1762 cores where a 8-word STM instruction give significantly higher
1763 memory write throughput than a sequence of individual 32bit stores.
1765 A possible side effect is a slight increase in scheduling latency
1766 between threads sharing the same address space if they invoke
1767 such copy operations with large buffers.
1769 However, if the CPU data cache is using a write-allocate mode,
1770 this option is unlikely to provide any performance gain.
1774 prompt "Enable seccomp to safely compute untrusted bytecode"
1776 This kernel feature is useful for number crunching applications
1777 that may need to compute untrusted bytecode during their
1778 execution. By using pipes or other transports made available to
1779 the process as file descriptors supporting the read/write
1780 syscalls, it's possible to isolate those applications in
1781 their own address space using seccomp. Once seccomp is
1782 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1783 and the task is only allowed to execute a few safe syscalls
1784 defined by each seccomp mode.
1797 bool "Xen guest support on ARM"
1798 depends on ARM && AEABI && OF
1799 depends on CPU_V7 && !CPU_V6
1800 depends on !GENERIC_ATOMIC64
1802 select ARCH_DMA_ADDR_T_64BIT
1806 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1808 config ARM_FLUSH_CONSOLE_ON_RESTART
1809 bool "Force flush the console on restart"
1811 If the console is locked while the system is rebooted, the messages
1812 in the temporary logbuffer would not have propogated to all the
1813 console drivers. This option forces the console lock to be
1814 released if it failed to be acquired, which will cause all the
1815 pending messages to be flushed.
1822 bool "Flattened Device Tree support"
1826 Include support for flattened device tree machine descriptions.
1829 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1832 This is the traditional way of passing data to the kernel at boot
1833 time. If you are solely relying on the flattened device tree (or
1834 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1835 to remove ATAGS support from your kernel binary. If unsure,
1838 config DEPRECATED_PARAM_STRUCT
1839 bool "Provide old way to pass kernel parameters"
1842 This was deprecated in 2001 and announced to live on for 5 years.
1843 Some old boot loaders still use this way.
1845 config BUILD_ARM_APPENDED_DTB_IMAGE
1846 bool "Build a concatenated zImage/dtb by default"
1849 Enabling this option will cause a concatenated zImage and list of
1850 DTBs to be built by default (instead of a standalone zImage.)
1851 The image will built in arch/arm/boot/zImage-dtb
1853 config BUILD_ARM_APPENDED_DTB_IMAGE_NAMES
1854 string "Default dtb names"
1855 depends on BUILD_ARM_APPENDED_DTB_IMAGE
1857 Space separated list of names of dtbs to append when
1858 building a concatenated zImage-dtb.
1860 # Compressed boot loader in ROM. Yes, we really want to ask about
1861 # TEXT and BSS so we preserve their values in the config files.
1862 config ZBOOT_ROM_TEXT
1863 hex "Compressed ROM boot loader base address"
1866 The physical address at which the ROM-able zImage is to be
1867 placed in the target. Platforms which normally make use of
1868 ROM-able zImage formats normally set this to a suitable
1869 value in their defconfig file.
1871 If ZBOOT_ROM is not enabled, this has no effect.
1873 config ZBOOT_ROM_BSS
1874 hex "Compressed ROM boot loader BSS address"
1877 The base address of an area of read/write memory in the target
1878 for the ROM-able zImage which must be available while the
1879 decompressor is running. It must be large enough to hold the
1880 entire decompressed kernel plus an additional 128 KiB.
1881 Platforms which normally make use of ROM-able zImage formats
1882 normally set this to a suitable value in their defconfig file.
1884 If ZBOOT_ROM is not enabled, this has no effect.
1887 bool "Compressed boot loader in ROM/flash"
1888 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1889 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1891 Say Y here if you intend to execute your compressed kernel image
1892 (zImage) directly from ROM or flash. If unsure, say N.
1894 config ARM_APPENDED_DTB
1895 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1898 With this option, the boot code will look for a device tree binary
1899 (DTB) appended to zImage
1900 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1902 This is meant as a backward compatibility convenience for those
1903 systems with a bootloader that can't be upgraded to accommodate
1904 the documented boot protocol using a device tree.
1906 Beware that there is very little in terms of protection against
1907 this option being confused by leftover garbage in memory that might
1908 look like a DTB header after a reboot if no actual DTB is appended
1909 to zImage. Do not leave this option active in a production kernel
1910 if you don't intend to always append a DTB. Proper passing of the
1911 location into r2 of a bootloader provided DTB is always preferable
1914 config ARM_ATAG_DTB_COMPAT
1915 bool "Supplement the appended DTB with traditional ATAG information"
1916 depends on ARM_APPENDED_DTB
1918 Some old bootloaders can't be updated to a DTB capable one, yet
1919 they provide ATAGs with memory configuration, the ramdisk address,
1920 the kernel cmdline string, etc. Such information is dynamically
1921 provided by the bootloader and can't always be stored in a static
1922 DTB. To allow a device tree enabled kernel to be used with such
1923 bootloaders, this option allows zImage to extract the information
1924 from the ATAG list and store it at run time into the appended DTB.
1927 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1928 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1930 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1931 bool "Use bootloader kernel arguments if available"
1933 Uses the command-line options passed by the boot loader instead of
1934 the device tree bootargs property. If the boot loader doesn't provide
1935 any, the device tree bootargs property will be used.
1937 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1938 bool "Extend with bootloader kernel arguments"
1940 The command-line arguments provided by the boot loader will be
1941 appended to the the device tree bootargs property.
1946 string "Default kernel command string"
1949 On some architectures (EBSA110 and CATS), there is currently no way
1950 for the boot loader to pass arguments to the kernel. For these
1951 architectures, you should supply some command-line options at build
1952 time by entering them here. As a minimum, you should specify the
1953 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1956 prompt "Kernel command line type" if CMDLINE != ""
1957 default CMDLINE_FROM_BOOTLOADER
1960 config CMDLINE_FROM_BOOTLOADER
1961 bool "Use bootloader kernel arguments if available"
1963 Uses the command-line options passed by the boot loader. If
1964 the boot loader doesn't provide any, the default kernel command
1965 string provided in CMDLINE will be used.
1967 config CMDLINE_EXTEND
1968 bool "Extend bootloader kernel arguments"
1970 The command-line arguments provided by the boot loader will be
1971 appended to the default kernel command string.
1973 config CMDLINE_FORCE
1974 bool "Always use the default kernel command string"
1976 Always use the default kernel command string, even if the boot
1977 loader passes other arguments to the kernel.
1978 This is useful if you cannot or don't want to change the
1979 command-line options your boot loader passes to the kernel.
1983 bool "Kernel Execute-In-Place from ROM"
1984 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1986 Execute-In-Place allows the kernel to run from non-volatile storage
1987 directly addressable by the CPU, such as NOR flash. This saves RAM
1988 space since the text section of the kernel is not loaded from flash
1989 to RAM. Read-write sections, such as the data section and stack,
1990 are still copied to RAM. The XIP kernel is not compressed since
1991 it has to run directly from flash, so it will take more space to
1992 store it. The flash address used to link the kernel object files,
1993 and for storing it, is configuration dependent. Therefore, if you
1994 say Y here, you must know the proper physical address where to
1995 store the kernel image depending on your own flash memory usage.
1997 Also note that the make target becomes "make xipImage" rather than
1998 "make zImage" or "make Image". The final kernel binary to put in
1999 ROM memory will be arch/arm/boot/xipImage.
2003 config XIP_PHYS_ADDR
2004 hex "XIP Kernel Physical Location"
2005 depends on XIP_KERNEL
2006 default "0x00080000"
2008 This is the physical address in your flash memory the kernel will
2009 be linked for and stored to. This address is dependent on your
2013 bool "Kexec system call (EXPERIMENTAL)"
2014 depends on (!SMP || PM_SLEEP_SMP)
2018 kexec is a system call that implements the ability to shutdown your
2019 current kernel, and to start another kernel. It is like a reboot
2020 but it is independent of the system firmware. And like a reboot
2021 you can start any kernel with it, not just Linux.
2023 It is an ongoing process to be certain the hardware in a machine
2024 is properly shutdown, so do not be surprised if this code does not
2025 initially work for you.
2028 bool "Export atags in procfs"
2029 depends on ATAGS && KEXEC
2032 Should the atags used to boot the kernel be exported in an "atags"
2033 file in procfs. Useful with kexec.
2036 bool "Build kdump crash kernel (EXPERIMENTAL)"
2038 Generate crash dump after being started by kexec. This should
2039 be normally only set in special crash dump kernels which are
2040 loaded in the main kernel with kexec-tools into a specially
2041 reserved region and then later executed after a crash by
2042 kdump/kexec. The crash dump kernel must be compiled to a
2043 memory address not used by the main kernel
2045 For more details see Documentation/kdump/kdump.txt
2047 config AUTO_ZRELADDR
2048 bool "Auto calculation of the decompressed kernel image address"
2050 ZRELADDR is the physical address where the decompressed kernel
2051 image will be placed. If AUTO_ZRELADDR is selected, the address
2052 will be determined at run-time by masking the current IP with
2053 0xf8000000. This assumes the zImage being placed in the first 128MB
2054 from start of memory.
2058 menu "CPU Power Management"
2060 source "drivers/cpufreq/Kconfig"
2062 source "drivers/cpuidle/Kconfig"
2066 menu "Floating point emulation"
2068 comment "At least one emulation must be selected"
2071 bool "NWFPE math emulation"
2072 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2074 Say Y to include the NWFPE floating point emulator in the kernel.
2075 This is necessary to run most binaries. Linux does not currently
2076 support floating point hardware so you need to say Y here even if
2077 your machine has an FPA or floating point co-processor podule.
2079 You may say N here if you are going to load the Acorn FPEmulator
2080 early in the bootup.
2083 bool "Support extended precision"
2084 depends on FPE_NWFPE
2086 Say Y to include 80-bit support in the kernel floating-point
2087 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2088 Note that gcc does not generate 80-bit operations by default,
2089 so in most cases this option only enlarges the size of the
2090 floating point emulator without any good reason.
2092 You almost surely want to say N here.
2095 bool "FastFPE math emulation (EXPERIMENTAL)"
2096 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2098 Say Y here to include the FAST floating point emulator in the kernel.
2099 This is an experimental much faster emulator which now also has full
2100 precision for the mantissa. It does not support any exceptions.
2101 It is very simple, and approximately 3-6 times faster than NWFPE.
2103 It should be sufficient for most programs. It may be not suitable
2104 for scientific calculations, but you have to check this for yourself.
2105 If you do not feel you need a faster FP emulation you should better
2109 bool "VFP-format floating point maths"
2110 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2112 Say Y to include VFP support code in the kernel. This is needed
2113 if your hardware includes a VFP unit.
2115 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2116 release notes and additional status information.
2118 Say N if your target does not have VFP hardware.
2126 bool "Advanced SIMD (NEON) Extension support"
2127 depends on VFPv3 && CPU_V7
2129 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2132 config KERNEL_MODE_NEON
2133 bool "Support for NEON in kernel mode"
2134 depends on NEON && AEABI
2136 Say Y to include support for NEON in kernel mode.
2140 menu "Userspace binary formats"
2142 source "fs/Kconfig.binfmt"
2146 menu "Power management options"
2148 source "kernel/power/Kconfig"
2150 config ARCH_SUSPEND_POSSIBLE
2151 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2152 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2155 config ARM_CPU_SUSPEND
2158 config ARCH_HIBERNATION_POSSIBLE
2161 default y if ARCH_SUSPEND_POSSIBLE
2165 source "net/Kconfig"
2167 source "drivers/Kconfig"
2169 source "drivers/firmware/Kconfig"
2173 source "arch/arm/Kconfig.debug"
2175 source "security/Kconfig"
2177 source "crypto/Kconfig"
2179 source "arch/arm/crypto/Kconfig"
2182 source "lib/Kconfig"
2184 source "arch/arm/kvm/Kconfig"