4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
28 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
30 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
31 select HAVE_ARCH_TRACEHOOK
33 select HAVE_CC_STACKPROTECTOR
34 select HAVE_CONTEXT_TRACKING
35 select HAVE_C_RECORDMCOUNT
36 select HAVE_DEBUG_KMEMLEAK
37 select HAVE_DMA_API_DEBUG
39 select HAVE_DMA_CONTIGUOUS if MMU
40 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
41 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
42 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
43 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
44 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
45 select HAVE_GENERIC_DMA_COHERENT
46 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
47 select HAVE_IDE if PCI || ISA || PCMCIA
48 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_KERNEL_GZIP
50 select HAVE_KERNEL_LZ4
51 select HAVE_KERNEL_LZMA
52 select HAVE_KERNEL_LZO
54 select HAVE_KPROBES if !XIP_KERNEL
55 select HAVE_KRETPROBES if (HAVE_KPROBES)
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
59 select HAVE_PERF_EVENTS
61 select HAVE_PERF_USER_STACK_DUMP
62 select HAVE_REGS_AND_STACK_ACCESS_API
63 select HAVE_SYSCALL_TRACEPOINTS
65 select HAVE_VIRT_CPU_ACCOUNTING_GEN
66 select IRQ_FORCED_THREADING
68 select MODULES_USE_ELF_REL
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
88 config NEED_SG_DMA_LENGTH
91 config ARM_DMA_USE_IOMMU
93 select ARM_HAS_SG_CHAIN
94 select NEED_SG_DMA_LENGTH
98 config ARM_DMA_IOMMU_ALIGNMENT
99 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
103 DMA mapping framework by default aligns all buffers to the smallest
104 PAGE_SIZE order which is greater than or equal to the requested buffer
105 size. This works well for buffers up to a few hundreds kilobytes, but
106 for larger buffers it just a waste of address space. Drivers which has
107 relatively small addressing window (like 64Mib) might run out of
108 virtual space with just a few allocations.
110 With this parameter you can specify the maximum PAGE_SIZE order for
111 DMA IOMMU buffers. Larger buffers will be aligned only to this
112 specified order. The order is expressed as a power of two multiplied
117 config MIGHT_HAVE_PCI
120 config SYS_SUPPORTS_APM_EMULATION
125 select GENERIC_ALLOCATOR
136 The Extended Industry Standard Architecture (EISA) bus was
137 developed as an open alternative to the IBM MicroChannel bus.
139 The EISA bus provided some of the features of the IBM MicroChannel
140 bus while maintaining backward compatibility with cards made for
141 the older ISA bus. The EISA bus saw limited use between 1988 and
142 1995 when it was made obsolete by the PCI bus.
144 Say Y here if you are building a kernel for an EISA-based machine.
151 config STACKTRACE_SUPPORT
155 config HAVE_LATENCYTOP_SUPPORT
160 config LOCKDEP_SUPPORT
164 config TRACE_IRQFLAGS_SUPPORT
168 config RWSEM_XCHGADD_ALGORITHM
172 config ARCH_HAS_ILOG2_U32
175 config ARCH_HAS_ILOG2_U64
178 config ARCH_HAS_BANDGAP
181 config GENERIC_HWEIGHT
185 config GENERIC_CALIBRATE_DELAY
189 config ARCH_MAY_HAVE_PC_FDC
195 config NEED_DMA_MAP_STATE
198 config ARCH_SUPPORTS_UPROBES
201 config ARCH_HAS_DMA_SET_COHERENT_MASK
204 config GENERIC_ISA_DMA
210 config NEED_RET_TO_USER
218 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
219 default DRAM_BASE if REMAP_VECTORS_TO_RAM
222 The base address of exception vectors. This must be two pages
225 config ARM_PATCH_PHYS_VIRT
226 bool "Patch physical to virtual translations at runtime" if EMBEDDED
228 depends on !XIP_KERNEL && MMU
229 depends on !ARCH_REALVIEW || !SPARSEMEM
231 Patch phys-to-virt and virt-to-phys translation functions at
232 boot and module load time according to the position of the
233 kernel in system memory.
235 This can only be used with non-XIP MMU kernels where the base
236 of physical memory is at a 16MB boundary.
238 Only disable this option if you know that you do not require
239 this feature (eg, building a kernel for a single machine) and
240 you need to shrink the kernel to the minimal size.
242 config NEED_MACH_GPIO_H
245 Select this when mach/gpio.h is required to provide special
246 definitions for this platform. The need for mach/gpio.h should
247 be avoided when possible.
249 config NEED_MACH_IO_H
252 Select this when mach/io.h is required to provide special
253 definitions for this platform. The need for mach/io.h should
254 be avoided when possible.
256 config NEED_MACH_MEMORY_H
259 Select this when mach/memory.h is required to provide special
260 definitions for this platform. The need for mach/memory.h should
261 be avoided when possible.
264 hex "Physical address of main memory" if MMU
265 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
266 default DRAM_BASE if !MMU
268 Please provide the physical address corresponding to the
269 location of main memory in your system.
275 source "init/Kconfig"
277 source "kernel/Kconfig.freezer"
282 bool "MMU-based Paged Memory Management Support"
285 Select if you want MMU-based virtualised addressing space
286 support by paged memory management. If unsure, say 'Y'.
289 # The "ARM system type" choice list is ordered alphabetically by option
290 # text. Please add new entries in the option alphabetic order.
293 prompt "ARM system type"
294 default ARCH_VERSATILE if !MMU
295 default ARCH_MULTIPLATFORM if MMU
297 config ARCH_MULTIPLATFORM
298 bool "Allow multiple platforms to be selected"
300 select ARCH_WANT_OPTIONAL_GPIOLIB
301 select ARM_HAS_SG_CHAIN
302 select ARM_PATCH_PHYS_VIRT
306 select GENERIC_CLOCKEVENTS
307 select MIGHT_HAVE_PCI
308 select MULTI_IRQ_HANDLER
312 config ARCH_INTEGRATOR
313 bool "ARM Ltd. Integrator family"
315 select ARM_PATCH_PHYS_VIRT
318 select COMMON_CLK_VERSATILE
319 select GENERIC_CLOCKEVENTS
322 select MULTI_IRQ_HANDLER
323 select NEED_MACH_MEMORY_H
324 select PLAT_VERSATILE
327 select VERSATILE_FPGA_IRQ
329 Support for ARM's Integrator platform.
332 bool "ARM Ltd. RealView family"
333 select ARCH_WANT_OPTIONAL_GPIOLIB
335 select ARM_TIMER_SP804
337 select COMMON_CLK_VERSATILE
338 select GENERIC_CLOCKEVENTS
339 select GPIO_PL061 if GPIOLIB
341 select NEED_MACH_MEMORY_H
342 select PLAT_VERSATILE
343 select PLAT_VERSATILE_CLCD
345 This enables support for ARM Ltd RealView boards.
347 config ARCH_VERSATILE
348 bool "ARM Ltd. Versatile family"
349 select ARCH_WANT_OPTIONAL_GPIOLIB
351 select ARM_TIMER_SP804
354 select GENERIC_CLOCKEVENTS
355 select HAVE_MACH_CLKDEV
357 select PLAT_VERSATILE
358 select PLAT_VERSATILE_CLCD
359 select PLAT_VERSATILE_CLOCK
360 select VERSATILE_FPGA_IRQ
362 This enables support for ARM Ltd Versatile board.
366 select ARCH_REQUIRE_GPIOLIB
369 select NEED_MACH_IO_H if PCCARD
371 select PINCTRL_AT91 if USE_OF
373 This enables support for systems based on Atmel
374 AT91RM9200 and AT91SAM9* processors.
377 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
378 select ARCH_REQUIRE_GPIOLIB
383 select GENERIC_CLOCKEVENTS
386 Support for Cirrus Logic 711x/721x/731x based boards.
389 bool "Cortina Systems Gemini"
390 select ARCH_REQUIRE_GPIOLIB
393 select GENERIC_CLOCKEVENTS
395 Support for the Cortina Systems Gemini family SoCs
399 select ARCH_USES_GETTIMEOFFSET
402 select NEED_MACH_IO_H
403 select NEED_MACH_MEMORY_H
406 This is an evaluation board for the StrongARM processor available
407 from Digital. It has limited hardware on-board, including an
408 Ethernet interface, two PCMCIA sockets, two serial ports and a
412 bool "Energy Micro efm32"
414 select ARCH_REQUIRE_GPIOLIB
420 select GENERIC_CLOCKEVENTS
426 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
431 select ARCH_HAS_HOLES_MEMORYMODEL
432 select ARCH_REQUIRE_GPIOLIB
433 select ARCH_USES_GETTIMEOFFSET
438 select NEED_MACH_MEMORY_H
440 This enables support for the Cirrus EP93xx series of CPUs.
442 config ARCH_FOOTBRIDGE
446 select GENERIC_CLOCKEVENTS
448 select NEED_MACH_IO_H if !MMU
449 select NEED_MACH_MEMORY_H
451 Support for systems based on the DC21285 companion chip
452 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
455 bool "Hilscher NetX based"
459 select GENERIC_CLOCKEVENTS
461 This enables support for systems based on the Hilscher NetX Soc
467 select NEED_MACH_MEMORY_H
468 select NEED_RET_TO_USER
474 Support for Intel's IOP13XX (XScale) family of processors.
479 select ARCH_REQUIRE_GPIOLIB
482 select NEED_RET_TO_USER
486 Support for Intel's 80219 and IOP32X (XScale) family of
492 select ARCH_REQUIRE_GPIOLIB
495 select NEED_RET_TO_USER
499 Support for Intel's IOP33X (XScale) family of processors.
504 select ARCH_HAS_DMA_SET_COHERENT_MASK
505 select ARCH_REQUIRE_GPIOLIB
506 select ARCH_SUPPORTS_BIG_ENDIAN
509 select DMABOUNCE if PCI
510 select GENERIC_CLOCKEVENTS
511 select MIGHT_HAVE_PCI
512 select NEED_MACH_IO_H
513 select USB_EHCI_BIG_ENDIAN_DESC
514 select USB_EHCI_BIG_ENDIAN_MMIO
516 Support for Intel's IXP4XX (XScale) family of processors.
520 select ARCH_REQUIRE_GPIOLIB
522 select GENERIC_CLOCKEVENTS
523 select MIGHT_HAVE_PCI
527 select PLAT_ORION_LEGACY
529 Support for the Marvell Dove SoC 88AP510
532 bool "Marvell Kirkwood"
533 select ARCH_REQUIRE_GPIOLIB
535 select GENERIC_CLOCKEVENTS
540 select PINCTRL_KIRKWOOD
541 select PLAT_ORION_LEGACY
543 Support for the following Marvell Kirkwood series SoCs:
544 88F6180, 88F6192 and 88F6281.
547 bool "Marvell MV78xx0"
548 select ARCH_REQUIRE_GPIOLIB
550 select GENERIC_CLOCKEVENTS
553 select PLAT_ORION_LEGACY
555 Support for the following Marvell MV78xx0 series SoCs:
561 select ARCH_REQUIRE_GPIOLIB
563 select GENERIC_CLOCKEVENTS
566 select PLAT_ORION_LEGACY
568 Support for the following Marvell Orion 5x series SoCs:
569 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
570 Orion-2 (5281), Orion-1-90 (6183).
573 bool "Marvell PXA168/910/MMP2"
575 select ARCH_REQUIRE_GPIOLIB
577 select GENERIC_ALLOCATOR
578 select GENERIC_CLOCKEVENTS
581 select MULTI_IRQ_HANDLER
586 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
589 bool "Micrel/Kendin KS8695"
590 select ARCH_REQUIRE_GPIOLIB
593 select GENERIC_CLOCKEVENTS
594 select NEED_MACH_MEMORY_H
596 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
597 System-on-Chip devices.
600 bool "Nuvoton W90X900 CPU"
601 select ARCH_REQUIRE_GPIOLIB
605 select GENERIC_CLOCKEVENTS
607 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
608 At present, the w90x900 has been renamed nuc900, regarding
609 the ARM series product line, you can login the following
610 link address to know more.
612 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
613 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
617 select ARCH_REQUIRE_GPIOLIB
622 select GENERIC_CLOCKEVENTS
626 Support for the NXP LPC32XX family of processors
629 bool "PXA2xx/PXA3xx-based"
632 select ARCH_REQUIRE_GPIOLIB
633 select ARM_CPU_SUSPEND if PM
637 select GENERIC_CLOCKEVENTS
640 select MULTI_IRQ_HANDLER
644 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
647 bool "Qualcomm MSM (non-multiplatform)"
648 select ARCH_REQUIRE_GPIOLIB
650 select GENERIC_CLOCKEVENTS
652 Support for Qualcomm MSM/QSD based systems. This runs on the
653 apps processor of the MSM/QSD and depends on a shared memory
654 interface to the modem processor which runs the baseband
655 stack and controls some vital subsystems
656 (clock and power control, etc).
658 config ARCH_SHMOBILE_LEGACY
659 bool "Renesas ARM SoCs (non-multiplatform)"
661 select ARM_PATCH_PHYS_VIRT
663 select GENERIC_CLOCKEVENTS
664 select HAVE_ARM_SCU if SMP
665 select HAVE_ARM_TWD if SMP
666 select HAVE_MACH_CLKDEV
668 select MIGHT_HAVE_CACHE_L2X0
669 select MULTI_IRQ_HANDLER
672 select PM_GENERIC_DOMAINS if PM
675 Support for Renesas ARM SoC platforms using a non-multiplatform
676 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
682 select ARCH_MAY_HAVE_PC_FDC
683 select ARCH_SPARSEMEM_ENABLE
684 select ARCH_USES_GETTIMEOFFSET
688 select HAVE_PATA_PLATFORM
690 select NEED_MACH_IO_H
691 select NEED_MACH_MEMORY_H
695 On the Acorn Risc-PC, Linux can support the internal IDE disk and
696 CD-ROM interface, serial and parallel port, and the floppy drive.
701 select ARCH_REQUIRE_GPIOLIB
702 select ARCH_SPARSEMEM_ENABLE
707 select GENERIC_CLOCKEVENTS
710 select NEED_MACH_MEMORY_H
713 Support for StrongARM 11x0 based boards.
716 bool "Samsung S3C24XX SoCs"
717 select ARCH_REQUIRE_GPIOLIB
720 select CLKSRC_SAMSUNG_PWM
721 select GENERIC_CLOCKEVENTS
723 select HAVE_S3C2410_I2C if I2C
724 select HAVE_S3C2410_WATCHDOG if WATCHDOG
725 select HAVE_S3C_RTC if RTC_CLASS
726 select MULTI_IRQ_HANDLER
727 select NEED_MACH_IO_H
730 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
731 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
732 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
733 Samsung SMDK2410 development board (and derivatives).
736 bool "Samsung S3C64XX"
737 select ARCH_REQUIRE_GPIOLIB
742 select CLKSRC_SAMSUNG_PWM
743 select COMMON_CLK_SAMSUNG
745 select GENERIC_CLOCKEVENTS
747 select HAVE_S3C2410_I2C if I2C
748 select HAVE_S3C2410_WATCHDOG if WATCHDOG
752 select PM_GENERIC_DOMAINS if PM
754 select S3C_GPIO_TRACK
756 select SAMSUNG_WAKEMASK
757 select SAMSUNG_WDT_RESET
759 Samsung S3C64XX series based systems
762 bool "Samsung S5P6440 S5P6450"
765 select CLKSRC_SAMSUNG_PWM
767 select GENERIC_CLOCKEVENTS
769 select HAVE_S3C2410_I2C if I2C
770 select HAVE_S3C2410_WATCHDOG if WATCHDOG
771 select HAVE_S3C_RTC if RTC_CLASS
773 select SAMSUNG_WDT_RESET
775 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
779 bool "Samsung S5PC100"
780 select ARCH_REQUIRE_GPIOLIB
783 select CLKSRC_SAMSUNG_PWM
785 select GENERIC_CLOCKEVENTS
787 select HAVE_S3C2410_I2C if I2C
788 select HAVE_S3C2410_WATCHDOG if WATCHDOG
789 select HAVE_S3C_RTC if RTC_CLASS
791 select SAMSUNG_WDT_RESET
793 Samsung S5PC100 series based systems
796 bool "Samsung S5PV210/S5PC110"
797 select ARCH_HAS_HOLES_MEMORYMODEL
798 select ARCH_SPARSEMEM_ENABLE
801 select CLKSRC_SAMSUNG_PWM
803 select GENERIC_CLOCKEVENTS
805 select HAVE_S3C2410_I2C if I2C
806 select HAVE_S3C2410_WATCHDOG if WATCHDOG
807 select HAVE_S3C_RTC if RTC_CLASS
808 select NEED_MACH_MEMORY_H
811 Samsung S5PV210/S5PC110 series based systems
815 select ARCH_HAS_HOLES_MEMORYMODEL
816 select ARCH_REQUIRE_GPIOLIB
818 select GENERIC_ALLOCATOR
819 select GENERIC_CLOCKEVENTS
820 select GENERIC_IRQ_CHIP
826 Support for TI's DaVinci platform.
831 select ARCH_HAS_HOLES_MEMORYMODEL
833 select ARCH_REQUIRE_GPIOLIB
836 select GENERIC_CLOCKEVENTS
837 select GENERIC_IRQ_CHIP
840 select NEED_MACH_IO_H if PCCARD
841 select NEED_MACH_MEMORY_H
843 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
847 menu "Multiple platform selection"
848 depends on ARCH_MULTIPLATFORM
850 comment "CPU Core family selection"
853 bool "ARMv4 based platforms (FA526)"
854 depends on !ARCH_MULTI_V6_V7
855 select ARCH_MULTI_V4_V5
858 config ARCH_MULTI_V4T
859 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
860 depends on !ARCH_MULTI_V6_V7
861 select ARCH_MULTI_V4_V5
862 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
863 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
864 CPU_ARM925T || CPU_ARM940T)
867 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
868 depends on !ARCH_MULTI_V6_V7
869 select ARCH_MULTI_V4_V5
870 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
871 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
872 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
874 config ARCH_MULTI_V4_V5
878 bool "ARMv6 based platforms (ARM11)"
879 select ARCH_MULTI_V6_V7
883 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
885 select ARCH_MULTI_V6_V7
889 config ARCH_MULTI_V6_V7
891 select MIGHT_HAVE_CACHE_L2X0
893 config ARCH_MULTI_CPU_AUTO
894 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
900 bool "Dummy Virtual Machine" if ARCH_MULTI_V7
904 select HAVE_ARM_ARCH_TIMER
907 # This is sorted alphabetically by mach-* pathname. However, plat-*
908 # Kconfigs may be included either alphabetically (according to the
909 # plat- suffix) or along side the corresponding mach-* source.
911 source "arch/arm/mach-mvebu/Kconfig"
913 source "arch/arm/mach-at91/Kconfig"
915 source "arch/arm/mach-axxia/Kconfig"
917 source "arch/arm/mach-bcm/Kconfig"
919 source "arch/arm/mach-berlin/Kconfig"
921 source "arch/arm/mach-clps711x/Kconfig"
923 source "arch/arm/mach-cns3xxx/Kconfig"
925 source "arch/arm/mach-davinci/Kconfig"
927 source "arch/arm/mach-dove/Kconfig"
929 source "arch/arm/mach-ep93xx/Kconfig"
931 source "arch/arm/mach-footbridge/Kconfig"
933 source "arch/arm/mach-gemini/Kconfig"
935 source "arch/arm/mach-highbank/Kconfig"
937 source "arch/arm/mach-hisi/Kconfig"
939 source "arch/arm/mach-integrator/Kconfig"
941 source "arch/arm/mach-iop32x/Kconfig"
943 source "arch/arm/mach-iop33x/Kconfig"
945 source "arch/arm/mach-iop13xx/Kconfig"
947 source "arch/arm/mach-ixp4xx/Kconfig"
949 source "arch/arm/mach-keystone/Kconfig"
951 source "arch/arm/mach-kirkwood/Kconfig"
953 source "arch/arm/mach-ks8695/Kconfig"
955 source "arch/arm/mach-msm/Kconfig"
957 source "arch/arm/mach-moxart/Kconfig"
959 source "arch/arm/mach-mv78xx0/Kconfig"
961 source "arch/arm/mach-imx/Kconfig"
963 source "arch/arm/mach-mxs/Kconfig"
965 source "arch/arm/mach-netx/Kconfig"
967 source "arch/arm/mach-nomadik/Kconfig"
969 source "arch/arm/mach-nspire/Kconfig"
971 source "arch/arm/plat-omap/Kconfig"
973 source "arch/arm/mach-omap1/Kconfig"
975 source "arch/arm/mach-omap2/Kconfig"
977 source "arch/arm/mach-orion5x/Kconfig"
979 source "arch/arm/mach-picoxcell/Kconfig"
981 source "arch/arm/mach-pxa/Kconfig"
982 source "arch/arm/plat-pxa/Kconfig"
984 source "arch/arm/mach-mmp/Kconfig"
986 source "arch/arm/mach-qcom/Kconfig"
988 source "arch/arm/mach-realview/Kconfig"
990 source "arch/arm/mach-rockchip/Kconfig"
992 source "arch/arm/mach-sa1100/Kconfig"
994 source "arch/arm/mach-socfpga/Kconfig"
996 source "arch/arm/mach-spear/Kconfig"
998 source "arch/arm/mach-sti/Kconfig"
1000 source "arch/arm/mach-s3c24xx/Kconfig"
1002 source "arch/arm/mach-s3c64xx/Kconfig"
1004 source "arch/arm/mach-s5p64x0/Kconfig"
1006 source "arch/arm/mach-s5pc100/Kconfig"
1008 source "arch/arm/mach-s5pv210/Kconfig"
1010 source "arch/arm/mach-exynos/Kconfig"
1011 source "arch/arm/plat-samsung/Kconfig"
1013 source "arch/arm/mach-shmobile/Kconfig"
1015 source "arch/arm/mach-sunxi/Kconfig"
1017 source "arch/arm/mach-prima2/Kconfig"
1019 source "arch/arm/mach-tegra/Kconfig"
1021 source "arch/arm/mach-u300/Kconfig"
1023 source "arch/arm/mach-ux500/Kconfig"
1025 source "arch/arm/mach-versatile/Kconfig"
1027 source "arch/arm/mach-vexpress/Kconfig"
1028 source "arch/arm/plat-versatile/Kconfig"
1030 source "arch/arm/mach-vt8500/Kconfig"
1032 source "arch/arm/mach-w90x900/Kconfig"
1034 source "arch/arm/mach-zynq/Kconfig"
1036 # Definitions to make life easier
1042 select GENERIC_CLOCKEVENTS
1048 select GENERIC_IRQ_CHIP
1051 config PLAT_ORION_LEGACY
1058 config PLAT_VERSATILE
1061 config ARM_TIMER_SP804
1064 select CLKSRC_OF if OF
1066 source "arch/arm/firmware/Kconfig"
1068 source arch/arm/mm/Kconfig
1071 bool "Enable iWMMXt support"
1072 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1073 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1075 Enable support for iWMMXt context switching at run time if
1076 running on a CPU that supports it.
1078 config MULTI_IRQ_HANDLER
1081 Allow each machine to specify it's own IRQ handler at run time.
1084 source "arch/arm/Kconfig-nommu"
1087 config PJ4B_ERRATA_4742
1088 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1089 depends on CPU_PJ4B && MACH_ARMADA_370
1092 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1093 Event (WFE) IDLE states, a specific timing sensitivity exists between
1094 the retiring WFI/WFE instructions and the newly issued subsequent
1095 instructions. This sensitivity can result in a CPU hang scenario.
1097 The software must insert either a Data Synchronization Barrier (DSB)
1098 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1101 config ARM_ERRATA_326103
1102 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1105 Executing a SWP instruction to read-only memory does not set bit 11
1106 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1107 treat the access as a read, preventing a COW from occurring and
1108 causing the faulting task to livelock.
1110 config ARM_ERRATA_411920
1111 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1112 depends on CPU_V6 || CPU_V6K
1114 Invalidation of the Instruction Cache operation can
1115 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1116 It does not affect the MPCore. This option enables the ARM Ltd.
1117 recommended workaround.
1119 config ARM_ERRATA_430973
1120 bool "ARM errata: Stale prediction on replaced interworking branch"
1123 This option enables the workaround for the 430973 Cortex-A8
1124 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1125 interworking branch is replaced with another code sequence at the
1126 same virtual address, whether due to self-modifying code or virtual
1127 to physical address re-mapping, Cortex-A8 does not recover from the
1128 stale interworking branch prediction. This results in Cortex-A8
1129 executing the new code sequence in the incorrect ARM or Thumb state.
1130 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1131 and also flushes the branch target cache at every context switch.
1132 Note that setting specific bits in the ACTLR register may not be
1133 available in non-secure mode.
1135 config ARM_ERRATA_458693
1136 bool "ARM errata: Processor deadlock when a false hazard is created"
1138 depends on !ARCH_MULTIPLATFORM
1140 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1141 erratum. For very specific sequences of memory operations, it is
1142 possible for a hazard condition intended for a cache line to instead
1143 be incorrectly associated with a different cache line. This false
1144 hazard might then cause a processor deadlock. The workaround enables
1145 the L1 caching of the NEON accesses and disables the PLD instruction
1146 in the ACTLR register. Note that setting specific bits in the ACTLR
1147 register may not be available in non-secure mode.
1149 config ARM_ERRATA_460075
1150 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1152 depends on !ARCH_MULTIPLATFORM
1154 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1155 erratum. Any asynchronous access to the L2 cache may encounter a
1156 situation in which recent store transactions to the L2 cache are lost
1157 and overwritten with stale memory contents from external memory. The
1158 workaround disables the write-allocate mode for the L2 cache via the
1159 ACTLR register. Note that setting specific bits in the ACTLR register
1160 may not be available in non-secure mode.
1162 config ARM_ERRATA_742230
1163 bool "ARM errata: DMB operation may be faulty"
1164 depends on CPU_V7 && SMP
1165 depends on !ARCH_MULTIPLATFORM
1167 This option enables the workaround for the 742230 Cortex-A9
1168 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1169 between two write operations may not ensure the correct visibility
1170 ordering of the two writes. This workaround sets a specific bit in
1171 the diagnostic register of the Cortex-A9 which causes the DMB
1172 instruction to behave as a DSB, ensuring the correct behaviour of
1175 config ARM_ERRATA_742231
1176 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1177 depends on CPU_V7 && SMP
1178 depends on !ARCH_MULTIPLATFORM
1180 This option enables the workaround for the 742231 Cortex-A9
1181 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1182 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1183 accessing some data located in the same cache line, may get corrupted
1184 data due to bad handling of the address hazard when the line gets
1185 replaced from one of the CPUs at the same time as another CPU is
1186 accessing it. This workaround sets specific bits in the diagnostic
1187 register of the Cortex-A9 which reduces the linefill issuing
1188 capabilities of the processor.
1190 config ARM_ERRATA_643719
1191 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1192 depends on CPU_V7 && SMP
1194 This option enables the workaround for the 643719 Cortex-A9 (prior to
1195 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1196 register returns zero when it should return one. The workaround
1197 corrects this value, ensuring cache maintenance operations which use
1198 it behave as intended and avoiding data corruption.
1200 config ARM_ERRATA_720789
1201 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1204 This option enables the workaround for the 720789 Cortex-A9 (prior to
1205 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1206 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1207 As a consequence of this erratum, some TLB entries which should be
1208 invalidated are not, resulting in an incoherency in the system page
1209 tables. The workaround changes the TLB flushing routines to invalidate
1210 entries regardless of the ASID.
1212 config ARM_ERRATA_743622
1213 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1215 depends on !ARCH_MULTIPLATFORM
1217 This option enables the workaround for the 743622 Cortex-A9
1218 (r2p*) erratum. Under very rare conditions, a faulty
1219 optimisation in the Cortex-A9 Store Buffer may lead to data
1220 corruption. This workaround sets a specific bit in the diagnostic
1221 register of the Cortex-A9 which disables the Store Buffer
1222 optimisation, preventing the defect from occurring. This has no
1223 visible impact on the overall performance or power consumption of the
1226 config ARM_ERRATA_751472
1227 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1229 depends on !ARCH_MULTIPLATFORM
1231 This option enables the workaround for the 751472 Cortex-A9 (prior
1232 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1233 completion of a following broadcasted operation if the second
1234 operation is received by a CPU before the ICIALLUIS has completed,
1235 potentially leading to corrupted entries in the cache or TLB.
1237 config ARM_ERRATA_754322
1238 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1241 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1242 r3p*) erratum. A speculative memory access may cause a page table walk
1243 which starts prior to an ASID switch but completes afterwards. This
1244 can populate the micro-TLB with a stale entry which may be hit with
1245 the new ASID. This workaround places two dsb instructions in the mm
1246 switching code so that no page table walks can cross the ASID switch.
1248 config ARM_ERRATA_754327
1249 bool "ARM errata: no automatic Store Buffer drain"
1250 depends on CPU_V7 && SMP
1252 This option enables the workaround for the 754327 Cortex-A9 (prior to
1253 r2p0) erratum. The Store Buffer does not have any automatic draining
1254 mechanism and therefore a livelock may occur if an external agent
1255 continuously polls a memory location waiting to observe an update.
1256 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1257 written polling loops from denying visibility of updates to memory.
1259 config ARM_ERRATA_364296
1260 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1263 This options enables the workaround for the 364296 ARM1136
1264 r0p2 erratum (possible cache data corruption with
1265 hit-under-miss enabled). It sets the undocumented bit 31 in
1266 the auxiliary control register and the FI bit in the control
1267 register, thus disabling hit-under-miss without putting the
1268 processor into full low interrupt latency mode. ARM11MPCore
1271 config ARM_ERRATA_764369
1272 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1273 depends on CPU_V7 && SMP
1275 This option enables the workaround for erratum 764369
1276 affecting Cortex-A9 MPCore with two or more processors (all
1277 current revisions). Under certain timing circumstances, a data
1278 cache line maintenance operation by MVA targeting an Inner
1279 Shareable memory region may fail to proceed up to either the
1280 Point of Coherency or to the Point of Unification of the
1281 system. This workaround adds a DSB instruction before the
1282 relevant cache maintenance functions and sets a specific bit
1283 in the diagnostic control register of the SCU.
1285 config ARM_ERRATA_775420
1286 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1289 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1290 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1291 operation aborts with MMU exception, it might cause the processor
1292 to deadlock. This workaround puts DSB before executing ISB if
1293 an abort may occur on cache maintenance.
1295 config ARM_ERRATA_798181
1296 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1297 depends on CPU_V7 && SMP
1299 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1300 adequately shooting down all use of the old entries. This
1301 option enables the Linux kernel workaround for this erratum
1302 which sends an IPI to the CPUs that are running the same ASID
1303 as the one being invalidated.
1305 config ARM_ERRATA_773022
1306 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1309 This option enables the workaround for the 773022 Cortex-A15
1310 (up to r0p4) erratum. In certain rare sequences of code, the
1311 loop buffer may deliver incorrect instructions. This
1312 workaround disables the loop buffer to avoid the erratum.
1316 source "arch/arm/common/Kconfig"
1326 Find out whether you have ISA slots on your motherboard. ISA is the
1327 name of a bus system, i.e. the way the CPU talks to the other stuff
1328 inside your box. Other bus systems are PCI, EISA, MicroChannel
1329 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1330 newer boards don't support it. If you have ISA, say Y, otherwise N.
1332 # Select ISA DMA controller support
1337 # Select ISA DMA interface
1342 bool "PCI support" if MIGHT_HAVE_PCI
1344 Find out whether you have a PCI motherboard. PCI is the name of a
1345 bus system, i.e. the way the CPU talks to the other stuff inside
1346 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1347 VESA. If you have PCI, say Y, otherwise N.
1353 config PCI_NANOENGINE
1354 bool "BSE nanoEngine PCI support"
1355 depends on SA1100_NANOENGINE
1357 Enable PCI on the BSE nanoEngine board.
1362 config PCI_HOST_ITE8152
1364 depends on PCI && MACH_ARMCORE
1368 source "drivers/pci/Kconfig"
1369 source "drivers/pci/pcie/Kconfig"
1371 source "drivers/pcmcia/Kconfig"
1375 menu "Kernel Features"
1380 This option should be selected by machines which have an SMP-
1383 The only effect of this option is to make the SMP-related
1384 options available to the user for configuration.
1387 bool "Symmetric Multi-Processing"
1388 depends on CPU_V6K || CPU_V7
1389 depends on GENERIC_CLOCKEVENTS
1391 depends on MMU || ARM_MPU
1393 This enables support for systems with more than one CPU. If you have
1394 a system with only one CPU, say N. If you have a system with more
1395 than one CPU, say Y.
1397 If you say N here, the kernel will run on uni- and multiprocessor
1398 machines, but will use only one CPU of a multiprocessor machine. If
1399 you say Y here, the kernel will run on many, but not all,
1400 uniprocessor machines. On a uniprocessor machine, the kernel
1401 will run faster if you say N here.
1403 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1404 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1405 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1407 If you don't know what to do here, say N.
1410 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1411 depends on SMP && !XIP_KERNEL && MMU
1414 SMP kernels contain instructions which fail on non-SMP processors.
1415 Enabling this option allows the kernel to modify itself to make
1416 these instructions safe. Disabling it allows about 1K of space
1419 If you don't know what to do here, say Y.
1421 config ARM_CPU_TOPOLOGY
1422 bool "Support cpu topology definition"
1423 depends on SMP && CPU_V7
1426 Support ARM cpu topology definition. The MPIDR register defines
1427 affinity between processors which is then used to describe the cpu
1428 topology of an ARM System.
1431 bool "Multi-core scheduler support"
1432 depends on ARM_CPU_TOPOLOGY
1434 Multi-core scheduler support improves the CPU scheduler's decision
1435 making when dealing with multi-core CPU chips at a cost of slightly
1436 increased overhead in some places. If unsure say N here.
1439 bool "SMT scheduler support"
1440 depends on ARM_CPU_TOPOLOGY
1442 Improves the CPU scheduler's decision making when dealing with
1443 MultiThreading at a cost of slightly increased overhead in some
1444 places. If unsure say N here.
1449 This option enables support for the ARM system coherency unit
1451 config HAVE_ARM_ARCH_TIMER
1452 bool "Architected timer support"
1454 select ARM_ARCH_TIMER
1455 select GENERIC_CLOCKEVENTS
1457 This option enables support for the ARM architected timer
1462 select CLKSRC_OF if OF
1464 This options enables support for the ARM timer and watchdog unit
1467 bool "Multi-Cluster Power Management"
1468 depends on CPU_V7 && SMP
1470 This option provides the common power management infrastructure
1471 for (multi-)cluster based systems, such as big.LITTLE based
1475 bool "big.LITTLE support (Experimental)"
1476 depends on CPU_V7 && SMP
1479 This option enables support selections for the big.LITTLE
1480 system architecture.
1483 bool "big.LITTLE switcher support"
1484 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1485 select ARM_CPU_SUSPEND
1488 The big.LITTLE "switcher" provides the core functionality to
1489 transparently handle transition between a cluster of A15's
1490 and a cluster of A7's in a big.LITTLE system.
1492 config BL_SWITCHER_DUMMY_IF
1493 tristate "Simple big.LITTLE switcher user interface"
1494 depends on BL_SWITCHER && DEBUG_KERNEL
1496 This is a simple and dummy char dev interface to control
1497 the big.LITTLE switcher core code. It is meant for
1498 debugging purposes only.
1501 prompt "Memory split"
1505 Select the desired split between kernel and user memory.
1507 If you are not absolutely sure what you are doing, leave this
1511 bool "3G/1G user/kernel split"
1513 bool "2G/2G user/kernel split"
1515 bool "1G/3G user/kernel split"
1520 default PHYS_OFFSET if !MMU
1521 default 0x40000000 if VMSPLIT_1G
1522 default 0x80000000 if VMSPLIT_2G
1526 int "Maximum number of CPUs (2-32)"
1532 bool "Support for hot-pluggable CPUs"
1535 Say Y here to experiment with turning CPUs off and on. CPUs
1536 can be controlled through /sys/devices/system/cpu.
1539 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1542 Say Y here if you want Linux to communicate with system firmware
1543 implementing the PSCI specification for CPU-centric power
1544 management operations described in ARM document number ARM DEN
1545 0022A ("Power State Coordination Interface System Software on
1548 # The GPIO number here must be sorted by descending number. In case of
1549 # a multiplatform kernel, we just want the highest value required by the
1550 # selected platforms.
1553 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1554 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1555 default 416 if ARCH_SUNXI
1556 default 392 if ARCH_U8500
1557 default 352 if ARCH_VT8500
1558 default 264 if MACH_H4700
1561 Maximum number of GPIOs in the system.
1563 If unsure, leave the default value.
1565 source kernel/Kconfig.preempt
1569 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1570 ARCH_S5PV210 || ARCH_EXYNOS4
1571 default AT91_TIMER_HZ if ARCH_AT91
1572 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1576 depends on HZ_FIXED = 0
1577 prompt "Timer frequency"
1601 default HZ_FIXED if HZ_FIXED != 0
1602 default 100 if HZ_100
1603 default 200 if HZ_200
1604 default 250 if HZ_250
1605 default 300 if HZ_300
1606 default 500 if HZ_500
1610 def_bool HIGH_RES_TIMERS
1612 config THUMB2_KERNEL
1613 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1614 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1615 default y if CPU_THUMBONLY
1617 select ARM_ASM_UNIFIED
1620 By enabling this option, the kernel will be compiled in
1621 Thumb-2 mode. A compiler/assembler that understand the unified
1622 ARM-Thumb syntax is needed.
1626 config THUMB2_AVOID_R_ARM_THM_JUMP11
1627 bool "Work around buggy Thumb-2 short branch relocations in gas"
1628 depends on THUMB2_KERNEL && MODULES
1631 Various binutils versions can resolve Thumb-2 branches to
1632 locally-defined, preemptible global symbols as short-range "b.n"
1633 branch instructions.
1635 This is a problem, because there's no guarantee the final
1636 destination of the symbol, or any candidate locations for a
1637 trampoline, are within range of the branch. For this reason, the
1638 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1639 relocation in modules at all, and it makes little sense to add
1642 The symptom is that the kernel fails with an "unsupported
1643 relocation" error when loading some modules.
1645 Until fixed tools are available, passing
1646 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1647 code which hits this problem, at the cost of a bit of extra runtime
1648 stack usage in some cases.
1650 The problem is described in more detail at:
1651 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1653 Only Thumb-2 kernels are affected.
1655 Unless you are sure your tools don't have this problem, say Y.
1657 config ARM_ASM_UNIFIED
1661 bool "Use the ARM EABI to compile the kernel"
1663 This option allows for the kernel to be compiled using the latest
1664 ARM ABI (aka EABI). This is only useful if you are using a user
1665 space environment that is also compiled with EABI.
1667 Since there are major incompatibilities between the legacy ABI and
1668 EABI, especially with regard to structure member alignment, this
1669 option also changes the kernel syscall calling convention to
1670 disambiguate both ABIs and allow for backward compatibility support
1671 (selected with CONFIG_OABI_COMPAT).
1673 To use this you need GCC version 4.0.0 or later.
1676 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1677 depends on AEABI && !THUMB2_KERNEL
1679 This option preserves the old syscall interface along with the
1680 new (ARM EABI) one. It also provides a compatibility layer to
1681 intercept syscalls that have structure arguments which layout
1682 in memory differs between the legacy ABI and the new ARM EABI
1683 (only for non "thumb" binaries). This option adds a tiny
1684 overhead to all syscalls and produces a slightly larger kernel.
1686 The seccomp filter system will not be available when this is
1687 selected, since there is no way yet to sensibly distinguish
1688 between calling conventions during filtering.
1690 If you know you'll be using only pure EABI user space then you
1691 can say N here. If this option is not selected and you attempt
1692 to execute a legacy ABI binary then the result will be
1693 UNPREDICTABLE (in fact it can be predicted that it won't work
1694 at all). If in doubt say N.
1696 config ARCH_HAS_HOLES_MEMORYMODEL
1699 config ARCH_SPARSEMEM_ENABLE
1702 config ARCH_SPARSEMEM_DEFAULT
1703 def_bool ARCH_SPARSEMEM_ENABLE
1705 config ARCH_SELECT_MEMORY_MODEL
1706 def_bool ARCH_SPARSEMEM_ENABLE
1708 config HAVE_ARCH_PFN_VALID
1709 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1712 bool "High Memory Support"
1715 The address space of ARM processors is only 4 Gigabytes large
1716 and it has to accommodate user address space, kernel address
1717 space as well as some memory mapped IO. That means that, if you
1718 have a large amount of physical memory and/or IO, not all of the
1719 memory can be "permanently mapped" by the kernel. The physical
1720 memory that is not permanently mapped is called "high memory".
1722 Depending on the selected kernel/user memory split, minimum
1723 vmalloc space and actual amount of RAM, you may not need this
1724 option which should result in a slightly faster kernel.
1729 bool "Allocate 2nd-level pagetables from highmem"
1732 config HW_PERF_EVENTS
1733 bool "Enable hardware performance counter support for perf events"
1734 depends on PERF_EVENTS
1737 Enable hardware performance counter support for perf events. If
1738 disabled, perf events will use software events only.
1740 config SYS_SUPPORTS_HUGETLBFS
1744 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1748 config ARCH_WANT_GENERAL_HUGETLB
1753 config FORCE_MAX_ZONEORDER
1754 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1755 range 11 64 if ARCH_SHMOBILE_LEGACY
1756 default "12" if SOC_AM33XX
1757 default "9" if SA1111 || ARCH_EFM32
1760 The kernel memory allocator divides physically contiguous memory
1761 blocks into "zones", where each zone is a power of two number of
1762 pages. This option selects the largest power of two that the kernel
1763 keeps in the memory allocator. If you need to allocate very large
1764 blocks of physically contiguous memory, then you may need to
1765 increase this value.
1767 This config option is actually maximum order plus one. For example,
1768 a value of 11 means that the largest free memory block is 2^10 pages.
1770 config ALIGNMENT_TRAP
1772 depends on CPU_CP15_MMU
1773 default y if !ARCH_EBSA110
1774 select HAVE_PROC_CPU if PROC_FS
1776 ARM processors cannot fetch/store information which is not
1777 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1778 address divisible by 4. On 32-bit ARM processors, these non-aligned
1779 fetch/store instructions will be emulated in software if you say
1780 here, which has a severe performance impact. This is necessary for
1781 correct operation of some network protocols. With an IP-only
1782 configuration it is safe to say N, otherwise say Y.
1784 config UACCESS_WITH_MEMCPY
1785 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1787 default y if CPU_FEROCEON
1789 Implement faster copy_to_user and clear_user methods for CPU
1790 cores where a 8-word STM instruction give significantly higher
1791 memory write throughput than a sequence of individual 32bit stores.
1793 A possible side effect is a slight increase in scheduling latency
1794 between threads sharing the same address space if they invoke
1795 such copy operations with large buffers.
1797 However, if the CPU data cache is using a write-allocate mode,
1798 this option is unlikely to provide any performance gain.
1802 prompt "Enable seccomp to safely compute untrusted bytecode"
1804 This kernel feature is useful for number crunching applications
1805 that may need to compute untrusted bytecode during their
1806 execution. By using pipes or other transports made available to
1807 the process as file descriptors supporting the read/write
1808 syscalls, it's possible to isolate those applications in
1809 their own address space using seccomp. Once seccomp is
1810 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1811 and the task is only allowed to execute a few safe syscalls
1812 defined by each seccomp mode.
1825 bool "Xen guest support on ARM (EXPERIMENTAL)"
1826 depends on ARM && AEABI && OF
1827 depends on CPU_V7 && !CPU_V6
1828 depends on !GENERIC_ATOMIC64
1830 select ARCH_DMA_ADDR_T_64BIT
1834 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1841 bool "Flattened Device Tree support"
1844 select OF_EARLY_FLATTREE
1845 select OF_RESERVED_MEM
1847 Include support for flattened device tree machine descriptions.
1850 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1853 This is the traditional way of passing data to the kernel at boot
1854 time. If you are solely relying on the flattened device tree (or
1855 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1856 to remove ATAGS support from your kernel binary. If unsure,
1859 config DEPRECATED_PARAM_STRUCT
1860 bool "Provide old way to pass kernel parameters"
1863 This was deprecated in 2001 and announced to live on for 5 years.
1864 Some old boot loaders still use this way.
1866 # Compressed boot loader in ROM. Yes, we really want to ask about
1867 # TEXT and BSS so we preserve their values in the config files.
1868 config ZBOOT_ROM_TEXT
1869 hex "Compressed ROM boot loader base address"
1872 The physical address at which the ROM-able zImage is to be
1873 placed in the target. Platforms which normally make use of
1874 ROM-able zImage formats normally set this to a suitable
1875 value in their defconfig file.
1877 If ZBOOT_ROM is not enabled, this has no effect.
1879 config ZBOOT_ROM_BSS
1880 hex "Compressed ROM boot loader BSS address"
1883 The base address of an area of read/write memory in the target
1884 for the ROM-able zImage which must be available while the
1885 decompressor is running. It must be large enough to hold the
1886 entire decompressed kernel plus an additional 128 KiB.
1887 Platforms which normally make use of ROM-able zImage formats
1888 normally set this to a suitable value in their defconfig file.
1890 If ZBOOT_ROM is not enabled, this has no effect.
1893 bool "Compressed boot loader in ROM/flash"
1894 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1895 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1897 Say Y here if you intend to execute your compressed kernel image
1898 (zImage) directly from ROM or flash. If unsure, say N.
1901 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1902 depends on ZBOOT_ROM && ARCH_SH7372
1903 default ZBOOT_ROM_NONE
1905 Include experimental SD/MMC loading code in the ROM-able zImage.
1906 With this enabled it is possible to write the ROM-able zImage
1907 kernel image to an MMC or SD card and boot the kernel straight
1908 from the reset vector. At reset the processor Mask ROM will load
1909 the first part of the ROM-able zImage which in turn loads the
1910 rest the kernel image to RAM.
1912 config ZBOOT_ROM_NONE
1913 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1915 Do not load image from SD or MMC
1917 config ZBOOT_ROM_MMCIF
1918 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1920 Load image from MMCIF hardware block.
1922 config ZBOOT_ROM_SH_MOBILE_SDHI
1923 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1925 Load image from SDHI hardware block
1929 config ARM_APPENDED_DTB
1930 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1933 With this option, the boot code will look for a device tree binary
1934 (DTB) appended to zImage
1935 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1937 This is meant as a backward compatibility convenience for those
1938 systems with a bootloader that can't be upgraded to accommodate
1939 the documented boot protocol using a device tree.
1941 Beware that there is very little in terms of protection against
1942 this option being confused by leftover garbage in memory that might
1943 look like a DTB header after a reboot if no actual DTB is appended
1944 to zImage. Do not leave this option active in a production kernel
1945 if you don't intend to always append a DTB. Proper passing of the
1946 location into r2 of a bootloader provided DTB is always preferable
1949 config ARM_ATAG_DTB_COMPAT
1950 bool "Supplement the appended DTB with traditional ATAG information"
1951 depends on ARM_APPENDED_DTB
1953 Some old bootloaders can't be updated to a DTB capable one, yet
1954 they provide ATAGs with memory configuration, the ramdisk address,
1955 the kernel cmdline string, etc. Such information is dynamically
1956 provided by the bootloader and can't always be stored in a static
1957 DTB. To allow a device tree enabled kernel to be used with such
1958 bootloaders, this option allows zImage to extract the information
1959 from the ATAG list and store it at run time into the appended DTB.
1962 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1963 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1965 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1966 bool "Use bootloader kernel arguments if available"
1968 Uses the command-line options passed by the boot loader instead of
1969 the device tree bootargs property. If the boot loader doesn't provide
1970 any, the device tree bootargs property will be used.
1972 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1973 bool "Extend with bootloader kernel arguments"
1975 The command-line arguments provided by the boot loader will be
1976 appended to the the device tree bootargs property.
1981 string "Default kernel command string"
1984 On some architectures (EBSA110 and CATS), there is currently no way
1985 for the boot loader to pass arguments to the kernel. For these
1986 architectures, you should supply some command-line options at build
1987 time by entering them here. As a minimum, you should specify the
1988 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1991 prompt "Kernel command line type" if CMDLINE != ""
1992 default CMDLINE_FROM_BOOTLOADER
1995 config CMDLINE_FROM_BOOTLOADER
1996 bool "Use bootloader kernel arguments if available"
1998 Uses the command-line options passed by the boot loader. If
1999 the boot loader doesn't provide any, the default kernel command
2000 string provided in CMDLINE will be used.
2002 config CMDLINE_EXTEND
2003 bool "Extend bootloader kernel arguments"
2005 The command-line arguments provided by the boot loader will be
2006 appended to the default kernel command string.
2008 config CMDLINE_FORCE
2009 bool "Always use the default kernel command string"
2011 Always use the default kernel command string, even if the boot
2012 loader passes other arguments to the kernel.
2013 This is useful if you cannot or don't want to change the
2014 command-line options your boot loader passes to the kernel.
2018 bool "Kernel Execute-In-Place from ROM"
2019 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2021 Execute-In-Place allows the kernel to run from non-volatile storage
2022 directly addressable by the CPU, such as NOR flash. This saves RAM
2023 space since the text section of the kernel is not loaded from flash
2024 to RAM. Read-write sections, such as the data section and stack,
2025 are still copied to RAM. The XIP kernel is not compressed since
2026 it has to run directly from flash, so it will take more space to
2027 store it. The flash address used to link the kernel object files,
2028 and for storing it, is configuration dependent. Therefore, if you
2029 say Y here, you must know the proper physical address where to
2030 store the kernel image depending on your own flash memory usage.
2032 Also note that the make target becomes "make xipImage" rather than
2033 "make zImage" or "make Image". The final kernel binary to put in
2034 ROM memory will be arch/arm/boot/xipImage.
2038 config XIP_PHYS_ADDR
2039 hex "XIP Kernel Physical Location"
2040 depends on XIP_KERNEL
2041 default "0x00080000"
2043 This is the physical address in your flash memory the kernel will
2044 be linked for and stored to. This address is dependent on your
2048 bool "Kexec system call (EXPERIMENTAL)"
2049 depends on (!SMP || PM_SLEEP_SMP)
2051 kexec is a system call that implements the ability to shutdown your
2052 current kernel, and to start another kernel. It is like a reboot
2053 but it is independent of the system firmware. And like a reboot
2054 you can start any kernel with it, not just Linux.
2056 It is an ongoing process to be certain the hardware in a machine
2057 is properly shutdown, so do not be surprised if this code does not
2058 initially work for you.
2061 bool "Export atags in procfs"
2062 depends on ATAGS && KEXEC
2065 Should the atags used to boot the kernel be exported in an "atags"
2066 file in procfs. Useful with kexec.
2069 bool "Build kdump crash kernel (EXPERIMENTAL)"
2071 Generate crash dump after being started by kexec. This should
2072 be normally only set in special crash dump kernels which are
2073 loaded in the main kernel with kexec-tools into a specially
2074 reserved region and then later executed after a crash by
2075 kdump/kexec. The crash dump kernel must be compiled to a
2076 memory address not used by the main kernel
2078 For more details see Documentation/kdump/kdump.txt
2080 config AUTO_ZRELADDR
2081 bool "Auto calculation of the decompressed kernel image address"
2083 ZRELADDR is the physical address where the decompressed kernel
2084 image will be placed. If AUTO_ZRELADDR is selected, the address
2085 will be determined at run-time by masking the current IP with
2086 0xf8000000. This assumes the zImage being placed in the first 128MB
2087 from start of memory.
2091 menu "CPU Power Management"
2093 source "drivers/cpufreq/Kconfig"
2095 source "drivers/cpuidle/Kconfig"
2099 menu "Floating point emulation"
2101 comment "At least one emulation must be selected"
2104 bool "NWFPE math emulation"
2105 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2107 Say Y to include the NWFPE floating point emulator in the kernel.
2108 This is necessary to run most binaries. Linux does not currently
2109 support floating point hardware so you need to say Y here even if
2110 your machine has an FPA or floating point co-processor podule.
2112 You may say N here if you are going to load the Acorn FPEmulator
2113 early in the bootup.
2116 bool "Support extended precision"
2117 depends on FPE_NWFPE
2119 Say Y to include 80-bit support in the kernel floating-point
2120 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2121 Note that gcc does not generate 80-bit operations by default,
2122 so in most cases this option only enlarges the size of the
2123 floating point emulator without any good reason.
2125 You almost surely want to say N here.
2128 bool "FastFPE math emulation (EXPERIMENTAL)"
2129 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2131 Say Y here to include the FAST floating point emulator in the kernel.
2132 This is an experimental much faster emulator which now also has full
2133 precision for the mantissa. It does not support any exceptions.
2134 It is very simple, and approximately 3-6 times faster than NWFPE.
2136 It should be sufficient for most programs. It may be not suitable
2137 for scientific calculations, but you have to check this for yourself.
2138 If you do not feel you need a faster FP emulation you should better
2142 bool "VFP-format floating point maths"
2143 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2145 Say Y to include VFP support code in the kernel. This is needed
2146 if your hardware includes a VFP unit.
2148 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2149 release notes and additional status information.
2151 Say N if your target does not have VFP hardware.
2159 bool "Advanced SIMD (NEON) Extension support"
2160 depends on VFPv3 && CPU_V7
2162 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2165 config KERNEL_MODE_NEON
2166 bool "Support for NEON in kernel mode"
2167 depends on NEON && AEABI
2169 Say Y to include support for NEON in kernel mode.
2173 menu "Userspace binary formats"
2175 source "fs/Kconfig.binfmt"
2178 tristate "RISC OS personality"
2181 Say Y here to include the kernel code necessary if you want to run
2182 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2183 experimental; if this sounds frightening, say N and sleep in peace.
2184 You can also say M here to compile this support as a module (which
2185 will be called arthur).
2189 menu "Power management options"
2191 source "kernel/power/Kconfig"
2193 config ARCH_SUSPEND_POSSIBLE
2194 depends on !ARCH_S5PC100
2195 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2196 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2199 config ARM_CPU_SUSPEND
2202 config ARCH_HIBERNATION_POSSIBLE
2205 default y if ARCH_SUSPEND_POSSIBLE
2209 source "net/Kconfig"
2211 source "drivers/Kconfig"
2215 source "arch/arm/Kconfig.debug"
2217 source "security/Kconfig"
2219 source "crypto/Kconfig"
2221 source "lib/Kconfig"
2223 source "arch/arm/kvm/Kconfig"