4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CPU_PM if (SUSPEND || CPU_IDLE)
11 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
12 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
13 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
14 select GENERIC_IRQ_PROBE
15 select GENERIC_IRQ_SHOW
16 select GENERIC_PCI_IOMAP
17 select GENERIC_SMP_IDLE_THREAD
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_STRNCPY_FROM_USER
20 select GENERIC_STRNLEN_USER
21 select HARDIRQS_SW_RESEND
23 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
25 select HAVE_ARCH_SECCOMP_FILTER
26 select HAVE_ARCH_TRACEHOOK
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_DEBUG_KMEMLEAK
30 select HAVE_DMA_API_DEBUG
32 select HAVE_DMA_CONTIGUOUS if MMU
33 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
34 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
35 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
36 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
37 select HAVE_GENERIC_DMA_COHERENT
38 select HAVE_GENERIC_HARDIRQS
39 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
40 select HAVE_IDE if PCI || ISA || PCMCIA
41 select HAVE_IRQ_TIME_ACCOUNTING
42 select HAVE_KERNEL_GZIP
43 select HAVE_KERNEL_LZMA
44 select HAVE_KERNEL_LZO
46 select HAVE_KPROBES if !XIP_KERNEL
47 select HAVE_KRETPROBES if (HAVE_KPROBES)
49 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
50 select HAVE_PERF_EVENTS
51 select HAVE_REGS_AND_STACK_ACCESS_API
52 select HAVE_SYSCALL_TRACEPOINTS
55 select PERF_USE_VMALLOC
57 select SYS_SUPPORTS_APM_EMULATION
58 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
59 select MODULES_USE_ELF_REL
60 select CLONE_BACKWARDS
61 select OLD_SIGSUSPEND3
63 select HAVE_CONTEXT_TRACKING
65 The ARM series is a line of low-power-consumption RISC chip designs
66 licensed by ARM Ltd and targeted at embedded applications and
67 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
68 manufactured, but legacy ARM-based PC hardware remains popular in
69 Europe. There is an ARM Linux project with a web page at
70 <http://www.arm.linux.org.uk/>.
72 config ARM_HAS_SG_CHAIN
75 config NEED_SG_DMA_LENGTH
78 config ARM_DMA_USE_IOMMU
80 select ARM_HAS_SG_CHAIN
81 select NEED_SG_DMA_LENGTH
85 config ARM_DMA_IOMMU_ALIGNMENT
86 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
90 DMA mapping framework by default aligns all buffers to the smallest
91 PAGE_SIZE order which is greater than or equal to the requested buffer
92 size. This works well for buffers up to a few hundreds kilobytes, but
93 for larger buffers it just a waste of address space. Drivers which has
94 relatively small addressing window (like 64Mib) might run out of
95 virtual space with just a few allocations.
97 With this parameter you can specify the maximum PAGE_SIZE order for
98 DMA IOMMU buffers. Larger buffers will be aligned only to this
99 specified order. The order is expressed as a power of two multiplied
107 config MIGHT_HAVE_PCI
110 config SYS_SUPPORTS_APM_EMULATION
115 select GENERIC_ALLOCATOR
126 The Extended Industry Standard Architecture (EISA) bus was
127 developed as an open alternative to the IBM MicroChannel bus.
129 The EISA bus provided some of the features of the IBM MicroChannel
130 bus while maintaining backward compatibility with cards made for
131 the older ISA bus. The EISA bus saw limited use between 1988 and
132 1995 when it was made obsolete by the PCI bus.
134 Say Y here if you are building a kernel for an EISA-based machine.
141 config STACKTRACE_SUPPORT
145 config HAVE_LATENCYTOP_SUPPORT
150 config LOCKDEP_SUPPORT
154 config TRACE_IRQFLAGS_SUPPORT
158 config RWSEM_GENERIC_SPINLOCK
162 config RWSEM_XCHGADD_ALGORITHM
165 config ARCH_HAS_ILOG2_U32
168 config ARCH_HAS_ILOG2_U64
171 config ARCH_HAS_CPUFREQ
174 Internal node to signify that the ARCH has CPUFREQ support
175 and that the relevant menu configurations are displayed for
178 config GENERIC_HWEIGHT
182 config GENERIC_CALIBRATE_DELAY
186 config ARCH_MAY_HAVE_PC_FDC
192 config NEED_DMA_MAP_STATE
195 config ARCH_HAS_DMA_SET_COHERENT_MASK
198 config GENERIC_ISA_DMA
204 config NEED_RET_TO_USER
212 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
213 default DRAM_BASE if REMAP_VECTORS_TO_RAM
216 The base address of exception vectors.
218 config ARM_PATCH_PHYS_VIRT
219 bool "Patch physical to virtual translations at runtime" if EMBEDDED
221 depends on !XIP_KERNEL && MMU
222 depends on !ARCH_REALVIEW || !SPARSEMEM
224 Patch phys-to-virt and virt-to-phys translation functions at
225 boot and module load time according to the position of the
226 kernel in system memory.
228 This can only be used with non-XIP MMU kernels where the base
229 of physical memory is at a 16MB boundary.
231 Only disable this option if you know that you do not require
232 this feature (eg, building a kernel for a single machine) and
233 you need to shrink the kernel to the minimal size.
235 config NEED_MACH_GPIO_H
238 Select this when mach/gpio.h is required to provide special
239 definitions for this platform. The need for mach/gpio.h should
240 be avoided when possible.
242 config NEED_MACH_IO_H
245 Select this when mach/io.h is required to provide special
246 definitions for this platform. The need for mach/io.h should
247 be avoided when possible.
249 config NEED_MACH_MEMORY_H
252 Select this when mach/memory.h is required to provide special
253 definitions for this platform. The need for mach/memory.h should
254 be avoided when possible.
257 hex "Physical address of main memory" if MMU
258 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
259 default DRAM_BASE if !MMU
261 Please provide the physical address corresponding to the
262 location of main memory in your system.
268 source "init/Kconfig"
270 source "kernel/Kconfig.freezer"
275 bool "MMU-based Paged Memory Management Support"
278 Select if you want MMU-based virtualised addressing space
279 support by paged memory management. If unsure, say 'Y'.
282 # The "ARM system type" choice list is ordered alphabetically by option
283 # text. Please add new entries in the option alphabetic order.
286 prompt "ARM system type"
287 default ARCH_VERSATILE if !MMU
288 default ARCH_MULTIPLATFORM if MMU
290 config ARCH_MULTIPLATFORM
291 bool "Allow multiple platforms to be selected"
293 select ARM_PATCH_PHYS_VIRT
296 select MULTI_IRQ_HANDLER
300 config ARCH_INTEGRATOR
301 bool "ARM Ltd. Integrator family"
302 select ARCH_HAS_CPUFREQ
305 select COMMON_CLK_VERSATILE
306 select GENERIC_CLOCKEVENTS
309 select MULTI_IRQ_HANDLER
310 select NEED_MACH_MEMORY_H
311 select PLAT_VERSATILE
313 select VERSATILE_FPGA_IRQ
315 Support for ARM's Integrator platform.
318 bool "ARM Ltd. RealView family"
319 select ARCH_WANT_OPTIONAL_GPIOLIB
321 select ARM_TIMER_SP804
323 select COMMON_CLK_VERSATILE
324 select GENERIC_CLOCKEVENTS
325 select GPIO_PL061 if GPIOLIB
327 select NEED_MACH_MEMORY_H
328 select PLAT_VERSATILE
329 select PLAT_VERSATILE_CLCD
331 This enables support for ARM Ltd RealView boards.
333 config ARCH_VERSATILE
334 bool "ARM Ltd. Versatile family"
335 select ARCH_WANT_OPTIONAL_GPIOLIB
337 select ARM_TIMER_SP804
340 select GENERIC_CLOCKEVENTS
341 select HAVE_MACH_CLKDEV
343 select PLAT_VERSATILE
344 select PLAT_VERSATILE_CLCD
345 select PLAT_VERSATILE_CLOCK
346 select VERSATILE_FPGA_IRQ
348 This enables support for ARM Ltd Versatile board.
352 select ARCH_REQUIRE_GPIOLIB
356 select NEED_MACH_GPIO_H
357 select NEED_MACH_IO_H if PCCARD
359 select PINCTRL_AT91 if USE_OF
361 This enables support for systems based on Atmel
362 AT91RM9200 and AT91SAM9* processors.
365 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
366 select ARCH_REQUIRE_GPIOLIB
371 select GENERIC_CLOCKEVENTS
372 select MULTI_IRQ_HANDLER
373 select NEED_MACH_MEMORY_H
376 Support for Cirrus Logic 711x/721x/731x based boards.
379 bool "Cortina Systems Gemini"
380 select ARCH_REQUIRE_GPIOLIB
381 select ARCH_USES_GETTIMEOFFSET
382 select NEED_MACH_GPIO_H
385 Support for the Cortina Systems Gemini family SoCs
389 select ARCH_USES_GETTIMEOFFSET
392 select NEED_MACH_IO_H
393 select NEED_MACH_MEMORY_H
396 This is an evaluation board for the StrongARM processor available
397 from Digital. It has limited hardware on-board, including an
398 Ethernet interface, two PCMCIA sockets, two serial ports and a
403 select ARCH_HAS_HOLES_MEMORYMODEL
404 select ARCH_REQUIRE_GPIOLIB
405 select ARCH_USES_GETTIMEOFFSET
410 select NEED_MACH_MEMORY_H
412 This enables support for the Cirrus EP93xx series of CPUs.
414 config ARCH_FOOTBRIDGE
418 select GENERIC_CLOCKEVENTS
420 select NEED_MACH_IO_H if !MMU
421 select NEED_MACH_MEMORY_H
423 Support for systems based on the DC21285 companion chip
424 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
427 bool "Hilscher NetX based"
431 select GENERIC_CLOCKEVENTS
433 This enables support for systems based on the Hilscher NetX Soc
438 select ARCH_SUPPORTS_MSI
440 select NEED_MACH_MEMORY_H
441 select NEED_RET_TO_USER
446 Support for Intel's IOP13XX (XScale) family of processors.
451 select ARCH_REQUIRE_GPIOLIB
453 select NEED_MACH_GPIO_H
454 select NEED_RET_TO_USER
458 Support for Intel's 80219 and IOP32X (XScale) family of
464 select ARCH_REQUIRE_GPIOLIB
466 select NEED_MACH_GPIO_H
467 select NEED_RET_TO_USER
471 Support for Intel's IOP33X (XScale) family of processors.
476 select ARCH_HAS_DMA_SET_COHERENT_MASK
477 select ARCH_REQUIRE_GPIOLIB
480 select DMABOUNCE if PCI
481 select GENERIC_CLOCKEVENTS
482 select MIGHT_HAVE_PCI
483 select NEED_MACH_IO_H
484 select USB_EHCI_BIG_ENDIAN_MMIO
485 select USB_EHCI_BIG_ENDIAN_DESC
487 Support for Intel's IXP4XX (XScale) family of processors.
491 select ARCH_REQUIRE_GPIOLIB
493 select GENERIC_CLOCKEVENTS
494 select MIGHT_HAVE_PCI
497 select PLAT_ORION_LEGACY
498 select USB_ARCH_HAS_EHCI
501 Support for the Marvell Dove SoC 88AP510
504 bool "Marvell Kirkwood"
505 select ARCH_REQUIRE_GPIOLIB
507 select GENERIC_CLOCKEVENTS
511 select PINCTRL_KIRKWOOD
512 select PLAT_ORION_LEGACY
515 Support for the following Marvell Kirkwood series SoCs:
516 88F6180, 88F6192 and 88F6281.
519 bool "Marvell MV78xx0"
520 select ARCH_REQUIRE_GPIOLIB
522 select GENERIC_CLOCKEVENTS
524 select PLAT_ORION_LEGACY
527 Support for the following Marvell MV78xx0 series SoCs:
533 select ARCH_REQUIRE_GPIOLIB
535 select GENERIC_CLOCKEVENTS
537 select PLAT_ORION_LEGACY
540 Support for the following Marvell Orion 5x series SoCs:
541 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
542 Orion-2 (5281), Orion-1-90 (6183).
545 bool "Marvell PXA168/910/MMP2"
547 select ARCH_REQUIRE_GPIOLIB
549 select GENERIC_ALLOCATOR
550 select GENERIC_CLOCKEVENTS
553 select NEED_MACH_GPIO_H
558 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
561 bool "Micrel/Kendin KS8695"
562 select ARCH_REQUIRE_GPIOLIB
565 select GENERIC_CLOCKEVENTS
566 select NEED_MACH_MEMORY_H
568 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
569 System-on-Chip devices.
572 bool "Nuvoton W90X900 CPU"
573 select ARCH_REQUIRE_GPIOLIB
577 select GENERIC_CLOCKEVENTS
579 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
580 At present, the w90x900 has been renamed nuc900, regarding
581 the ARM series product line, you can login the following
582 link address to know more.
584 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
585 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
589 select ARCH_REQUIRE_GPIOLIB
594 select GENERIC_CLOCKEVENTS
597 select USB_ARCH_HAS_OHCI
600 Support for the NXP LPC32XX family of processors
603 bool "PXA2xx/PXA3xx-based"
605 select ARCH_HAS_CPUFREQ
607 select ARCH_REQUIRE_GPIOLIB
608 select ARM_CPU_SUSPEND if PM
612 select GENERIC_CLOCKEVENTS
615 select MULTI_IRQ_HANDLER
616 select NEED_MACH_GPIO_H
620 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
624 select ARCH_REQUIRE_GPIOLIB
626 select GENERIC_CLOCKEVENTS
629 Support for Qualcomm MSM/QSD based systems. This runs on the
630 apps processor of the MSM/QSD and depends on a shared memory
631 interface to the modem processor which runs the baseband
632 stack and controls some vital subsystems
633 (clock and power control, etc).
636 bool "Renesas SH-Mobile / R-Mobile"
638 select GENERIC_CLOCKEVENTS
639 select HAVE_ARM_SCU if SMP
640 select HAVE_ARM_TWD if LOCAL_TIMERS
642 select HAVE_MACH_CLKDEV
644 select MIGHT_HAVE_CACHE_L2X0
645 select MULTI_IRQ_HANDLER
646 select NEED_MACH_MEMORY_H
648 select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
649 select PM_GENERIC_DOMAINS if PM
652 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
657 select ARCH_MAY_HAVE_PC_FDC
658 select ARCH_SPARSEMEM_ENABLE
659 select ARCH_USES_GETTIMEOFFSET
662 select HAVE_PATA_PLATFORM
664 select NEED_MACH_IO_H
665 select NEED_MACH_MEMORY_H
669 On the Acorn Risc-PC, Linux can support the internal IDE disk and
670 CD-ROM interface, serial and parallel port, and the floppy drive.
674 select ARCH_HAS_CPUFREQ
676 select ARCH_REQUIRE_GPIOLIB
677 select ARCH_SPARSEMEM_ENABLE
682 select GENERIC_CLOCKEVENTS
685 select NEED_MACH_GPIO_H
686 select NEED_MACH_MEMORY_H
689 Support for StrongARM 11x0 based boards.
692 bool "Samsung S3C24XX SoCs"
693 select ARCH_HAS_CPUFREQ
694 select ARCH_REQUIRE_GPIOLIB
697 select GENERIC_CLOCKEVENTS
699 select HAVE_S3C2410_I2C if I2C
700 select HAVE_S3C2410_WATCHDOG if WATCHDOG
701 select HAVE_S3C_RTC if RTC_CLASS
702 select MULTI_IRQ_HANDLER
703 select NEED_MACH_GPIO_H
704 select NEED_MACH_IO_H
706 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
707 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
708 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
709 Samsung SMDK2410 development board (and derivatives).
712 bool "Samsung S3C64XX"
713 select ARCH_HAS_CPUFREQ
714 select ARCH_REQUIRE_GPIOLIB
719 select GENERIC_CLOCKEVENTS
721 select HAVE_S3C2410_I2C if I2C
722 select HAVE_S3C2410_WATCHDOG if WATCHDOG
724 select NEED_MACH_GPIO_H
728 select S3C_GPIO_TRACK
729 select SAMSUNG_CLKSRC
730 select SAMSUNG_GPIOLIB_4BIT
731 select SAMSUNG_IRQ_VIC_TIMER
732 select USB_ARCH_HAS_OHCI
734 Samsung S3C64XX series based systems
737 bool "Samsung S5P6440 S5P6450"
741 select GENERIC_CLOCKEVENTS
743 select HAVE_S3C2410_I2C if I2C
744 select HAVE_S3C2410_WATCHDOG if WATCHDOG
745 select HAVE_S3C_RTC if RTC_CLASS
746 select NEED_MACH_GPIO_H
748 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
752 bool "Samsung S5PC100"
753 select ARCH_REQUIRE_GPIOLIB
757 select GENERIC_CLOCKEVENTS
759 select HAVE_S3C2410_I2C if I2C
760 select HAVE_S3C2410_WATCHDOG if WATCHDOG
761 select HAVE_S3C_RTC if RTC_CLASS
762 select NEED_MACH_GPIO_H
764 Samsung S5PC100 series based systems
767 bool "Samsung S5PV210/S5PC110"
768 select ARCH_HAS_CPUFREQ
769 select ARCH_HAS_HOLES_MEMORYMODEL
770 select ARCH_SPARSEMEM_ENABLE
774 select GENERIC_CLOCKEVENTS
776 select HAVE_S3C2410_I2C if I2C
777 select HAVE_S3C2410_WATCHDOG if WATCHDOG
778 select HAVE_S3C_RTC if RTC_CLASS
779 select NEED_MACH_GPIO_H
780 select NEED_MACH_MEMORY_H
782 Samsung S5PV210/S5PC110 series based systems
785 bool "Samsung EXYNOS"
786 select ARCH_HAS_CPUFREQ
787 select ARCH_HAS_HOLES_MEMORYMODEL
788 select ARCH_SPARSEMEM_ENABLE
792 select GENERIC_CLOCKEVENTS
794 select HAVE_S3C2410_I2C if I2C
795 select HAVE_S3C2410_WATCHDOG if WATCHDOG
796 select HAVE_S3C_RTC if RTC_CLASS
797 select NEED_MACH_GPIO_H
798 select NEED_MACH_MEMORY_H
800 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
804 select ARCH_USES_GETTIMEOFFSET
808 select NEED_MACH_MEMORY_H
813 Support for the StrongARM based Digital DNARD machine, also known
814 as "Shark" (<http://www.shark-linux.de/shark.html>).
817 bool "ST-Ericsson U300 Series"
819 select ARCH_REQUIRE_GPIOLIB
821 select ARM_PATCH_PHYS_VIRT
827 select GENERIC_CLOCKEVENTS
831 Support for ST-Ericsson U300 series mobile platforms.
835 select ARCH_HAS_HOLES_MEMORYMODEL
836 select ARCH_REQUIRE_GPIOLIB
838 select GENERIC_ALLOCATOR
839 select GENERIC_CLOCKEVENTS
840 select GENERIC_IRQ_CHIP
842 select NEED_MACH_GPIO_H
846 Support for TI's DaVinci platform.
851 select ARCH_HAS_CPUFREQ
852 select ARCH_HAS_HOLES_MEMORYMODEL
854 select ARCH_REQUIRE_GPIOLIB
857 select GENERIC_CLOCKEVENTS
858 select GENERIC_IRQ_CHIP
862 select NEED_MACH_IO_H if PCCARD
863 select NEED_MACH_MEMORY_H
865 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
869 menu "Multiple platform selection"
870 depends on ARCH_MULTIPLATFORM
872 comment "CPU Core family selection"
875 bool "ARMv4 based platforms (FA526, StrongARM)"
876 depends on !ARCH_MULTI_V6_V7
877 select ARCH_MULTI_V4_V5
879 config ARCH_MULTI_V4T
880 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
881 depends on !ARCH_MULTI_V6_V7
882 select ARCH_MULTI_V4_V5
885 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
886 depends on !ARCH_MULTI_V6_V7
887 select ARCH_MULTI_V4_V5
889 config ARCH_MULTI_V4_V5
893 bool "ARMv6 based platforms (ARM11)"
894 select ARCH_MULTI_V6_V7
898 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
900 select ARCH_MULTI_V6_V7
903 config ARCH_MULTI_V6_V7
906 config ARCH_MULTI_CPU_AUTO
907 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
913 # This is sorted alphabetically by mach-* pathname. However, plat-*
914 # Kconfigs may be included either alphabetically (according to the
915 # plat- suffix) or along side the corresponding mach-* source.
917 source "arch/arm/mach-mvebu/Kconfig"
919 source "arch/arm/mach-at91/Kconfig"
921 source "arch/arm/mach-bcm/Kconfig"
923 source "arch/arm/mach-bcm2835/Kconfig"
925 source "arch/arm/mach-clps711x/Kconfig"
927 source "arch/arm/mach-cns3xxx/Kconfig"
929 source "arch/arm/mach-davinci/Kconfig"
931 source "arch/arm/mach-dove/Kconfig"
933 source "arch/arm/mach-ep93xx/Kconfig"
935 source "arch/arm/mach-footbridge/Kconfig"
937 source "arch/arm/mach-gemini/Kconfig"
939 source "arch/arm/mach-highbank/Kconfig"
941 source "arch/arm/mach-integrator/Kconfig"
943 source "arch/arm/mach-iop32x/Kconfig"
945 source "arch/arm/mach-iop33x/Kconfig"
947 source "arch/arm/mach-iop13xx/Kconfig"
949 source "arch/arm/mach-ixp4xx/Kconfig"
951 source "arch/arm/mach-kirkwood/Kconfig"
953 source "arch/arm/mach-ks8695/Kconfig"
955 source "arch/arm/mach-msm/Kconfig"
957 source "arch/arm/mach-mv78xx0/Kconfig"
959 source "arch/arm/mach-imx/Kconfig"
961 source "arch/arm/mach-mxs/Kconfig"
963 source "arch/arm/mach-netx/Kconfig"
965 source "arch/arm/mach-nomadik/Kconfig"
967 source "arch/arm/plat-omap/Kconfig"
969 source "arch/arm/mach-omap1/Kconfig"
971 source "arch/arm/mach-omap2/Kconfig"
973 source "arch/arm/mach-orion5x/Kconfig"
975 source "arch/arm/mach-picoxcell/Kconfig"
977 source "arch/arm/mach-pxa/Kconfig"
978 source "arch/arm/plat-pxa/Kconfig"
980 source "arch/arm/mach-mmp/Kconfig"
982 source "arch/arm/mach-realview/Kconfig"
984 source "arch/arm/mach-sa1100/Kconfig"
986 source "arch/arm/plat-samsung/Kconfig"
988 source "arch/arm/mach-socfpga/Kconfig"
990 source "arch/arm/mach-spear/Kconfig"
992 source "arch/arm/mach-s3c24xx/Kconfig"
995 source "arch/arm/mach-s3c64xx/Kconfig"
998 source "arch/arm/mach-s5p64x0/Kconfig"
1000 source "arch/arm/mach-s5pc100/Kconfig"
1002 source "arch/arm/mach-s5pv210/Kconfig"
1004 source "arch/arm/mach-exynos/Kconfig"
1006 source "arch/arm/mach-shmobile/Kconfig"
1008 source "arch/arm/mach-sunxi/Kconfig"
1010 source "arch/arm/mach-prima2/Kconfig"
1012 source "arch/arm/mach-tegra/Kconfig"
1014 source "arch/arm/mach-u300/Kconfig"
1016 source "arch/arm/mach-ux500/Kconfig"
1018 source "arch/arm/mach-versatile/Kconfig"
1020 source "arch/arm/mach-vexpress/Kconfig"
1021 source "arch/arm/plat-versatile/Kconfig"
1023 source "arch/arm/mach-virt/Kconfig"
1025 source "arch/arm/mach-vt8500/Kconfig"
1027 source "arch/arm/mach-w90x900/Kconfig"
1029 source "arch/arm/mach-zynq/Kconfig"
1031 # Definitions to make life easier
1037 select GENERIC_CLOCKEVENTS
1043 select GENERIC_IRQ_CHIP
1046 config PLAT_ORION_LEGACY
1053 config PLAT_VERSATILE
1056 config ARM_TIMER_SP804
1059 select CLKSRC_OF if OF
1061 source arch/arm/mm/Kconfig
1065 default 16 if ARCH_EP93XX
1069 bool "Enable iWMMXt support" if !CPU_PJ4
1070 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1071 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1073 Enable support for iWMMXt context switching at run time if
1074 running on a CPU that supports it.
1078 depends on CPU_XSCALE
1081 config MULTI_IRQ_HANDLER
1084 Allow each machine to specify it's own IRQ handler at run time.
1087 source "arch/arm/Kconfig-nommu"
1090 config PJ4B_ERRATA_4742
1091 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1092 depends on CPU_PJ4B && MACH_ARMADA_370
1095 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1096 Event (WFE) IDLE states, a specific timing sensitivity exists between
1097 the retiring WFI/WFE instructions and the newly issued subsequent
1098 instructions. This sensitivity can result in a CPU hang scenario.
1100 The software must insert either a Data Synchronization Barrier (DSB)
1101 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1104 config ARM_ERRATA_326103
1105 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1108 Executing a SWP instruction to read-only memory does not set bit 11
1109 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1110 treat the access as a read, preventing a COW from occurring and
1111 causing the faulting task to livelock.
1113 config ARM_ERRATA_411920
1114 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1115 depends on CPU_V6 || CPU_V6K
1117 Invalidation of the Instruction Cache operation can
1118 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1119 It does not affect the MPCore. This option enables the ARM Ltd.
1120 recommended workaround.
1122 config ARM_ERRATA_430973
1123 bool "ARM errata: Stale prediction on replaced interworking branch"
1126 This option enables the workaround for the 430973 Cortex-A8
1127 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1128 interworking branch is replaced with another code sequence at the
1129 same virtual address, whether due to self-modifying code or virtual
1130 to physical address re-mapping, Cortex-A8 does not recover from the
1131 stale interworking branch prediction. This results in Cortex-A8
1132 executing the new code sequence in the incorrect ARM or Thumb state.
1133 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1134 and also flushes the branch target cache at every context switch.
1135 Note that setting specific bits in the ACTLR register may not be
1136 available in non-secure mode.
1138 config ARM_ERRATA_458693
1139 bool "ARM errata: Processor deadlock when a false hazard is created"
1141 depends on !ARCH_MULTIPLATFORM
1143 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1144 erratum. For very specific sequences of memory operations, it is
1145 possible for a hazard condition intended for a cache line to instead
1146 be incorrectly associated with a different cache line. This false
1147 hazard might then cause a processor deadlock. The workaround enables
1148 the L1 caching of the NEON accesses and disables the PLD instruction
1149 in the ACTLR register. Note that setting specific bits in the ACTLR
1150 register may not be available in non-secure mode.
1152 config ARM_ERRATA_460075
1153 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1155 depends on !ARCH_MULTIPLATFORM
1157 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1158 erratum. Any asynchronous access to the L2 cache may encounter a
1159 situation in which recent store transactions to the L2 cache are lost
1160 and overwritten with stale memory contents from external memory. The
1161 workaround disables the write-allocate mode for the L2 cache via the
1162 ACTLR register. Note that setting specific bits in the ACTLR register
1163 may not be available in non-secure mode.
1165 config ARM_ERRATA_742230
1166 bool "ARM errata: DMB operation may be faulty"
1167 depends on CPU_V7 && SMP
1168 depends on !ARCH_MULTIPLATFORM
1170 This option enables the workaround for the 742230 Cortex-A9
1171 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1172 between two write operations may not ensure the correct visibility
1173 ordering of the two writes. This workaround sets a specific bit in
1174 the diagnostic register of the Cortex-A9 which causes the DMB
1175 instruction to behave as a DSB, ensuring the correct behaviour of
1178 config ARM_ERRATA_742231
1179 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1180 depends on CPU_V7 && SMP
1181 depends on !ARCH_MULTIPLATFORM
1183 This option enables the workaround for the 742231 Cortex-A9
1184 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1185 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1186 accessing some data located in the same cache line, may get corrupted
1187 data due to bad handling of the address hazard when the line gets
1188 replaced from one of the CPUs at the same time as another CPU is
1189 accessing it. This workaround sets specific bits in the diagnostic
1190 register of the Cortex-A9 which reduces the linefill issuing
1191 capabilities of the processor.
1193 config PL310_ERRATA_588369
1194 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1195 depends on CACHE_L2X0
1197 The PL310 L2 cache controller implements three types of Clean &
1198 Invalidate maintenance operations: by Physical Address
1199 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1200 They are architecturally defined to behave as the execution of a
1201 clean operation followed immediately by an invalidate operation,
1202 both performing to the same memory location. This functionality
1203 is not correctly implemented in PL310 as clean lines are not
1204 invalidated as a result of these operations.
1206 config ARM_ERRATA_643719
1207 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1208 depends on CPU_V7 && SMP
1210 This option enables the workaround for the 643719 Cortex-A9 (prior to
1211 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1212 register returns zero when it should return one. The workaround
1213 corrects this value, ensuring cache maintenance operations which use
1214 it behave as intended and avoiding data corruption.
1216 config ARM_ERRATA_720789
1217 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1220 This option enables the workaround for the 720789 Cortex-A9 (prior to
1221 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1222 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1223 As a consequence of this erratum, some TLB entries which should be
1224 invalidated are not, resulting in an incoherency in the system page
1225 tables. The workaround changes the TLB flushing routines to invalidate
1226 entries regardless of the ASID.
1228 config PL310_ERRATA_727915
1229 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1230 depends on CACHE_L2X0
1232 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1233 operation (offset 0x7FC). This operation runs in background so that
1234 PL310 can handle normal accesses while it is in progress. Under very
1235 rare circumstances, due to this erratum, write data can be lost when
1236 PL310 treats a cacheable write transaction during a Clean &
1237 Invalidate by Way operation.
1239 config ARM_ERRATA_743622
1240 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1242 depends on !ARCH_MULTIPLATFORM
1244 This option enables the workaround for the 743622 Cortex-A9
1245 (r2p*) erratum. Under very rare conditions, a faulty
1246 optimisation in the Cortex-A9 Store Buffer may lead to data
1247 corruption. This workaround sets a specific bit in the diagnostic
1248 register of the Cortex-A9 which disables the Store Buffer
1249 optimisation, preventing the defect from occurring. This has no
1250 visible impact on the overall performance or power consumption of the
1253 config ARM_ERRATA_751472
1254 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1256 depends on !ARCH_MULTIPLATFORM
1258 This option enables the workaround for the 751472 Cortex-A9 (prior
1259 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1260 completion of a following broadcasted operation if the second
1261 operation is received by a CPU before the ICIALLUIS has completed,
1262 potentially leading to corrupted entries in the cache or TLB.
1264 config PL310_ERRATA_753970
1265 bool "PL310 errata: cache sync operation may be faulty"
1266 depends on CACHE_PL310
1268 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1270 Under some condition the effect of cache sync operation on
1271 the store buffer still remains when the operation completes.
1272 This means that the store buffer is always asked to drain and
1273 this prevents it from merging any further writes. The workaround
1274 is to replace the normal offset of cache sync operation (0x730)
1275 by another offset targeting an unmapped PL310 register 0x740.
1276 This has the same effect as the cache sync operation: store buffer
1277 drain and waiting for all buffers empty.
1279 config ARM_ERRATA_754322
1280 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1283 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1284 r3p*) erratum. A speculative memory access may cause a page table walk
1285 which starts prior to an ASID switch but completes afterwards. This
1286 can populate the micro-TLB with a stale entry which may be hit with
1287 the new ASID. This workaround places two dsb instructions in the mm
1288 switching code so that no page table walks can cross the ASID switch.
1290 config ARM_ERRATA_754327
1291 bool "ARM errata: no automatic Store Buffer drain"
1292 depends on CPU_V7 && SMP
1294 This option enables the workaround for the 754327 Cortex-A9 (prior to
1295 r2p0) erratum. The Store Buffer does not have any automatic draining
1296 mechanism and therefore a livelock may occur if an external agent
1297 continuously polls a memory location waiting to observe an update.
1298 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1299 written polling loops from denying visibility of updates to memory.
1301 config ARM_ERRATA_364296
1302 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1303 depends on CPU_V6 && !SMP
1305 This options enables the workaround for the 364296 ARM1136
1306 r0p2 erratum (possible cache data corruption with
1307 hit-under-miss enabled). It sets the undocumented bit 31 in
1308 the auxiliary control register and the FI bit in the control
1309 register, thus disabling hit-under-miss without putting the
1310 processor into full low interrupt latency mode. ARM11MPCore
1313 config ARM_ERRATA_764369
1314 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1315 depends on CPU_V7 && SMP
1317 This option enables the workaround for erratum 764369
1318 affecting Cortex-A9 MPCore with two or more processors (all
1319 current revisions). Under certain timing circumstances, a data
1320 cache line maintenance operation by MVA targeting an Inner
1321 Shareable memory region may fail to proceed up to either the
1322 Point of Coherency or to the Point of Unification of the
1323 system. This workaround adds a DSB instruction before the
1324 relevant cache maintenance functions and sets a specific bit
1325 in the diagnostic control register of the SCU.
1327 config PL310_ERRATA_769419
1328 bool "PL310 errata: no automatic Store Buffer drain"
1329 depends on CACHE_L2X0
1331 On revisions of the PL310 prior to r3p2, the Store Buffer does
1332 not automatically drain. This can cause normal, non-cacheable
1333 writes to be retained when the memory system is idle, leading
1334 to suboptimal I/O performance for drivers using coherent DMA.
1335 This option adds a write barrier to the cpu_idle loop so that,
1336 on systems with an outer cache, the store buffer is drained
1339 config ARM_ERRATA_775420
1340 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1343 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1344 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1345 operation aborts with MMU exception, it might cause the processor
1346 to deadlock. This workaround puts DSB before executing ISB if
1347 an abort may occur on cache maintenance.
1349 config ARM_ERRATA_798181
1350 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1351 depends on CPU_V7 && SMP
1353 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1354 adequately shooting down all use of the old entries. This
1355 option enables the Linux kernel workaround for this erratum
1356 which sends an IPI to the CPUs that are running the same ASID
1357 as the one being invalidated.
1361 source "arch/arm/common/Kconfig"
1371 Find out whether you have ISA slots on your motherboard. ISA is the
1372 name of a bus system, i.e. the way the CPU talks to the other stuff
1373 inside your box. Other bus systems are PCI, EISA, MicroChannel
1374 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1375 newer boards don't support it. If you have ISA, say Y, otherwise N.
1377 # Select ISA DMA controller support
1382 # Select ISA DMA interface
1387 bool "PCI support" if MIGHT_HAVE_PCI
1389 Find out whether you have a PCI motherboard. PCI is the name of a
1390 bus system, i.e. the way the CPU talks to the other stuff inside
1391 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1392 VESA. If you have PCI, say Y, otherwise N.
1398 config PCI_NANOENGINE
1399 bool "BSE nanoEngine PCI support"
1400 depends on SA1100_NANOENGINE
1402 Enable PCI on the BSE nanoEngine board.
1407 # Select the host bridge type
1408 config PCI_HOST_VIA82C505
1410 depends on PCI && ARCH_SHARK
1413 config PCI_HOST_ITE8152
1415 depends on PCI && MACH_ARMCORE
1419 source "drivers/pci/Kconfig"
1421 source "drivers/pcmcia/Kconfig"
1425 menu "Kernel Features"
1430 This option should be selected by machines which have an SMP-
1433 The only effect of this option is to make the SMP-related
1434 options available to the user for configuration.
1437 bool "Symmetric Multi-Processing"
1438 depends on CPU_V6K || CPU_V7
1439 depends on GENERIC_CLOCKEVENTS
1442 select USE_GENERIC_SMP_HELPERS
1444 This enables support for systems with more than one CPU. If you have
1445 a system with only one CPU, like most personal computers, say N. If
1446 you have a system with more than one CPU, say Y.
1448 If you say N here, the kernel will run on single and multiprocessor
1449 machines, but will use only one CPU of a multiprocessor machine. If
1450 you say Y here, the kernel will run on many, but not all, single
1451 processor machines. On a single processor machine, the kernel will
1452 run faster if you say N here.
1454 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1455 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1456 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1458 If you don't know what to do here, say N.
1461 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1462 depends on SMP && !XIP_KERNEL
1465 SMP kernels contain instructions which fail on non-SMP processors.
1466 Enabling this option allows the kernel to modify itself to make
1467 these instructions safe. Disabling it allows about 1K of space
1470 If you don't know what to do here, say Y.
1472 config ARM_CPU_TOPOLOGY
1473 bool "Support cpu topology definition"
1474 depends on SMP && CPU_V7
1477 Support ARM cpu topology definition. The MPIDR register defines
1478 affinity between processors which is then used to describe the cpu
1479 topology of an ARM System.
1482 bool "Multi-core scheduler support"
1483 depends on ARM_CPU_TOPOLOGY
1485 Multi-core scheduler support improves the CPU scheduler's decision
1486 making when dealing with multi-core CPU chips at a cost of slightly
1487 increased overhead in some places. If unsure say N here.
1490 bool "SMT scheduler support"
1491 depends on ARM_CPU_TOPOLOGY
1493 Improves the CPU scheduler's decision making when dealing with
1494 MultiThreading at a cost of slightly increased overhead in some
1495 places. If unsure say N here.
1497 config DISABLE_CPU_SCHED_DOMAIN_BALANCE
1498 bool "(EXPERIMENTAL) Disable CPU level scheduler load-balancing"
1500 Disables scheduler load-balancing at CPU sched domain level.
1503 bool "(EXPERIMENTAL) Heterogenous multiprocessor scheduling"
1504 depends on DISABLE_CPU_SCHED_DOMAIN_BALANCE && SCHED_MC && FAIR_GROUP_SCHED && !SCHED_AUTOGROUP
1506 Experimental scheduler optimizations for heterogeneous platforms.
1507 Attempts to introspectively select task affinity to optimize power
1508 and performance. Basic support for multiple (>2) cpu types is in place,
1509 but it has only been tested with two types of cpus.
1510 There is currently no support for migration of task groups, hence
1511 !SCHED_AUTOGROUP. Furthermore, normal load-balancing must be disabled
1512 between cpus of different type (DISABLE_CPU_SCHED_DOMAIN_BALANCE).
1514 config SCHED_HMP_PRIO_FILTER
1515 bool "(EXPERIMENTAL) Filter HMP migrations by task priority"
1516 depends on SCHED_HMP
1519 Enables task priority based HMP migration filter. Any task with
1520 a NICE value above the threshold will always be on low-power cpus
1521 with less compute capacity.
1523 config SCHED_HMP_PRIO_FILTER_VAL
1524 int "NICE priority threshold"
1526 depends on SCHED_HMP_PRIO_FILTER
1528 config HMP_FAST_CPU_MASK
1529 string "HMP scheduler fast CPU mask"
1530 depends on SCHED_HMP
1532 Leave empty to use device tree information.
1533 Specify the cpuids of the fast CPUs in the system as a list string,
1534 e.g. cpuid 0+1 should be specified as 0-1.
1536 config HMP_SLOW_CPU_MASK
1537 string "HMP scheduler slow CPU mask"
1538 depends on SCHED_HMP
1540 Leave empty to use device tree information.
1541 Specify the cpuids of the slow CPUs in the system as a list string,
1542 e.g. cpuid 0+1 should be specified as 0-1.
1547 This option enables support for the ARM system coherency unit
1549 config HAVE_ARM_ARCH_TIMER
1550 bool "Architected timer support"
1552 select ARM_ARCH_TIMER
1554 This option enables support for the ARM architected timer
1559 select CLKSRC_OF if OF
1561 This options enables support for the ARM timer and watchdog unit
1564 bool "Multi-Cluster Power Management"
1565 depends on CPU_V7 && SMP
1567 This option provides the common power management infrastructure
1568 for (multi-)cluster based systems, such as big.LITTLE based
1572 prompt "Memory split"
1575 Select the desired split between kernel and user memory.
1577 If you are not absolutely sure what you are doing, leave this
1581 bool "3G/1G user/kernel split"
1583 bool "2G/2G user/kernel split"
1585 bool "1G/3G user/kernel split"
1590 default 0x40000000 if VMSPLIT_1G
1591 default 0x80000000 if VMSPLIT_2G
1595 int "Maximum number of CPUs (2-32)"
1601 bool "Support for hot-pluggable CPUs"
1602 depends on SMP && HOTPLUG
1604 Say Y here to experiment with turning CPUs off and on. CPUs
1605 can be controlled through /sys/devices/system/cpu.
1608 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1611 Say Y here if you want Linux to communicate with system firmware
1612 implementing the PSCI specification for CPU-centric power
1613 management operations described in ARM document number ARM DEN
1614 0022A ("Power State Coordination Interface System Software on
1618 bool "Use local timer interrupts"
1622 Enable support for local timers on SMP platforms, rather then the
1623 legacy IPI broadcast method. Local timers allows the system
1624 accounting to be spread across the timer interval, preventing a
1625 "thundering herd" at every timer tick.
1627 # The GPIO number here must be sorted by descending number. In case of
1628 # a multiplatform kernel, we just want the highest value required by the
1629 # selected platforms.
1632 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1633 default 512 if SOC_OMAP5
1634 default 392 if ARCH_U8500
1635 default 352 if ARCH_VT8500
1636 default 288 if ARCH_SUNXI
1637 default 264 if MACH_H4700
1640 Maximum number of GPIOs in the system.
1642 If unsure, leave the default value.
1644 source kernel/Kconfig.preempt
1648 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1649 ARCH_S5PV210 || ARCH_EXYNOS4
1650 default AT91_TIMER_HZ if ARCH_AT91
1651 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1655 def_bool HIGH_RES_TIMERS
1657 config THUMB2_KERNEL
1658 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1659 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1660 default y if CPU_THUMBONLY
1662 select ARM_ASM_UNIFIED
1665 By enabling this option, the kernel will be compiled in
1666 Thumb-2 mode. A compiler/assembler that understand the unified
1667 ARM-Thumb syntax is needed.
1671 config THUMB2_AVOID_R_ARM_THM_JUMP11
1672 bool "Work around buggy Thumb-2 short branch relocations in gas"
1673 depends on THUMB2_KERNEL && MODULES
1676 Various binutils versions can resolve Thumb-2 branches to
1677 locally-defined, preemptible global symbols as short-range "b.n"
1678 branch instructions.
1680 This is a problem, because there's no guarantee the final
1681 destination of the symbol, or any candidate locations for a
1682 trampoline, are within range of the branch. For this reason, the
1683 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1684 relocation in modules at all, and it makes little sense to add
1687 The symptom is that the kernel fails with an "unsupported
1688 relocation" error when loading some modules.
1690 Until fixed tools are available, passing
1691 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1692 code which hits this problem, at the cost of a bit of extra runtime
1693 stack usage in some cases.
1695 The problem is described in more detail at:
1696 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1698 Only Thumb-2 kernels are affected.
1700 Unless you are sure your tools don't have this problem, say Y.
1702 config ARM_ASM_UNIFIED
1706 bool "Use the ARM EABI to compile the kernel"
1708 This option allows for the kernel to be compiled using the latest
1709 ARM ABI (aka EABI). This is only useful if you are using a user
1710 space environment that is also compiled with EABI.
1712 Since there are major incompatibilities between the legacy ABI and
1713 EABI, especially with regard to structure member alignment, this
1714 option also changes the kernel syscall calling convention to
1715 disambiguate both ABIs and allow for backward compatibility support
1716 (selected with CONFIG_OABI_COMPAT).
1718 To use this you need GCC version 4.0.0 or later.
1721 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1722 depends on AEABI && !THUMB2_KERNEL
1725 This option preserves the old syscall interface along with the
1726 new (ARM EABI) one. It also provides a compatibility layer to
1727 intercept syscalls that have structure arguments which layout
1728 in memory differs between the legacy ABI and the new ARM EABI
1729 (only for non "thumb" binaries). This option adds a tiny
1730 overhead to all syscalls and produces a slightly larger kernel.
1731 If you know you'll be using only pure EABI user space then you
1732 can say N here. If this option is not selected and you attempt
1733 to execute a legacy ABI binary then the result will be
1734 UNPREDICTABLE (in fact it can be predicted that it won't work
1735 at all). If in doubt say Y.
1737 config ARCH_HAS_HOLES_MEMORYMODEL
1740 config ARCH_SPARSEMEM_ENABLE
1743 config ARCH_SPARSEMEM_DEFAULT
1744 def_bool ARCH_SPARSEMEM_ENABLE
1746 config ARCH_SELECT_MEMORY_MODEL
1747 def_bool ARCH_SPARSEMEM_ENABLE
1749 config HAVE_ARCH_PFN_VALID
1750 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1753 bool "High Memory Support"
1756 The address space of ARM processors is only 4 Gigabytes large
1757 and it has to accommodate user address space, kernel address
1758 space as well as some memory mapped IO. That means that, if you
1759 have a large amount of physical memory and/or IO, not all of the
1760 memory can be "permanently mapped" by the kernel. The physical
1761 memory that is not permanently mapped is called "high memory".
1763 Depending on the selected kernel/user memory split, minimum
1764 vmalloc space and actual amount of RAM, you may not need this
1765 option which should result in a slightly faster kernel.
1770 bool "Allocate 2nd-level pagetables from highmem"
1773 config HW_PERF_EVENTS
1774 bool "Enable hardware performance counter support for perf events"
1775 depends on PERF_EVENTS
1778 Enable hardware performance counter support for perf events. If
1779 disabled, perf events will use software events only.
1783 config FORCE_MAX_ZONEORDER
1784 int "Maximum zone order" if ARCH_SHMOBILE
1785 range 11 64 if ARCH_SHMOBILE
1786 default "12" if SOC_AM33XX
1787 default "9" if SA1111
1790 The kernel memory allocator divides physically contiguous memory
1791 blocks into "zones", where each zone is a power of two number of
1792 pages. This option selects the largest power of two that the kernel
1793 keeps in the memory allocator. If you need to allocate very large
1794 blocks of physically contiguous memory, then you may need to
1795 increase this value.
1797 This config option is actually maximum order plus one. For example,
1798 a value of 11 means that the largest free memory block is 2^10 pages.
1800 config ALIGNMENT_TRAP
1802 depends on CPU_CP15_MMU
1803 default y if !ARCH_EBSA110
1804 select HAVE_PROC_CPU if PROC_FS
1806 ARM processors cannot fetch/store information which is not
1807 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1808 address divisible by 4. On 32-bit ARM processors, these non-aligned
1809 fetch/store instructions will be emulated in software if you say
1810 here, which has a severe performance impact. This is necessary for
1811 correct operation of some network protocols. With an IP-only
1812 configuration it is safe to say N, otherwise say Y.
1814 config UACCESS_WITH_MEMCPY
1815 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1817 default y if CPU_FEROCEON
1819 Implement faster copy_to_user and clear_user methods for CPU
1820 cores where a 8-word STM instruction give significantly higher
1821 memory write throughput than a sequence of individual 32bit stores.
1823 A possible side effect is a slight increase in scheduling latency
1824 between threads sharing the same address space if they invoke
1825 such copy operations with large buffers.
1827 However, if the CPU data cache is using a write-allocate mode,
1828 this option is unlikely to provide any performance gain.
1832 prompt "Enable seccomp to safely compute untrusted bytecode"
1834 This kernel feature is useful for number crunching applications
1835 that may need to compute untrusted bytecode during their
1836 execution. By using pipes or other transports made available to
1837 the process as file descriptors supporting the read/write
1838 syscalls, it's possible to isolate those applications in
1839 their own address space using seccomp. Once seccomp is
1840 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1841 and the task is only allowed to execute a few safe syscalls
1842 defined by each seccomp mode.
1844 config CC_STACKPROTECTOR
1845 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1847 This option turns on the -fstack-protector GCC feature. This
1848 feature puts, at the beginning of functions, a canary value on
1849 the stack just before the return address, and validates
1850 the value just before actually returning. Stack based buffer
1851 overflows (that need to overwrite this return address) now also
1852 overwrite the canary, which gets detected and the attack is then
1853 neutralized via a kernel panic.
1854 This feature requires gcc version 4.2 or above.
1861 bool "Xen guest support on ARM (EXPERIMENTAL)"
1862 depends on ARM && AEABI && OF
1863 depends on CPU_V7 && !CPU_V6
1864 depends on !GENERIC_ATOMIC64
1867 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1874 bool "Flattened Device Tree support"
1877 select OF_EARLY_FLATTREE
1879 Include support for flattened device tree machine descriptions.
1882 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1885 This is the traditional way of passing data to the kernel at boot
1886 time. If you are solely relying on the flattened device tree (or
1887 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1888 to remove ATAGS support from your kernel binary. If unsure,
1891 config DEPRECATED_PARAM_STRUCT
1892 bool "Provide old way to pass kernel parameters"
1895 This was deprecated in 2001 and announced to live on for 5 years.
1896 Some old boot loaders still use this way.
1898 # Compressed boot loader in ROM. Yes, we really want to ask about
1899 # TEXT and BSS so we preserve their values in the config files.
1900 config ZBOOT_ROM_TEXT
1901 hex "Compressed ROM boot loader base address"
1904 The physical address at which the ROM-able zImage is to be
1905 placed in the target. Platforms which normally make use of
1906 ROM-able zImage formats normally set this to a suitable
1907 value in their defconfig file.
1909 If ZBOOT_ROM is not enabled, this has no effect.
1911 config ZBOOT_ROM_BSS
1912 hex "Compressed ROM boot loader BSS address"
1915 The base address of an area of read/write memory in the target
1916 for the ROM-able zImage which must be available while the
1917 decompressor is running. It must be large enough to hold the
1918 entire decompressed kernel plus an additional 128 KiB.
1919 Platforms which normally make use of ROM-able zImage formats
1920 normally set this to a suitable value in their defconfig file.
1922 If ZBOOT_ROM is not enabled, this has no effect.
1925 bool "Compressed boot loader in ROM/flash"
1926 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1928 Say Y here if you intend to execute your compressed kernel image
1929 (zImage) directly from ROM or flash. If unsure, say N.
1932 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1933 depends on ZBOOT_ROM && ARCH_SH7372
1934 default ZBOOT_ROM_NONE
1936 Include experimental SD/MMC loading code in the ROM-able zImage.
1937 With this enabled it is possible to write the ROM-able zImage
1938 kernel image to an MMC or SD card and boot the kernel straight
1939 from the reset vector. At reset the processor Mask ROM will load
1940 the first part of the ROM-able zImage which in turn loads the
1941 rest the kernel image to RAM.
1943 config ZBOOT_ROM_NONE
1944 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1946 Do not load image from SD or MMC
1948 config ZBOOT_ROM_MMCIF
1949 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1951 Load image from MMCIF hardware block.
1953 config ZBOOT_ROM_SH_MOBILE_SDHI
1954 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1956 Load image from SDHI hardware block
1960 config ARM_APPENDED_DTB
1961 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1962 depends on OF && !ZBOOT_ROM
1964 With this option, the boot code will look for a device tree binary
1965 (DTB) appended to zImage
1966 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1968 This is meant as a backward compatibility convenience for those
1969 systems with a bootloader that can't be upgraded to accommodate
1970 the documented boot protocol using a device tree.
1972 Beware that there is very little in terms of protection against
1973 this option being confused by leftover garbage in memory that might
1974 look like a DTB header after a reboot if no actual DTB is appended
1975 to zImage. Do not leave this option active in a production kernel
1976 if you don't intend to always append a DTB. Proper passing of the
1977 location into r2 of a bootloader provided DTB is always preferable
1980 config ARM_ATAG_DTB_COMPAT
1981 bool "Supplement the appended DTB with traditional ATAG information"
1982 depends on ARM_APPENDED_DTB
1984 Some old bootloaders can't be updated to a DTB capable one, yet
1985 they provide ATAGs with memory configuration, the ramdisk address,
1986 the kernel cmdline string, etc. Such information is dynamically
1987 provided by the bootloader and can't always be stored in a static
1988 DTB. To allow a device tree enabled kernel to be used with such
1989 bootloaders, this option allows zImage to extract the information
1990 from the ATAG list and store it at run time into the appended DTB.
1993 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1994 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1996 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1997 bool "Use bootloader kernel arguments if available"
1999 Uses the command-line options passed by the boot loader instead of
2000 the device tree bootargs property. If the boot loader doesn't provide
2001 any, the device tree bootargs property will be used.
2003 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2004 bool "Extend with bootloader kernel arguments"
2006 The command-line arguments provided by the boot loader will be
2007 appended to the the device tree bootargs property.
2012 string "Default kernel command string"
2015 On some architectures (EBSA110 and CATS), there is currently no way
2016 for the boot loader to pass arguments to the kernel. For these
2017 architectures, you should supply some command-line options at build
2018 time by entering them here. As a minimum, you should specify the
2019 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2022 prompt "Kernel command line type" if CMDLINE != ""
2023 default CMDLINE_FROM_BOOTLOADER
2026 config CMDLINE_FROM_BOOTLOADER
2027 bool "Use bootloader kernel arguments if available"
2029 Uses the command-line options passed by the boot loader. If
2030 the boot loader doesn't provide any, the default kernel command
2031 string provided in CMDLINE will be used.
2033 config CMDLINE_EXTEND
2034 bool "Extend bootloader kernel arguments"
2036 The command-line arguments provided by the boot loader will be
2037 appended to the default kernel command string.
2039 config CMDLINE_FORCE
2040 bool "Always use the default kernel command string"
2042 Always use the default kernel command string, even if the boot
2043 loader passes other arguments to the kernel.
2044 This is useful if you cannot or don't want to change the
2045 command-line options your boot loader passes to the kernel.
2049 bool "Kernel Execute-In-Place from ROM"
2050 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2052 Execute-In-Place allows the kernel to run from non-volatile storage
2053 directly addressable by the CPU, such as NOR flash. This saves RAM
2054 space since the text section of the kernel is not loaded from flash
2055 to RAM. Read-write sections, such as the data section and stack,
2056 are still copied to RAM. The XIP kernel is not compressed since
2057 it has to run directly from flash, so it will take more space to
2058 store it. The flash address used to link the kernel object files,
2059 and for storing it, is configuration dependent. Therefore, if you
2060 say Y here, you must know the proper physical address where to
2061 store the kernel image depending on your own flash memory usage.
2063 Also note that the make target becomes "make xipImage" rather than
2064 "make zImage" or "make Image". The final kernel binary to put in
2065 ROM memory will be arch/arm/boot/xipImage.
2069 config XIP_PHYS_ADDR
2070 hex "XIP Kernel Physical Location"
2071 depends on XIP_KERNEL
2072 default "0x00080000"
2074 This is the physical address in your flash memory the kernel will
2075 be linked for and stored to. This address is dependent on your
2079 bool "Kexec system call (EXPERIMENTAL)"
2080 depends on (!SMP || PM_SLEEP_SMP)
2082 kexec is a system call that implements the ability to shutdown your
2083 current kernel, and to start another kernel. It is like a reboot
2084 but it is independent of the system firmware. And like a reboot
2085 you can start any kernel with it, not just Linux.
2087 It is an ongoing process to be certain the hardware in a machine
2088 is properly shutdown, so do not be surprised if this code does not
2089 initially work for you. It may help to enable device hotplugging
2093 bool "Export atags in procfs"
2094 depends on ATAGS && KEXEC
2097 Should the atags used to boot the kernel be exported in an "atags"
2098 file in procfs. Useful with kexec.
2101 bool "Build kdump crash kernel (EXPERIMENTAL)"
2103 Generate crash dump after being started by kexec. This should
2104 be normally only set in special crash dump kernels which are
2105 loaded in the main kernel with kexec-tools into a specially
2106 reserved region and then later executed after a crash by
2107 kdump/kexec. The crash dump kernel must be compiled to a
2108 memory address not used by the main kernel
2110 For more details see Documentation/kdump/kdump.txt
2112 config AUTO_ZRELADDR
2113 bool "Auto calculation of the decompressed kernel image address"
2114 depends on !ZBOOT_ROM && !ARCH_U300
2116 ZRELADDR is the physical address where the decompressed kernel
2117 image will be placed. If AUTO_ZRELADDR is selected, the address
2118 will be determined at run-time by masking the current IP with
2119 0xf8000000. This assumes the zImage being placed in the first 128MB
2120 from start of memory.
2124 menu "CPU Power Management"
2127 source "drivers/cpufreq/Kconfig"
2132 Internal configuration node for common cpufreq on Samsung SoC
2134 config CPU_FREQ_S3C24XX
2135 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2136 depends on ARCH_S3C24XX && CPU_FREQ
2139 This enables the CPUfreq driver for the Samsung S3C24XX family
2142 For details, take a look at <file:Documentation/cpu-freq>.
2146 config CPU_FREQ_S3C24XX_PLL
2147 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2148 depends on CPU_FREQ_S3C24XX
2150 Compile in support for changing the PLL frequency from the
2151 S3C24XX series CPUfreq driver. The PLL takes time to settle
2152 after a frequency change, so by default it is not enabled.
2154 This also means that the PLL tables for the selected CPU(s) will
2155 be built which may increase the size of the kernel image.
2157 config CPU_FREQ_S3C24XX_DEBUG
2158 bool "Debug CPUfreq Samsung driver core"
2159 depends on CPU_FREQ_S3C24XX
2161 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2163 config CPU_FREQ_S3C24XX_IODEBUG
2164 bool "Debug CPUfreq Samsung driver IO timing"
2165 depends on CPU_FREQ_S3C24XX
2167 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2169 config CPU_FREQ_S3C24XX_DEBUGFS
2170 bool "Export debugfs for CPUFreq"
2171 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2173 Export status information via debugfs.
2177 source "drivers/cpuidle/Kconfig"
2181 menu "Floating point emulation"
2183 comment "At least one emulation must be selected"
2186 bool "NWFPE math emulation"
2187 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2189 Say Y to include the NWFPE floating point emulator in the kernel.
2190 This is necessary to run most binaries. Linux does not currently
2191 support floating point hardware so you need to say Y here even if
2192 your machine has an FPA or floating point co-processor podule.
2194 You may say N here if you are going to load the Acorn FPEmulator
2195 early in the bootup.
2198 bool "Support extended precision"
2199 depends on FPE_NWFPE
2201 Say Y to include 80-bit support in the kernel floating-point
2202 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2203 Note that gcc does not generate 80-bit operations by default,
2204 so in most cases this option only enlarges the size of the
2205 floating point emulator without any good reason.
2207 You almost surely want to say N here.
2210 bool "FastFPE math emulation (EXPERIMENTAL)"
2211 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2213 Say Y here to include the FAST floating point emulator in the kernel.
2214 This is an experimental much faster emulator which now also has full
2215 precision for the mantissa. It does not support any exceptions.
2216 It is very simple, and approximately 3-6 times faster than NWFPE.
2218 It should be sufficient for most programs. It may be not suitable
2219 for scientific calculations, but you have to check this for yourself.
2220 If you do not feel you need a faster FP emulation you should better
2224 bool "VFP-format floating point maths"
2225 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2227 Say Y to include VFP support code in the kernel. This is needed
2228 if your hardware includes a VFP unit.
2230 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2231 release notes and additional status information.
2233 Say N if your target does not have VFP hardware.
2241 bool "Advanced SIMD (NEON) Extension support"
2242 depends on VFPv3 && CPU_V7
2244 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2249 menu "Userspace binary formats"
2251 source "fs/Kconfig.binfmt"
2254 tristate "RISC OS personality"
2257 Say Y here to include the kernel code necessary if you want to run
2258 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2259 experimental; if this sounds frightening, say N and sleep in peace.
2260 You can also say M here to compile this support as a module (which
2261 will be called arthur).
2265 menu "Power management options"
2267 source "kernel/power/Kconfig"
2269 config ARCH_SUSPEND_POSSIBLE
2270 depends on !ARCH_S5PC100
2271 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2272 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2275 config ARM_CPU_SUSPEND
2280 source "net/Kconfig"
2282 source "drivers/Kconfig"
2286 source "arch/arm/Kconfig.debug"
2288 source "security/Kconfig"
2290 source "crypto/Kconfig"
2292 source "lib/Kconfig"
2294 source "arch/arm/kvm/Kconfig"