2 # For a description of the syntax of this configuration file,
3 # see Documentation/kbuild/kconfig-language.txt.
6 mainmenu "Linux Kernel Configuration"
15 select SYS_SUPPORTS_APM_EMULATION
16 select GENERIC_ATOMIC64 if (!CPU_32v6K)
17 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
19 select HAVE_KPROBES if (!XIP_KERNEL)
20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_GENERIC_DMA_COHERENT
23 select HAVE_KERNEL_GZIP
24 select HAVE_KERNEL_LZO
25 select HAVE_KERNEL_LZMA
26 select HAVE_PERF_EVENTS
27 select PERF_USE_VMALLOC
28 select HAVE_REGS_AND_STACK_ACCESS_API
30 The ARM series is a line of low-power-consumption RISC chip designs
31 licensed by ARM Ltd and targeted at embedded applications and
32 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
33 manufactured, but legacy ARM-based PC hardware remains popular in
34 Europe. There is an ARM Linux project with a web page at
35 <http://www.arm.linux.org.uk/>.
40 config SYS_SUPPORTS_APM_EMULATION
43 config HAVE_SCHED_CLOCK
49 config ARCH_USES_GETTIMEOFFSET
53 config GENERIC_CLOCKEVENTS
56 config GENERIC_CLOCKEVENTS_BROADCAST
58 depends on GENERIC_CLOCKEVENTS
63 select GENERIC_ALLOCATOR
74 The Extended Industry Standard Architecture (EISA) bus was
75 developed as an open alternative to the IBM MicroChannel bus.
77 The EISA bus provided some of the features of the IBM MicroChannel
78 bus while maintaining backward compatibility with cards made for
79 the older ISA bus. The EISA bus saw limited use between 1988 and
80 1995 when it was made obsolete by the PCI bus.
82 Say Y here if you are building a kernel for an EISA-based machine.
92 MicroChannel Architecture is found in some IBM PS/2 machines and
93 laptops. It is a bus system similar to PCI or ISA. See
94 <file:Documentation/mca.txt> (and especially the web page given
95 there) before attempting to build an MCA bus kernel.
97 config GENERIC_HARDIRQS
101 config STACKTRACE_SUPPORT
105 config HAVE_LATENCYTOP_SUPPORT
110 config LOCKDEP_SUPPORT
114 config TRACE_IRQFLAGS_SUPPORT
118 config HARDIRQS_SW_RESEND
122 config GENERIC_IRQ_PROBE
126 config GENERIC_LOCKBREAK
129 depends on SMP && PREEMPT
131 config RWSEM_GENERIC_SPINLOCK
135 config RWSEM_XCHGADD_ALGORITHM
138 config ARCH_HAS_CPU_IDLE_WAIT
142 config ARCH_HAS_DEFAULT_IDLE
146 config ARCH_HAS_ILOG2_U32
149 config ARCH_HAS_ILOG2_U64
152 config ARCH_HAS_CPUFREQ
155 Internal node to signify that the ARCH has CPUFREQ support
156 and that the relevant menu configurations are displayed for
159 config GENERIC_HWEIGHT
163 config GENERIC_CALIBRATE_DELAY
167 config ARCH_MAY_HAVE_PC_FDC
173 config NEED_DMA_MAP_STATE
176 config GENERIC_ISA_DMA
185 config GENERIC_HARDIRQS_NO__DO_IRQ
188 config ARM_L1_CACHE_SHIFT_6
191 Setting ARM L1 cache line size to 64 Bytes.
193 config ARCH_PROVIDES_UDELAY
198 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
199 default DRAM_BASE if REMAP_VECTORS_TO_RAM
202 The base address of exception vectors.
204 source "init/Kconfig"
206 source "kernel/Kconfig.freezer"
211 bool "MMU-based Paged Memory Management Support"
214 Select if you want MMU-based virtualised addressing space
215 support by paged memory management. If unsure, say 'Y'.
218 # The "ARM system type" choice list is ordered alphabetically by option
219 # text. Please add new entries in the option alphabetic order.
222 prompt "ARM system type"
223 default ARCH_VERSATILE
226 bool "Agilent AAEC-2000 based"
230 select ARCH_USES_GETTIMEOFFSET
232 This enables support for systems based on the Agilent AAEC-2000
234 config ARCH_INTEGRATOR
235 bool "ARM Ltd. Integrator family"
237 select ARCH_HAS_CPUFREQ
240 select GENERIC_CLOCKEVENTS
241 select PLAT_VERSATILE
243 Support for ARM's Integrator platform.
246 bool "ARM Ltd. RealView family"
250 select GENERIC_CLOCKEVENTS
251 select ARCH_WANT_OPTIONAL_GPIOLIB
252 select PLAT_VERSATILE
253 select ARM_TIMER_SP804
254 select GPIO_PL061 if GPIOLIB
256 This enables support for ARM Ltd RealView boards.
258 config ARCH_VERSATILE
259 bool "ARM Ltd. Versatile family"
264 select GENERIC_CLOCKEVENTS
265 select ARCH_WANT_OPTIONAL_GPIOLIB
266 select PLAT_VERSATILE
267 select ARM_TIMER_SP804
269 This enables support for ARM Ltd Versatile board.
272 bool "ARM Ltd. Versatile Express family"
273 select ARCH_WANT_OPTIONAL_GPIOLIB
275 select ARM_TIMER_SP804
277 select GENERIC_CLOCKEVENTS
280 select PLAT_VERSATILE
282 This enables support for the ARM Ltd Versatile Express boards.
286 select ARCH_REQUIRE_GPIOLIB
289 This enables support for systems based on the Atmel AT91RM9200,
290 AT91SAM9 and AT91CAP9 processors.
293 bool "Broadcom BCMRING"
298 select GENERIC_CLOCKEVENTS
299 select ARCH_WANT_OPTIONAL_GPIOLIB
301 Support for Broadcom's BCMRing platform.
304 bool "Cirrus Logic CLPS711x/EP721x-based"
306 select ARCH_USES_GETTIMEOFFSET
308 Support for Cirrus Logic 711x/721x based boards.
311 bool "Cavium Networks CNS3XXX family"
313 select GENERIC_CLOCKEVENTS
315 select PCI_DOMAINS if PCI
317 Support for Cavium Networks CNS3XXX platform.
320 bool "Cortina Systems Gemini"
322 select ARCH_REQUIRE_GPIOLIB
323 select ARCH_USES_GETTIMEOFFSET
325 Support for the Cortina Systems Gemini family SoCs
332 select ARCH_USES_GETTIMEOFFSET
334 This is an evaluation board for the StrongARM processor available
335 from Digital. It has limited hardware on-board, including an
336 Ethernet interface, two PCMCIA sockets, two serial ports and a
345 select ARCH_REQUIRE_GPIOLIB
346 select ARCH_HAS_HOLES_MEMORYMODEL
347 select ARCH_USES_GETTIMEOFFSET
349 This enables support for the Cirrus EP93xx series of CPUs.
351 config ARCH_FOOTBRIDGE
355 select ARCH_USES_GETTIMEOFFSET
357 Support for systems based on the DC21285 companion chip
358 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
361 bool "Freescale MXC/iMX-based"
362 select GENERIC_CLOCKEVENTS
363 select ARCH_REQUIRE_GPIOLIB
366 Support for Freescale MXC/iMX-based family of processors
369 bool "Freescale STMP3xxx"
372 select ARCH_REQUIRE_GPIOLIB
373 select GENERIC_CLOCKEVENTS
374 select USB_ARCH_HAS_EHCI
376 Support for systems based on the Freescale 3xxx CPUs.
379 bool "Hilscher NetX based"
382 select GENERIC_CLOCKEVENTS
384 This enables support for systems based on the Hilscher NetX Soc
387 bool "Hynix HMS720x-based"
390 select ARCH_USES_GETTIMEOFFSET
392 This enables support for systems based on the Hynix HMS720x
400 select ARCH_SUPPORTS_MSI
403 Support for Intel's IOP13XX (XScale) family of processors.
411 select ARCH_REQUIRE_GPIOLIB
413 Support for Intel's 80219 and IOP32X (XScale) family of
422 select ARCH_REQUIRE_GPIOLIB
424 Support for Intel's IOP33X (XScale) family of processors.
431 select ARCH_USES_GETTIMEOFFSET
433 Support for Intel's IXP23xx (XScale) family of processors.
436 bool "IXP2400/2800-based"
440 select ARCH_USES_GETTIMEOFFSET
442 Support for Intel's IXP2400/2800 (XScale) family of processors.
449 select GENERIC_CLOCKEVENTS
450 select DMABOUNCE if PCI
452 Support for Intel's IXP4XX (XScale) family of processors.
457 select ARCH_REQUIRE_GPIOLIB
458 select GENERIC_CLOCKEVENTS
461 Support for the Marvell Dove SoC 88AP510
464 bool "Marvell Kirkwood"
467 select ARCH_REQUIRE_GPIOLIB
468 select GENERIC_CLOCKEVENTS
471 Support for the following Marvell Kirkwood series SoCs:
472 88F6180, 88F6192 and 88F6281.
475 bool "Marvell Loki (88RC8480)"
477 select GENERIC_CLOCKEVENTS
480 Support for the Marvell Loki (88RC8480) SoC.
485 select ARCH_REQUIRE_GPIOLIB
488 select USB_ARCH_HAS_OHCI
491 select GENERIC_CLOCKEVENTS
493 Support for the NXP LPC32XX family of processors
496 bool "Marvell MV78xx0"
499 select ARCH_REQUIRE_GPIOLIB
500 select GENERIC_CLOCKEVENTS
503 Support for the following Marvell MV78xx0 series SoCs:
511 select ARCH_REQUIRE_GPIOLIB
512 select GENERIC_CLOCKEVENTS
515 Support for the following Marvell Orion 5x series SoCs:
516 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
517 Orion-2 (5281), Orion-1-90 (6183).
520 bool "Marvell PXA168/910/MMP2"
522 select ARCH_REQUIRE_GPIOLIB
524 select GENERIC_CLOCKEVENTS
528 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
531 bool "Micrel/Kendin KS8695"
533 select ARCH_REQUIRE_GPIOLIB
534 select ARCH_USES_GETTIMEOFFSET
536 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
537 System-on-Chip devices.
540 bool "NetSilicon NS9xxx"
543 select GENERIC_CLOCKEVENTS
546 Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
549 <http://www.digi.com/products/microprocessors/index.jsp>
552 bool "Nuvoton W90X900 CPU"
554 select ARCH_REQUIRE_GPIOLIB
556 select GENERIC_CLOCKEVENTS
558 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
559 At present, the w90x900 has been renamed nuc900, regarding
560 the ARM series product line, you can login the following
561 link address to know more.
563 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
564 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
567 bool "Nuvoton NUC93X CPU"
571 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
572 low-power and high performance MPEG-4/JPEG multimedia controller chip.
577 select GENERIC_CLOCKEVENTS
581 select ARCH_HAS_BARRIERS if CACHE_L2X0
582 select ARCH_HAS_CPUFREQ
583 select ARCH_PROVIDES_UDELAY
586 This enables support for NVIDIA Tegra based systems (Tegra APX,
587 Tegra 6xx and Tegra 2 series).
590 bool "Philips Nexperia PNX4008 Mobile"
593 select ARCH_USES_GETTIMEOFFSET
595 This enables support for Philips PNX4008 mobile platform.
598 bool "PXA2xx/PXA3xx-based"
601 select ARCH_HAS_CPUFREQ
603 select ARCH_REQUIRE_GPIOLIB
604 select GENERIC_CLOCKEVENTS
608 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
613 select GENERIC_CLOCKEVENTS
614 select ARCH_REQUIRE_GPIOLIB
616 Support for Qualcomm MSM/QSD based systems. This runs on the
617 apps processor of the MSM/QSD and depends on a shared memory
618 interface to the modem processor which runs the baseband
619 stack and controls some vital subsystems
620 (clock and power control, etc).
623 bool "Renesas SH-Mobile"
625 Support for Renesas's SH-Mobile ARM platforms
632 select ARCH_MAY_HAVE_PC_FDC
633 select HAVE_PATA_PLATFORM
636 select ARCH_SPARSEMEM_ENABLE
637 select ARCH_USES_GETTIMEOFFSET
639 On the Acorn Risc-PC, Linux can support the internal IDE disk and
640 CD-ROM interface, serial and parallel port, and the floppy drive.
646 select ARCH_SPARSEMEM_ENABLE
648 select ARCH_HAS_CPUFREQ
650 select GENERIC_CLOCKEVENTS
653 select ARCH_REQUIRE_GPIOLIB
655 Support for StrongARM 11x0 based boards.
658 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
660 select ARCH_HAS_CPUFREQ
662 select ARCH_USES_GETTIMEOFFSET
663 select HAVE_S3C2410_I2C
665 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
666 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
667 the Samsung SMDK2410 development board (and derivatives).
669 Note, the S3C2416 and the S3C2450 are so close that they even share
670 the same SoC ID code. This means that there is no seperate machine
671 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
674 bool "Samsung S3C64XX"
680 select ARCH_USES_GETTIMEOFFSET
681 select ARCH_HAS_CPUFREQ
682 select ARCH_REQUIRE_GPIOLIB
683 select SAMSUNG_CLKSRC
684 select SAMSUNG_IRQ_VIC_TIMER
685 select SAMSUNG_IRQ_UART
686 select S3C_GPIO_TRACK
687 select S3C_GPIO_PULL_UPDOWN
688 select S3C_GPIO_CFG_S3C24XX
689 select S3C_GPIO_CFG_S3C64XX
691 select USB_ARCH_HAS_OHCI
692 select SAMSUNG_GPIOLIB_4BIT
693 select HAVE_S3C2410_I2C
694 select HAVE_S3C2410_WATCHDOG
696 Samsung S3C64XX series based systems
699 bool "Samsung S5P6440"
703 select HAVE_S3C2410_WATCHDOG
704 select ARCH_USES_GETTIMEOFFSET
705 select HAVE_S3C2410_I2C
708 Samsung S5P6440 CPU based systems
711 bool "Samsung S5P6442"
715 select ARCH_USES_GETTIMEOFFSET
716 select HAVE_S3C2410_WATCHDOG
718 Samsung S5P6442 CPU based systems
721 bool "Samsung S5PC100"
725 select ARM_L1_CACHE_SHIFT_6
726 select ARCH_USES_GETTIMEOFFSET
727 select HAVE_S3C2410_I2C
729 select HAVE_S3C2410_WATCHDOG
731 Samsung S5PC100 series based systems
734 bool "Samsung S5PV210/S5PC110"
738 select ARM_L1_CACHE_SHIFT_6
739 select ARCH_USES_GETTIMEOFFSET
740 select HAVE_S3C2410_I2C
742 select HAVE_S3C2410_WATCHDOG
744 Samsung S5PV210/S5PC110 series based systems
747 bool "Samsung S5PV310/S5PC210"
751 select GENERIC_CLOCKEVENTS
753 Samsung S5PV310 series based systems
762 select ARCH_USES_GETTIMEOFFSET
764 Support for the StrongARM based Digital DNARD machine, also known
765 as "Shark" (<http://www.shark-linux.de/shark.html>).
770 select ARCH_SPARSEMEM_ENABLE if !LH7A40X_CONTIGMEM
771 select ARCH_USES_GETTIMEOFFSET
773 Say Y here for systems based on one of the Sharp LH7A40X
774 System on a Chip processors. These CPUs include an ARM922T
775 core with a wide array of integrated devices for
776 hand-held and low-power applications.
779 bool "ST-Ericsson U300 Series"
785 select GENERIC_CLOCKEVENTS
789 Support for ST-Ericsson U300 series mobile platforms.
792 bool "ST-Ericsson U8500 Series"
795 select GENERIC_CLOCKEVENTS
797 select ARCH_REQUIRE_GPIOLIB
799 Support for ST-Ericsson's Ux500 architecture
802 bool "STMicroelectronics Nomadik"
807 select GENERIC_CLOCKEVENTS
808 select ARCH_REQUIRE_GPIOLIB
810 Support for the Nomadik platform by ST-Ericsson
814 select GENERIC_CLOCKEVENTS
815 select ARCH_REQUIRE_GPIOLIB
819 select GENERIC_ALLOCATOR
820 select ARCH_HAS_HOLES_MEMORYMODEL
822 Support for TI's DaVinci platform.
827 select ARCH_REQUIRE_GPIOLIB
828 select ARCH_HAS_CPUFREQ
829 select GENERIC_CLOCKEVENTS
830 select ARCH_HAS_HOLES_MEMORYMODEL
832 Support for TI's OMAP platform (OMAP1 and OMAP2).
835 bool "Rockchip Soc Rk29"
839 select HAVE_SCHED_CLOCK
840 select ARCH_HAS_CPUFREQ
842 select GENERIC_CLOCKEVENTS
843 select ARCH_REQUIRE_GPIOLIB
848 select ARM_L1_CACHE_SHIFT_6
850 Support for Rockchip RK29 soc.
855 select ARCH_REQUIRE_GPIOLIB
857 select GENERIC_CLOCKEVENTS
860 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
865 # This is sorted alphabetically by mach-* pathname. However, plat-*
866 # Kconfigs may be included either alphabetically (according to the
867 # plat- suffix) or along side the corresponding mach-* source.
869 source "arch/arm/mach-aaec2000/Kconfig"
871 source "arch/arm/mach-at91/Kconfig"
873 source "arch/arm/mach-bcmring/Kconfig"
875 source "arch/arm/mach-clps711x/Kconfig"
877 source "arch/arm/mach-cns3xxx/Kconfig"
879 source "arch/arm/mach-davinci/Kconfig"
881 source "arch/arm/mach-dove/Kconfig"
883 source "arch/arm/mach-ep93xx/Kconfig"
885 source "arch/arm/mach-footbridge/Kconfig"
887 source "arch/arm/mach-gemini/Kconfig"
889 source "arch/arm/mach-h720x/Kconfig"
891 source "arch/arm/mach-integrator/Kconfig"
893 source "arch/arm/mach-iop32x/Kconfig"
895 source "arch/arm/mach-iop33x/Kconfig"
897 source "arch/arm/mach-iop13xx/Kconfig"
899 source "arch/arm/mach-ixp4xx/Kconfig"
901 source "arch/arm/mach-ixp2000/Kconfig"
903 source "arch/arm/mach-ixp23xx/Kconfig"
905 source "arch/arm/mach-kirkwood/Kconfig"
907 source "arch/arm/mach-ks8695/Kconfig"
909 source "arch/arm/mach-lh7a40x/Kconfig"
911 source "arch/arm/mach-loki/Kconfig"
913 source "arch/arm/mach-lpc32xx/Kconfig"
915 source "arch/arm/mach-msm/Kconfig"
917 source "arch/arm/mach-mv78xx0/Kconfig"
919 source "arch/arm/plat-mxc/Kconfig"
921 source "arch/arm/mach-netx/Kconfig"
923 source "arch/arm/mach-nomadik/Kconfig"
924 source "arch/arm/plat-nomadik/Kconfig"
926 source "arch/arm/mach-ns9xxx/Kconfig"
928 source "arch/arm/mach-nuc93x/Kconfig"
930 source "arch/arm/plat-omap/Kconfig"
932 source "arch/arm/mach-omap1/Kconfig"
934 source "arch/arm/mach-omap2/Kconfig"
936 source "arch/arm/mach-orion5x/Kconfig"
938 source "arch/arm/mach-pxa/Kconfig"
939 source "arch/arm/plat-pxa/Kconfig"
941 source "arch/arm/mach-mmp/Kconfig"
943 source "arch/arm/mach-realview/Kconfig"
945 source "arch/arm/mach-rk29/Kconfig"
947 source "arch/arm/mach-sa1100/Kconfig"
949 source "arch/arm/plat-samsung/Kconfig"
950 source "arch/arm/plat-s3c24xx/Kconfig"
951 source "arch/arm/plat-s5p/Kconfig"
953 source "arch/arm/plat-spear/Kconfig"
956 source "arch/arm/mach-s3c2400/Kconfig"
957 source "arch/arm/mach-s3c2410/Kconfig"
958 source "arch/arm/mach-s3c2412/Kconfig"
959 source "arch/arm/mach-s3c2416/Kconfig"
960 source "arch/arm/mach-s3c2440/Kconfig"
961 source "arch/arm/mach-s3c2443/Kconfig"
965 source "arch/arm/mach-s3c64xx/Kconfig"
968 source "arch/arm/mach-s5p6440/Kconfig"
970 source "arch/arm/mach-s5p6442/Kconfig"
972 source "arch/arm/mach-s5pc100/Kconfig"
974 source "arch/arm/mach-s5pv210/Kconfig"
976 source "arch/arm/mach-s5pv310/Kconfig"
978 source "arch/arm/mach-shmobile/Kconfig"
980 source "arch/arm/plat-stmp3xxx/Kconfig"
982 source "arch/arm/mach-tegra/Kconfig"
984 source "arch/arm/mach-u300/Kconfig"
986 source "arch/arm/mach-ux500/Kconfig"
988 source "arch/arm/mach-versatile/Kconfig"
990 source "arch/arm/mach-vexpress/Kconfig"
992 source "arch/arm/mach-w90x900/Kconfig"
994 # Definitions to make life easier
1000 select GENERIC_CLOCKEVENTS
1008 config PLAT_VERSATILE
1011 config ARM_TIMER_SP804
1014 source arch/arm/mm/Kconfig
1017 bool "Enable iWMMXt support"
1018 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK
1019 default y if PXA27x || PXA3xx || ARCH_MMP
1021 Enable support for iWMMXt context switching at run time if
1022 running on a CPU that supports it.
1024 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1027 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1031 depends on (CPU_V6 || CPU_V7 || XSCALE_PMU) && \
1032 (!ARCH_OMAP3 || OMAP3_EMU)
1037 source "arch/arm/Kconfig-nommu"
1040 config ARM_ERRATA_411920
1041 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1042 depends on CPU_V6 && !SMP
1044 Invalidation of the Instruction Cache operation can
1045 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1046 It does not affect the MPCore. This option enables the ARM Ltd.
1047 recommended workaround.
1049 config ARM_ERRATA_430973
1050 bool "ARM errata: Stale prediction on replaced interworking branch"
1053 This option enables the workaround for the 430973 Cortex-A8
1054 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1055 interworking branch is replaced with another code sequence at the
1056 same virtual address, whether due to self-modifying code or virtual
1057 to physical address re-mapping, Cortex-A8 does not recover from the
1058 stale interworking branch prediction. This results in Cortex-A8
1059 executing the new code sequence in the incorrect ARM or Thumb state.
1060 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1061 and also flushes the branch target cache at every context switch.
1062 Note that setting specific bits in the ACTLR register may not be
1063 available in non-secure mode.
1065 config ARM_ERRATA_458693
1066 bool "ARM errata: Processor deadlock when a false hazard is created"
1069 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1070 erratum. For very specific sequences of memory operations, it is
1071 possible for a hazard condition intended for a cache line to instead
1072 be incorrectly associated with a different cache line. This false
1073 hazard might then cause a processor deadlock. The workaround enables
1074 the L1 caching of the NEON accesses and disables the PLD instruction
1075 in the ACTLR register. Note that setting specific bits in the ACTLR
1076 register may not be available in non-secure mode.
1078 config ARM_ERRATA_460075
1079 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1082 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1083 erratum. Any asynchronous access to the L2 cache may encounter a
1084 situation in which recent store transactions to the L2 cache are lost
1085 and overwritten with stale memory contents from external memory. The
1086 workaround disables the write-allocate mode for the L2 cache via the
1087 ACTLR register. Note that setting specific bits in the ACTLR register
1088 may not be available in non-secure mode.
1090 config ARM_ERRATA_742230
1091 bool "ARM errata: DMB operation may be faulty"
1092 depends on CPU_V7 && SMP
1094 This option enables the workaround for the 742230 Cortex-A9
1095 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1096 between two write operations may not ensure the correct visibility
1097 ordering of the two writes. This workaround sets a specific bit in
1098 the diagnostic register of the Cortex-A9 which causes the DMB
1099 instruction to behave as a DSB, ensuring the correct behaviour of
1102 config ARM_ERRATA_742231
1103 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1104 depends on CPU_V7 && SMP
1106 This option enables the workaround for the 742231 Cortex-A9
1107 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1108 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1109 accessing some data located in the same cache line, may get corrupted
1110 data due to bad handling of the address hazard when the line gets
1111 replaced from one of the CPUs at the same time as another CPU is
1112 accessing it. This workaround sets specific bits in the diagnostic
1113 register of the Cortex-A9 which reduces the linefill issuing
1114 capabilities of the processor.
1116 config PL310_ERRATA_588369
1117 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1118 depends on CACHE_L2X0 && ARCH_OMAP4
1120 The PL310 L2 cache controller implements three types of Clean &
1121 Invalidate maintenance operations: by Physical Address
1122 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1123 They are architecturally defined to behave as the execution of a
1124 clean operation followed immediately by an invalidate operation,
1125 both performing to the same memory location. This functionality
1126 is not correctly implemented in PL310 as clean lines are not
1127 invalidated as a result of these operations. Note that this errata
1128 uses Texas Instrument's secure monitor api.
1130 config ARM_ERRATA_720789
1131 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1132 depends on CPU_V7 && SMP
1134 This option enables the workaround for the 720789 Cortex-A9 (prior to
1135 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1136 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1137 As a consequence of this erratum, some TLB entries which should be
1138 invalidated are not, resulting in an incoherency in the system page
1139 tables. The workaround changes the TLB flushing routines to invalidate
1140 entries regardless of the ASID.
1142 config ARM_ERRATA_743622
1143 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1146 This option enables the workaround for the 743622 Cortex-A9
1147 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1148 optimisation in the Cortex-A9 Store Buffer may lead to data
1149 corruption. This workaround sets a specific bit in the diagnostic
1150 register of the Cortex-A9 which disables the Store Buffer
1151 optimisation, preventing the defect from occurring. This has no
1152 visible impact on the overall performance or power consumption of the
1157 source "arch/arm/common/Kconfig"
1167 Find out whether you have ISA slots on your motherboard. ISA is the
1168 name of a bus system, i.e. the way the CPU talks to the other stuff
1169 inside your box. Other bus systems are PCI, EISA, MicroChannel
1170 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1171 newer boards don't support it. If you have ISA, say Y, otherwise N.
1173 # Select ISA DMA controller support
1178 # Select ISA DMA interface
1183 bool "PCI support" if ARCH_INTEGRATOR_AP || ARCH_VERSATILE_PB || ARCH_IXP4XX || ARCH_KS8695 || MACH_ARMCORE || ARCH_CNS3XXX
1185 Find out whether you have a PCI motherboard. PCI is the name of a
1186 bus system, i.e. the way the CPU talks to the other stuff inside
1187 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1188 VESA. If you have PCI, say Y, otherwise N.
1197 # Select the host bridge type
1198 config PCI_HOST_VIA82C505
1200 depends on PCI && ARCH_SHARK
1203 config PCI_HOST_ITE8152
1205 depends on PCI && MACH_ARMCORE
1209 source "drivers/pci/Kconfig"
1211 source "drivers/pcmcia/Kconfig"
1215 menu "Kernel Features"
1217 source "kernel/time/Kconfig"
1220 bool "Symmetric Multi-Processing (EXPERIMENTAL)"
1221 depends on EXPERIMENTAL && (REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP ||\
1222 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 ||\
1223 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
1224 depends on GENERIC_CLOCKEVENTS
1225 select USE_GENERIC_SMP_HELPERS
1226 select HAVE_ARM_SCU if ARCH_REALVIEW || ARCH_OMAP4 || ARCH_S5PV310 ||\
1227 ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4
1229 This enables support for systems with more than one CPU. If you have
1230 a system with only one CPU, like most personal computers, say N. If
1231 you have a system with more than one CPU, say Y.
1233 If you say N here, the kernel will run on single and multiprocessor
1234 machines, but will use only one CPU of a multiprocessor machine. If
1235 you say Y here, the kernel will run on many, but not all, single
1236 processor machines. On a single processor machine, the kernel will
1237 run faster if you say N here.
1239 See also <file:Documentation/i386/IO-APIC.txt>,
1240 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1241 <http://www.linuxdoc.org/docs.html#howto>.
1243 If you don't know what to do here, say N.
1249 This option enables support for the ARM system coherency unit
1255 This options enables support for the ARM timer and watchdog unit
1258 prompt "Memory split"
1261 Select the desired split between kernel and user memory.
1263 If you are not absolutely sure what you are doing, leave this
1267 bool "3G/1G user/kernel split"
1269 bool "2G/2G user/kernel split"
1271 bool "1G/3G user/kernel split"
1276 default 0x40000000 if VMSPLIT_1G
1277 default 0x80000000 if VMSPLIT_2G
1281 int "Maximum number of CPUs (2-32)"
1287 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1288 depends on SMP && HOTPLUG && EXPERIMENTAL
1290 Say Y here to experiment with turning CPUs off and on. CPUs
1291 can be controlled through /sys/devices/system/cpu.
1294 bool "Use local timer interrupts"
1295 depends on SMP && (REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || \
1296 REALVIEW_EB_A9MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1297 ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4)
1299 select HAVE_ARM_TWD if ARCH_REALVIEW || ARCH_OMAP4 || ARCH_S5PV310 || \
1300 ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS
1302 Enable support for local timers on SMP platforms, rather then the
1303 legacy IPI broadcast method. Local timers allows the system
1304 accounting to be spread across the timer interval, preventing a
1305 "thundering herd" at every timer tick.
1307 source kernel/Kconfig.preempt
1311 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P6440 || \
1312 ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
1313 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1314 default AT91_TIMER_HZ if ARCH_AT91
1315 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1318 config THUMB2_KERNEL
1319 bool "Compile the kernel in Thumb-2 mode"
1320 depends on CPU_V7 && EXPERIMENTAL
1322 select ARM_ASM_UNIFIED
1324 By enabling this option, the kernel will be compiled in
1325 Thumb-2 mode. A compiler/assembler that understand the unified
1326 ARM-Thumb syntax is needed.
1330 config ARM_ASM_UNIFIED
1334 bool "Use the ARM EABI to compile the kernel"
1336 This option allows for the kernel to be compiled using the latest
1337 ARM ABI (aka EABI). This is only useful if you are using a user
1338 space environment that is also compiled with EABI.
1340 Since there are major incompatibilities between the legacy ABI and
1341 EABI, especially with regard to structure member alignment, this
1342 option also changes the kernel syscall calling convention to
1343 disambiguate both ABIs and allow for backward compatibility support
1344 (selected with CONFIG_OABI_COMPAT).
1346 To use this you need GCC version 4.0.0 or later.
1349 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1350 depends on AEABI && EXPERIMENTAL
1353 This option preserves the old syscall interface along with the
1354 new (ARM EABI) one. It also provides a compatibility layer to
1355 intercept syscalls that have structure arguments which layout
1356 in memory differs between the legacy ABI and the new ARM EABI
1357 (only for non "thumb" binaries). This option adds a tiny
1358 overhead to all syscalls and produces a slightly larger kernel.
1359 If you know you'll be using only pure EABI user space then you
1360 can say N here. If this option is not selected and you attempt
1361 to execute a legacy ABI binary then the result will be
1362 UNPREDICTABLE (in fact it can be predicted that it won't work
1363 at all). If in doubt say Y.
1365 config ARCH_HAS_HOLES_MEMORYMODEL
1368 config ARCH_SPARSEMEM_ENABLE
1371 config ARCH_SPARSEMEM_DEFAULT
1372 def_bool ARCH_SPARSEMEM_ENABLE
1374 config ARCH_SELECT_MEMORY_MODEL
1375 def_bool ARCH_SPARSEMEM_ENABLE
1378 bool "High Memory Support (EXPERIMENTAL)"
1379 depends on MMU && EXPERIMENTAL
1381 The address space of ARM processors is only 4 Gigabytes large
1382 and it has to accommodate user address space, kernel address
1383 space as well as some memory mapped IO. That means that, if you
1384 have a large amount of physical memory and/or IO, not all of the
1385 memory can be "permanently mapped" by the kernel. The physical
1386 memory that is not permanently mapped is called "high memory".
1388 Depending on the selected kernel/user memory split, minimum
1389 vmalloc space and actual amount of RAM, you may not need this
1390 option which should result in a slightly faster kernel.
1395 bool "Allocate 2nd-level pagetables from highmem"
1397 depends on !OUTER_CACHE
1399 config HW_PERF_EVENTS
1400 bool "Enable hardware performance counter support for perf events"
1401 depends on PERF_EVENTS && CPU_HAS_PMU
1404 Enable hardware performance counter support for perf events. If
1405 disabled, perf events will use software events only.
1410 This enables support for sparse irqs. This is useful in general
1411 as most CPUs have a fairly sparse array of IRQ vectors, which
1412 the irq_desc then maps directly on to. Systems with a high
1413 number of off-chip IRQs will want to treat this as
1414 experimental until they have been independently verified.
1418 config FORCE_MAX_ZONEORDER
1419 int "Maximum zone order" if ARCH_SHMOBILE
1420 range 11 64 if ARCH_SHMOBILE
1421 default "9" if SA1111
1424 The kernel memory allocator divides physically contiguous memory
1425 blocks into "zones", where each zone is a power of two number of
1426 pages. This option selects the largest power of two that the kernel
1427 keeps in the memory allocator. If you need to allocate very large
1428 blocks of physically contiguous memory, then you may need to
1429 increase this value.
1431 This config option is actually maximum order plus one. For example,
1432 a value of 11 means that the largest free memory block is 2^10 pages.
1435 bool "Timer and CPU usage LEDs"
1436 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1437 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1438 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1439 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1440 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1441 ARCH_AT91 || ARCH_DAVINCI || \
1442 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1444 If you say Y here, the LEDs on your machine will be used
1445 to provide useful information about your current system status.
1447 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1448 be able to select which LEDs are active using the options below. If
1449 you are compiling a kernel for the EBSA-110 or the LART however, the
1450 red LED will simply flash regularly to indicate that the system is
1451 still functional. It is safe to say Y here if you have a CATS
1452 system, but the driver will do nothing.
1455 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1456 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1457 || MACH_OMAP_PERSEUS2
1459 depends on !GENERIC_CLOCKEVENTS
1460 default y if ARCH_EBSA110
1462 If you say Y here, one of the system LEDs (the green one on the
1463 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1464 will flash regularly to indicate that the system is still
1465 operational. This is mainly useful to kernel hackers who are
1466 debugging unstable kernels.
1468 The LART uses the same LED for both Timer LED and CPU usage LED
1469 functions. You may choose to use both, but the Timer LED function
1470 will overrule the CPU usage LED.
1473 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1475 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1476 || MACH_OMAP_PERSEUS2
1479 If you say Y here, the red LED will be used to give a good real
1480 time indication of CPU usage, by lighting whenever the idle task
1481 is not currently executing.
1483 The LART uses the same LED for both Timer LED and CPU usage LED
1484 functions. You may choose to use both, but the Timer LED function
1485 will overrule the CPU usage LED.
1487 config ALIGNMENT_TRAP
1489 depends on CPU_CP15_MMU
1490 default y if !ARCH_EBSA110
1491 select HAVE_PROC_CPU if PROC_FS
1493 ARM processors cannot fetch/store information which is not
1494 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1495 address divisible by 4. On 32-bit ARM processors, these non-aligned
1496 fetch/store instructions will be emulated in software if you say
1497 here, which has a severe performance impact. This is necessary for
1498 correct operation of some network protocols. With an IP-only
1499 configuration it is safe to say N, otherwise say Y.
1501 config UACCESS_WITH_MEMCPY
1502 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1503 depends on MMU && EXPERIMENTAL
1504 default y if CPU_FEROCEON
1506 Implement faster copy_to_user and clear_user methods for CPU
1507 cores where a 8-word STM instruction give significantly higher
1508 memory write throughput than a sequence of individual 32bit stores.
1510 A possible side effect is a slight increase in scheduling latency
1511 between threads sharing the same address space if they invoke
1512 such copy operations with large buffers.
1514 However, if the CPU data cache is using a write-allocate mode,
1515 this option is unlikely to provide any performance gain.
1517 config CC_STACKPROTECTOR
1518 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1520 This option turns on the -fstack-protector GCC feature. This
1521 feature puts, at the beginning of functions, a canary value on
1522 the stack just before the return address, and validates
1523 the value just before actually returning. Stack based buffer
1524 overflows (that need to overwrite this return address) now also
1525 overwrite the canary, which gets detected and the attack is then
1526 neutralized via a kernel panic.
1527 This feature requires gcc version 4.2 or above.
1529 config DEPRECATED_PARAM_STRUCT
1530 bool "Provide old way to pass kernel parameters"
1532 This was deprecated in 2001 and announced to live on for 5 years.
1533 Some old boot loaders still use this way.
1539 # Compressed boot loader in ROM. Yes, we really want to ask about
1540 # TEXT and BSS so we preserve their values in the config files.
1541 config ZBOOT_ROM_TEXT
1542 hex "Compressed ROM boot loader base address"
1545 The physical address at which the ROM-able zImage is to be
1546 placed in the target. Platforms which normally make use of
1547 ROM-able zImage formats normally set this to a suitable
1548 value in their defconfig file.
1550 If ZBOOT_ROM is not enabled, this has no effect.
1552 config ZBOOT_ROM_BSS
1553 hex "Compressed ROM boot loader BSS address"
1556 The base address of an area of read/write memory in the target
1557 for the ROM-able zImage which must be available while the
1558 decompressor is running. It must be large enough to hold the
1559 entire decompressed kernel plus an additional 128 KiB.
1560 Platforms which normally make use of ROM-able zImage formats
1561 normally set this to a suitable value in their defconfig file.
1563 If ZBOOT_ROM is not enabled, this has no effect.
1566 bool "Compressed boot loader in ROM/flash"
1567 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1569 Say Y here if you intend to execute your compressed kernel image
1570 (zImage) directly from ROM or flash. If unsure, say N.
1573 string "Default kernel command string"
1576 On some architectures (EBSA110 and CATS), there is currently no way
1577 for the boot loader to pass arguments to the kernel. For these
1578 architectures, you should supply some command-line options at build
1579 time by entering them here. As a minimum, you should specify the
1580 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1582 config CMDLINE_FORCE
1583 bool "Always use the default kernel command string"
1584 depends on CMDLINE != ""
1586 Always use the default kernel command string, even if the boot
1587 loader passes other arguments to the kernel.
1588 This is useful if you cannot or don't want to change the
1589 command-line options your boot loader passes to the kernel.
1594 bool "Kernel Execute-In-Place from ROM"
1595 depends on !ZBOOT_ROM
1597 Execute-In-Place allows the kernel to run from non-volatile storage
1598 directly addressable by the CPU, such as NOR flash. This saves RAM
1599 space since the text section of the kernel is not loaded from flash
1600 to RAM. Read-write sections, such as the data section and stack,
1601 are still copied to RAM. The XIP kernel is not compressed since
1602 it has to run directly from flash, so it will take more space to
1603 store it. The flash address used to link the kernel object files,
1604 and for storing it, is configuration dependent. Therefore, if you
1605 say Y here, you must know the proper physical address where to
1606 store the kernel image depending on your own flash memory usage.
1608 Also note that the make target becomes "make xipImage" rather than
1609 "make zImage" or "make Image". The final kernel binary to put in
1610 ROM memory will be arch/arm/boot/xipImage.
1614 config XIP_PHYS_ADDR
1615 hex "XIP Kernel Physical Location"
1616 depends on XIP_KERNEL
1617 default "0x00080000"
1619 This is the physical address in your flash memory the kernel will
1620 be linked for and stored to. This address is dependent on your
1624 bool "Kexec system call (EXPERIMENTAL)"
1625 depends on EXPERIMENTAL
1627 kexec is a system call that implements the ability to shutdown your
1628 current kernel, and to start another kernel. It is like a reboot
1629 but it is independent of the system firmware. And like a reboot
1630 you can start any kernel with it, not just Linux.
1632 It is an ongoing process to be certain the hardware in a machine
1633 is properly shutdown, so do not be surprised if this code does not
1634 initially work for you. It may help to enable device hotplugging
1638 bool "Export atags in procfs"
1642 Should the atags used to boot the kernel be exported in an "atags"
1643 file in procfs. Useful with kexec.
1645 config AUTO_ZRELADDR
1646 bool "Auto calculation of the decompressed kernel image address"
1647 depends on !ZBOOT_ROM && !ARCH_U300
1649 ZRELADDR is the physical address where the decompressed kernel
1650 image will be placed. If AUTO_ZRELADDR is selected, the address
1651 will be determined at run-time by masking the current IP with
1652 0xf8000000. This assumes the zImage being placed in the first 128MB
1653 from start of memory.
1657 menu "CPU Power Management"
1661 source "drivers/cpufreq/Kconfig"
1663 config CPU_FREQ_SA1100
1666 config CPU_FREQ_SA1110
1669 config CPU_FREQ_INTEGRATOR
1670 tristate "CPUfreq driver for ARM Integrator CPUs"
1671 depends on ARCH_INTEGRATOR && CPU_FREQ
1674 This enables the CPUfreq driver for ARM Integrator CPUs.
1676 For details, take a look at <file:Documentation/cpu-freq>.
1682 depends on CPU_FREQ && ARCH_PXA && PXA25x
1684 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1686 config CPU_FREQ_S3C64XX
1687 bool "CPUfreq support for Samsung S3C64XX CPUs"
1688 depends on CPU_FREQ && CPU_S3C6410
1693 Internal configuration node for common cpufreq on Samsung SoC
1695 config CPU_FREQ_S3C24XX
1696 bool "CPUfreq driver for Samsung S3C24XX series CPUs"
1697 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1700 This enables the CPUfreq driver for the Samsung S3C24XX family
1703 For details, take a look at <file:Documentation/cpu-freq>.
1707 config CPU_FREQ_S3C24XX_PLL
1708 bool "Support CPUfreq changing of PLL frequency"
1709 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1711 Compile in support for changing the PLL frequency from the
1712 S3C24XX series CPUfreq driver. The PLL takes time to settle
1713 after a frequency change, so by default it is not enabled.
1715 This also means that the PLL tables for the selected CPU(s) will
1716 be built which may increase the size of the kernel image.
1718 config CPU_FREQ_S3C24XX_DEBUG
1719 bool "Debug CPUfreq Samsung driver core"
1720 depends on CPU_FREQ_S3C24XX
1722 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
1724 config CPU_FREQ_S3C24XX_IODEBUG
1725 bool "Debug CPUfreq Samsung driver IO timing"
1726 depends on CPU_FREQ_S3C24XX
1728 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
1730 config CPU_FREQ_S3C24XX_DEBUGFS
1731 bool "Export debugfs for CPUFreq"
1732 depends on CPU_FREQ_S3C24XX && DEBUG_FS
1734 Export status information via debugfs.
1738 source "drivers/cpuidle/Kconfig"
1742 menu "Floating point emulation"
1744 comment "At least one emulation must be selected"
1747 bool "NWFPE math emulation"
1748 depends on !AEABI || OABI_COMPAT
1750 Say Y to include the NWFPE floating point emulator in the kernel.
1751 This is necessary to run most binaries. Linux does not currently
1752 support floating point hardware so you need to say Y here even if
1753 your machine has an FPA or floating point co-processor podule.
1755 You may say N here if you are going to load the Acorn FPEmulator
1756 early in the bootup.
1759 bool "Support extended precision"
1760 depends on FPE_NWFPE
1762 Say Y to include 80-bit support in the kernel floating-point
1763 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1764 Note that gcc does not generate 80-bit operations by default,
1765 so in most cases this option only enlarges the size of the
1766 floating point emulator without any good reason.
1768 You almost surely want to say N here.
1771 bool "FastFPE math emulation (EXPERIMENTAL)"
1772 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
1774 Say Y here to include the FAST floating point emulator in the kernel.
1775 This is an experimental much faster emulator which now also has full
1776 precision for the mantissa. It does not support any exceptions.
1777 It is very simple, and approximately 3-6 times faster than NWFPE.
1779 It should be sufficient for most programs. It may be not suitable
1780 for scientific calculations, but you have to check this for yourself.
1781 If you do not feel you need a faster FP emulation you should better
1785 bool "VFP-format floating point maths"
1786 depends on CPU_V6 || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1788 Say Y to include VFP support code in the kernel. This is needed
1789 if your hardware includes a VFP unit.
1791 Please see <file:Documentation/arm/VFP/release-notes.txt> for
1792 release notes and additional status information.
1794 Say N if your target does not have VFP hardware.
1802 bool "Advanced SIMD (NEON) Extension support"
1803 depends on VFPv3 && CPU_V7
1805 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1810 menu "Userspace binary formats"
1812 source "fs/Kconfig.binfmt"
1815 tristate "RISC OS personality"
1818 Say Y here to include the kernel code necessary if you want to run
1819 Acorn RISC OS/Arthur binaries under Linux. This code is still very
1820 experimental; if this sounds frightening, say N and sleep in peace.
1821 You can also say M here to compile this support as a module (which
1822 will be called arthur).
1826 menu "Power management options"
1828 source "kernel/power/Kconfig"
1830 config ARCH_SUSPEND_POSSIBLE
1835 source "net/Kconfig"
1837 source "drivers/Kconfig"
1841 source "arch/arm/Kconfig.debug"
1843 source "security/Kconfig"
1845 source "crypto/Kconfig"
1847 source "lib/Kconfig"